Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
  • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0167—Manufacturing their channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Definitions

• the present invention relates to micro-miniaturized semiconductor devices comprising transistors on silicon-germanium.
• the present invention is particularly applicable in fabricating transistors with enhanced channel carrier mobility.
• CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency.
• Current technology utilizes crystalline semiconductor wafers as substrates, such as a lightly p- doped epitaxial ("epi") layer of silicon (Si) grown on a heavily-doped, crystalline Si Substrate.
• epi epitaxial
• the low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n- type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
• the use of the very thin epi layers, i.e., several ⁇ m thick, is made possible by utilizing shallow trench isolation ("STI"), which advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer.
• STI shallow trench isolation
• STI allows for closer spacing of adjacent active areas by avoiding the "bird's beak" formed at the edge of each LOCOS isolation structure.
• STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
• Substrates based on "strained silicon” have attracted interest as a semiconductor material which provides increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices with higher operating speeds, enhanced performance characteristics, and lower power consumption.
• Si layer is grown on a relaxed, graded composition of silicon-germanium (Si-Ge) buffer layer several microns thick, which Si-Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer.
• Si-Ge buffer layer typically contains 12 to 25 at.% Ge.
• Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Si-Ge buffer layer, to align with the greater lattice constant (spacing) of Si and Ge atoms therein (relative to pure Si).
• Si-Ge silicon-Ge
• Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow.
• electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si.
• Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
• Conventional practices based on strained silicon technology also involve epitaxially growing a relaxed silicon layer on a tensilely stressed silicon layer which is subsequently doped to form relaxed source/drain regions in the relaxed silicon layer.
• the mobility of electrons is faster than the mobility of holes in conventional bulk silicon substrates.
• the drive current of the PMOS transistor is less than the drive current of the NMOS transistor creating an imbalance.
• This imbalance is exacerbated in CMOS transistors fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si on Si-Ge, because the increase in electron mobility is greater than the increase in hole mobility.
• a strained lattice semiconductor substrate e.g., strained Si on Si-Ge
• An advantage of the present invention is a method of fabricating a semiconductor device comprising transistors on Si-Ge substrates with enhanced drive currents.
• Another advantage of the present invention is a semiconductor device comprising transistors based on Si-Ge substrates with enhanced drive currents. Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
• a semiconductor device comprising: a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si-Ge); a transistor comprising source/drain regions and a gate electrode over the substrate with a gate dielectric layer therebetween; and a stressed dielectric liner over side surfaces of the gate electrode and over the source/drain regions.
• Another advantage of the present invention is a method of manufacturing a semiconductor device, the method comprising: forming a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si-Ge); forming a transistor comprising source/drain regions and a gate electrode, having an upper surface and side surfaces, over the substrate with gate dielectric layer therebetween; and forming a stressed dielectric liner over the side surfaces of the gate electrode and over the source/drain regions.
• Si silicon
• Si-Ge silicon-germanium
• Embodiments of the present invention comprise forming dielectric sidewall spacers on side surfaces of the gate electrode, such as an oxide liner and a nitride layer thereon, epitaxially growing a relaxed Si layer on the strained Si layer, forming source/drain regions in the relaxed Si layer and then depositing the stressed dielectric liner on the sidewall spacers, on the relaxed source/drain regions and on a portion of the strained Si layer between the sidewall spacers and raised source/drain regions.
• dielectric sidewall spacers on side surfaces of the gate electrode, such as an oxide liner and a nitride layer thereon, epitaxially growing a relaxed Si layer on the strained Si layer, forming source/drain regions in the relaxed Si layer and then depositing the stressed dielectric liner on the sidewall spacers, on the relaxed source/drain regions and on a portion of the strained Si layer between the sidewall spacers and raised source/drain regions.
• Embodiments of the present invention also include forming dielectric sidewall spacers on side surfaces of the gate electrode, forming source/drain regions in the strained Si layer, forming a metal silicide layer on the upper surface of the gate electrode and a metal silicide layer on the source/drain regions, removing the dielectric sidewall spacers to expose a portion of the strained Si layer adjacent the side surfaces of the gate electrode, and then forming the stress dielectric liner on the metal silicide layer, on the upper surface of the gate electrode, on the side surfaces of the gate electrode, on the adjacent exposed portions of the strained Si layer, and on the silicide layer overlying the source/drain regions.
• the stressed dielectric liner exhibits high tensile stress. In embodiments of the present invention comprising P-channel transistors, the stressed dielectric liner exhibits high compressive stress.
• the stressed dielectric liner may comprise a layer of silicon nitride, silicon carbide or silicon oxynitride, at a thickness of about 200A to about lOOOA.
• Embodiments of the present invention include fabricating semiconductor devices comprising complimentary MOS (CMOS) transistors, with a compressive film on the PMOS transistor and a tensile film on the NMOS transistor.
• CMOS complimentary MOS
• process flow includes depositing a compressive stressed nitride film over both the NMOS and PMOS transistors, and then depositing a thin buffer film, such as an oxide or oxynitride film, over both the NMOS and PMOS transistors. Selective etching is then conducted to remove the oxide and compressive stressed nitride films from the NMOS transistor while masking the PMOS transistor. A tensile stressed nitride film is then deposited over both the NMOS and PMOS transistors, and then selectively etched away from the PMOS transistor.
• the resulting CMOS device comprises an NMOS transistor with a tensile stressed film thereon and a PMOS transistor with a compressive stress film thereon.
• Figs. 1 and 2 schematically illustrate sequential phases of a method in accordance with an embodiment of the present invention.
• Figs. 3 through 6 schematically illustrate sequential phases of a method in accordance with another embodiment of the present invention.
• Figs. 7 through 14 schematically illustrate sequential phases of a method in accordance with another embodiment of the present invention.
• similar features or elements are denoted by similar reference characters; in Figs. 3 through 6, similar features or elements are denoted by similar reference characters; and in Figs. 7 through 14, similar features or elements are denoted by similar reference characters.
• DESCRIPTION OF THE INVENTION Transistors built on Si-Ge substrates involve different considerations than those built on bulk silicon substrates.
• Si-Ge substrates are formed with a strained silicon layer having a thickness of about 200A to about 300A. Relaxed source/drain regions may be formed thereon at a thickness of up to about 400A. Thus, the thickness of the strained Si layer and drain/source regions together typically does not exceed 800A.
• the strained Si layer even together with a relaxed Si layer, is relatively transparent to the type of stress exhibited by a film deposited thereon. Accordingly, a tensile stressed layer deposited on a strained Si layer, or a relaxed Si layer formed on a strained Si layer, would also impart tensile stress to a channel region formed therein; and a compressive stressed layer deposited on such a thin Si layer or layers imparts compressive stress to a channel region formed therein; whereas, in bulk substrates, the opposite would occur.
• the present invention addresses and solves the problem of increasing the drive current of transistors based on strained Si substrates in a cost effective and efficient manner by significantly enhancing the channel carrier mobility.
• the present invention stems from the recognition that the channel carrier mobility of transistors based on strained Si substrates can be increased by applying a stress thereto.
• channel carrier mobility is enhanced by applying a stressed dielectric layer exhibiting high compressive stress for increasing hole mobility.
• channel carrier mobility is significantly increased by applying a stressed layer exhibiting high tensile stress for increasing electron mobility. Stressed dielectric layers may be applied to transistors wherein the source/drain regions are formed within the strained Si layer, and to transistors having relaxed source/drain regions formed on strained Si layers.
• the stressed dielectric layer may comprise silicon carbide, silicon nitride or silicon oxynitride, and may be deposited by plasma enhanced chemical vapor deposition (PECVD) at a thickness of about 200A to about 1000A.
• PECVD plasma enhanced chemical vapor deposition
• Conventional PECVD conditions may be employed for deposition of a highly compressive or highly tensile dielectric layer.
• high compressive stress both high frequency and low frequency power are applied.
• the low frequency power is significantly reduced.
• a tensile stress is applied to the underlying strained or relaxed Si layer.
• a compressive stress is applied to the underlying strained or relaxed Si layer.
• a stressed conformal silicon nitride layer exhibiting a high compressive stress may be deposited at: a silane (S1H 4 ) flow rate of 200 to 500 seem; a nitrogen (N 2 ) flow rate of 2,000 to 10,000 seem; an ammonia (NH 3 ) flow rate of 2,500 to 5,000 seem; a SiH 4 /NH 3 ratio of 0.2 to 0.04, a temperature of 350°C to 550°C; a pressure of 1 to 6 Torr; a high frequency power of 70 to 300 watts; a low frequency power of 20 to 60 watts and an electrode (shower head) spacing of 400 to 600 mils.
• S1H 4 silane
• N 2 nitrogen
• NH 3 ammonia
• SiH 4 /NH 3 ratio of 0.2 to 0.04
• a temperature of 350°C to 550°C a pressure of 1 to 6 Torr
• a silicon nitride layer exhibiting a high tensile stress may be deposited at a S1H 4 flow rate of 50 to 500 seem; an NH 3 flow rate of 1,500 to 5,000 seem; a N 2 flow rate of 4,000 to 30,000 seem; a SiH 4 NH 3 ratio of 0.2 to 0.04, a temperature of 350°C to 550°C, a pressure of 2 to 10 Torr; a high frequency power of 40 to 300 watts and a low frequency power of 0 to 10 watts.
• a dielectric layer exhibiting high tensile stress may be formed by depositing the dielectric layer by chemical vapor deposition and then treating the deposited dielectric layer with ultraviolet or electron beam radiation to increase its tensile stress.
• the stressed layer is applied at a relatively low temperature. Accordingly, the present invention enables deposition of a tensile or compressive stressed layer in transistors having nickel silicide layers formed on source/drain regions and gate electrodes, without exceeding the thermal stability limits of the nickel silicon layers.
• the present invention is also applicable to transistors comprising other metal silicides, such as cobalt silicide.
• a separate layer of silicon is deposited prior to depositing a layer of cobalt and implementing silicidation.
• An embodiment of the present invention is schematically illustrated in Figs. 1 through 6. Adverting to Fig. 1, a layer of strained Si 11 is formed on a layer of Si-Ge 10. It should be understood that Si layer 11 may be entirely strained or strained locally in the source/drain regions as in conventional practices, and that embodiments of the present invention encompass both types of strained Si layers.
• a gate electrode 12 is formed over strained Si layer 11 with a gate dielectric layer 13 therebetween.
• Sidewall spacers are then formed comprising an L-shaped oxide liner 14, e.g., silicon oxide, and a nitride layer 15, e.g., silicon nitride, thereon.
• a relaxed Si layer 16 is then epitaxially grown on strained Si layer 11 and source/drain regions formed therein, as by doping extending the source/drain regions into strained Si layer 11.
• a metal silicide layer 20, 20A such as nickel silicide, is formed on the upper surface of gate electrode 12 on an relaxed source/drain region 16, respectively.
• a stressed dielectric liner 21 is then formed on the sidewall spacers, silicides 20, 20A, and between the oxide liner 14 and relaxed source/drain region 16 on the Si layer 11.
• the stressed dielectric layer 21 imparts strain 20 to silicon layer 11 under the gate electrode and under the spacers, thereby advantageously increasing channel carrier mobility. In embodiments wherein the entire Si layer 11 is strained, the stressed dielectric layer further increases strain in the channel region under the gate electrode and spacers, thereby further increasing channel carrier mobility.
• Stressed dielectric layer 21 can be, for example, silicon nitride deposited by PECVD exhibiting a high compressive or tensile stress. Additional features illustrated in Fig.
• the stress applied by the highly stressed dielectric layer 21 enhances channel carrier mobility, thereby increasing the drive current of the transistor.
• Another embodiment of the present invention is schematically illustrated in Figs. 3 through 6. Adverting to Fig. 3, strained Si layer 31 is formed over Si-Ge layer 30. As in the previous discussed embodiment, Si layer 31 may be globally strained or locally strained under the source/drain regions. Gate electrode 32 is formed over strained Si layer 31 with a gate dielectric layer 33 therebetween.
• liner 34 may be deposited by ALD and may also comprise silicon nitride.
• Silicon oxide liner advantageously prevents consumption of the gate electrode by silicidation on the side surfaces thereof, and advantageously prevents a subsequently formed thin layer of nickel silicide on the silicon nitride sidewall spacers from contacting the nickel silicide contact layer on the upper surface of the gate electrode and/or from contacting the nickel silicide contact layers on the upper surface of the strained Si layer 31, thereby preventing nickel silicide bridging along the silicon nitride sidewall spacers. Silicon nitride spacers 35 are then formed on silicon oxide liner 34 as by employing PECVD followed by etching.
• silicidation is implemented, as by forming a layer of nickel silicide 40 on the upper surface of gate electrode 32, as illustrated in Fig. 4, and by forming a layer of nickel silicide 41 on the source/drain region formed in the strained Si layer 31 or strained portion of silicon layer 31.
• the liner and sidewall spacers are then removed exposing a portion of the upper surface of strained Si layer 31 between the silicide layers 41 and the side surfaces of gate electrode 32, with a very thin oxide layer thereon, e.g., less 5 ⁇ A, serving as a buffer layer.
• a highly stressed dielectric layer 50 is then deposited, such as a silicon nitride layer exhibiting high compressive stress, by PECVD, as shown in Fig. 6.
• the highly stressed dielectric layer 50 serves to increase channel hole mobility, thereby increasing the drive current.
• FIGs. 7 through 14 Adverting to Fig. 7, a CMOS device is schematically illustrated comprising an NMOS transistor portion at tire left and a PMOS transistor portion on the right, wherein similar features are denoted by similar reference characters.
• Strained Si layer 71 is formed over Si-Ge layer 70. As in previous discussed embodiments, Si layer 71 may be globally strained or locally strained in the source/drain regions.
• Gate electrode 72 is formed over strained Si layer 71 with a gate dielectric layer 73 therebetween.
• Silicon oxide liner 74 can be formed in the same manner as discussed with respect to silicon oxide liner 34 in Fig. 3.
• Silicon nitride spacers 75 are then formed on silicon oxide liner 74, as by employing PECVD followed by etching.
• silicidation is implemented, as by forming a layer of nickel silicide 76 on the upper surface of gate electrodes 72 and by forming a layer of nickel silicide 77 on the source/drain regions formed on the strained Si layer 71.
• liner 74 and sidewall spacer 75 are removed from each transistor exposing a portion of the upper surface of strained Si layer 71 between silicide layers 77 and the side surfaces of gate electrode 72.
• a highly compressive stressed silicon nitride film 90 having a compressive stressed greater than 1.5GPa, is then deposited over both the NMOS and PMOS transistors as illustrated in Fig. 9.
• Deposition of highly compressive stressed silicon nitride film 90 may be implemented at a temperature of about 400°C to about 480°C, at a SiH 4 flow rate of about 200 to about 300 seem, an NH 3 flow rate of about 3,000 to about 4,000 seem, a N 2 flow rate of about 3,500 to about 4,500 seem, a pressure of about 2 to about 6 TOIT, a shower head spacing of about 400 to about 600 mils, a high frequency RF power of about 60 to about 100 watts, a low frequency RF power of about 40 watts to about 90 watts, followed by NH 3 /N 2 plasma treatment with NH 3 at a flow rate of about 500 to about 1500 seem and with N 2 at a flow rate of about 2,000 to about 4,000 seem, at a high frequency RF power of about 100 watts to about 600 watts, and a low frequency RF power of about 20 watts to about 60 watts for about 20 to about 60 seconds.
• a thin oxide or oxynitride film 100 is deposited, as illustrated in Fig. 10, by a conventional CVD process. Typically oxide or oxynitride film 100 is deposited at a thickness of about 3 ⁇ A to about 6 ⁇ A.
• a mask 110 e.g., photoresist or hard mask is applied over the PMOS transistor, as illustrated in Fig. 11, and the oxide or oxynitride film 100 and high compressive stress silicon nitride film 90 removed from the NMOS transistor. Adverting to Fig.
• a highly tensile stressed silicon nitride film 120 having a tensile stress of greater than 1.5GPa, is then deposited over both the PMOS and NMOS transistors.
• Deposition of highly tensile stressed film 120 can be implemented at a temperature of about 400°C to about 480°C, a S1H 4 flow rate of about 40 to about 80 seem, and NH 3 flow rate of about 1,500 to about 2,500 seem, a N 2 flow rate- of about 20,000 to about 40,000 seem, a spacing (between substrate and shower head) of about 400 to about 600 mils, a pressure of about 2 to about 8 Torr, a high frequency power of about 40 to about 80 watts, and a low frequency power up to about 10 watts.
• a thin oxide or oxynitride film is then deposited by a conventional CVD process, as at a thickness of about 3 ⁇ A to about 6 ⁇ A.
• a mask 131 such as a photoresist or hard mask, is then applied over the NMOS transistor, and the oxide or oxynitride film 130 and the highly tensile stressed silicon nitride film 120 are selectively removed from the PMOS transistor stopping on the oxide or oxynitride film 100.
• the mask 131 is then removed, and the resulting structure is illustrated in Fig.
• CMOS device which comprises an oxide or oxynitride film 130 and a highly tensile stressed silicon nitride film 120 over the NMOS transistor and an oxide or oxynitride filmlOO and a highly compressive stressed silicon nitride film 90 over the PMOS transistor.
• the resulting CMOS device comprises both PMOS and NMOS transistors with increased channel carrier mobility and, hence, increased drive current.
• the present invention provides methodology enabling the fabrication of high quality, high operating speed, micro-miniaturized semiconductor devices based upon strained lattice technology, with maximized transistor drive currents.
• the inventive methodology can be practiced utilizing conventional processing techniques and instrumentalities at rates consistent with the throughput requirements of automated fabrication techniques, and is fully compatible with conventional process flow for the manufacture of high-density integrated semiconductor devices.
• the present invention enjoys industrial applicability in fabricating various types of semiconductor devices.
• the present invention enjoys particular industrial applicability in fabricating micro-miniaturized semiconductor devices with high operating speeds.
• numerous specific details are set forth, such as specific materials, structures, reactants, processes, etc., in order to provide a better understanding of the present invention.
• the present invention can be practiced without resorting to the details specifically set forth.
• well-known processing materials and techniques have not been described in detail in order not to unnecessarily obscure the present invention.

Landscapes

• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Formation Of Insulating Films (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=34966169

Family Applications (1)

Country Status (7)

Cited By (8)

Families Citing this family (103)

Citations (2)

Family Cites Families (15)

• 2004
  • 2004-05-05 US US10/838,330 patent/US7053400B2/en not_active Expired - Lifetime
• 2005
  • 2005-04-19 WO PCT/US2005/013239 patent/WO2005112127A1/en not_active Ceased
  • 2005-04-19 JP JP2007511390A patent/JP2007536736A/ja active Pending
  • 2005-04-19 CN CNB2005800140631A patent/CN100533766C/zh not_active Expired - Lifetime
  • 2005-04-19 DE DE112005001029.5T patent/DE112005001029B4/de not_active Expired - Lifetime
  • 2005-04-19 GB GB0621299A patent/GB2429116B/en not_active Expired - Lifetime
  • 2005-05-03 TW TW094114208A patent/TWI411100B/zh not_active IP Right Cessation
• 2006
  • 2006-04-25 US US11/410,062 patent/US20060208250A1/en not_active Abandoned

Patent Citations (2)

Non-Patent Citations (3)

Also Published As

Similar Documents

Legal Events