US7390729B2 - Method of fabricating a semiconductor device - Google Patents
Method of fabricating a semiconductor device Download PDFInfo
- Publication number
- US7390729B2 US7390729B2 US11/309,740 US30974006A US7390729B2 US 7390729 B2 US7390729 B2 US 7390729B2 US 30974006 A US30974006 A US 30974006A US 7390729 B2 US7390729 B2 US 7390729B2
- Authority
- US
- United States
- Prior art keywords
- layer
- fabricating
- spacer
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 107
- 229910052751 metal Inorganic materials 0.000 claims abstract description 80
- 239000002184 metal Substances 0.000 claims abstract description 80
- 125000006850 spacer group Chemical group 0.000 claims abstract description 63
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 58
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 238000004381 surface treatment Methods 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 34
- 238000000137 annealing Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 10
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 239000000243 solution Substances 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000001272 nitrous oxide Substances 0.000 claims description 5
- 239000007800 oxidant agent Substances 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 239000003929 acidic solution Substances 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 2
- 238000005530 etching Methods 0.000 description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000006557 surface reaction Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- OPTOQCQBJWTWPN-UHFFFAOYSA-N [Si].[Ge].[Si] Chemical compound [Si].[Ge].[Si] OPTOQCQBJWTWPN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- CODNYICXDISAEA-UHFFFAOYSA-N bromine monochloride Chemical compound BrCl CODNYICXDISAEA-UHFFFAOYSA-N 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- XTEGARKTQYYJKE-UHFFFAOYSA-N chloric acid Chemical compound OCl(=O)=O XTEGARKTQYYJKE-UHFFFAOYSA-N 0.000 description 1
- 229940005991 chloric acid Drugs 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- QWPPOHNGKGFGJK-UHFFFAOYSA-N hypochlorous acid Chemical compound ClO QWPPOHNGKGFGJK-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- the present invention relates to an integrated circuit and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device and a method of fabricating the same.
- a stress layer will be formed on the substrate to increase the mobility of electrons or holes in the channel of the MOS transistor.
- MOS metal oxide semiconductor
- a stress layer having compressive stress can be formed on the substrate, so as to generate the compressive stress along the channel direction in the p-type MOS transistor; and for an n-type MOS transistor, a stress layer having tensile stress can be formed on the substrate, so as to generate the tensile stress along the channel direction of the n-type transistor.
- the increase of the compressive stress or the tensile stress the mobility of holes or electrons in the channel is also increased, so as to increase the drive current, and further improve the performance of the device.
- FIGS. 6A ⁇ 6B are sectional flow charts of a method of fabricating a semiconductor device to improve the mobility of electrons or holes in the channel according to prior art.
- a MOS transistor 20 is formed on a substrate 10 , and metal silicide layers 22 and 24 are formed on the gate structure 13 and source/drain region 18 , respectively.
- an etching process is performed before the stress layer is formed, so as to reduce the width S 1 of the spacer 14 to S 2 , which allows the stress layer formed subsequently to be closer to the channel, thus the mobility of electrons or holes in the channel is increased.
- the metal silicide layers 22 and 24 are directly exposed to the etching environment without any protection, the metal silicide layers 22 and 24 will be damaged after the etching process, especially after the over etching, resulting in unsatisfactory sheet resistance.
- the present invention is to provide a semiconductor device and a method of fabricating the same, which improve the mobility of electrons or holes in the channel and prevent the metal silicide layers from being damaged during the subsequent etching process of reducing the width of the spacer.
- the present invention provides a method of fabricating a semiconductor device.
- a transistor is formed on a substrate.
- the transistor comprises a gate structure and a source/drain region, wherein the gate structure comprises a gate conductor layer over the substrate, a gate dielectric layer between the gate conductor layer and the substrate and a spacer on the side wall of the gate conductor layer.
- a metal silicide layer is formed on the surface of the gate conductor layer and the source/drain region of the transistor.
- a surface treatment process is performed to selectively form a protection layer on the metal silicide layer, and the material of the protection layer is different from that of the spacer on the side wall of the gate conductor layer.
- the spacer is partially removed, so as to reduce the width of the spacer, such that a space exists between the spacer and the metal silicide layer. Then, a stress layer is formed on the substrate and covers the spacer, the protection layer and the space between the spacer and the metal silicide layer.
- the step of forming the metal silicide layer on the surface of the gate conductor layer and the source/drain region comprises forming a metal layer on the substrate; next, performing a first annealing process to enable the metal layer to react with the surface of the gate conductor layer and the surface of the source/drain region, so as to form the metal silicide layer; and then selectively removing the metal layer that is not reacted and performing a second annealing process.
- the surface treatment step is performed between the step of selectively removing the metal layer that is not reacted and the step of the second annealing, or is performed after the step of the second annealing and before the step of partially removing the spacer.
- the surface treatment step includes an oxidization process a nitridation process or an oxynitridation process.
- the oxidization process can be a wet oxidization process or a dry oxidization process.
- the wet oxidization process may use hydrogen peroxide water solution, ozone water solution or acidic solution as an oxidizer.
- the dry oxidization process can be an oxygen ashing or a plasma oxidization process. In the plasma oxidization process, oxygen, ozone, nitrous oxide, nitrogen monoxide or the combinations thereof can be introduced to function as a reacting gas.
- the surface treatment step includes a nitridation process.
- the nitridation process includes the plasma nitridation process, which, for example, introduces nitrogen and hydrogen or ammonia as the reacting gas.
- the metal silicide can be silicides of titanium, cobalt, nickel, platinum, palladium, molybdenum, or alloys or combinations thereof.
- the present invention provides a semiconductor device, which comprises a transistor, a metal silicide layer, a protection layer and a stress layer.
- the transistor disposed on the substrate comprises a gate structure and a source/drain region, wherein the gate structure comprises a gate conductor layer, a gate dielectric layer and a spacer.
- the gate dielectric layer is disposed between the gate conductor layer and the substrate, and the spacer is disposed on the side wall of the gate conductor layer.
- the metal silicide layer is located on the surface of the source/drain region and the surface of the gate conductor layer, and a space exists between the metal silicide layer above the source/drain region and the spacer.
- the protection layer covers the metal silicide layer, but does not cover the spacer.
- the stress layer covers the spacer, the protection layer, and the space.
- the protection layer includes metal oxides, metal nitrides or metal oxynitrides.
- the metal silicide can be silicides of titanium, cobalt, nickel, platinum, palladium, molybdenum, or alloys or combinations thereof.
- the stress layer is a compressive stress layer or a tensile stress layer.
- a surface treatment step is performed before the step of reducing the width of the spacer to form a protection layer on the metal silicide layers via surface reaction, thus preventing the metal silicide layers from being damaged during the subsequent etching process of reducing the width of the spacer.
- FIGS. 1A ⁇ 1D are sectional flow charts of a method of fabricating a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a partial sectional view of a method of fabricating a semiconductor device according to another embodiment of the present invention.
- FIG. 3 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
- FIG. 4 is a flow chart of a method of fabricating a semiconductor device according to another embodiment of the present invention.
- FIG. 5 is a flow chart of a method of fabricating a semiconductor device according to still another embodiment of the present invention.
- FIGS. 6A ⁇ 6B are sectional flow charts of a method of fabricating a semiconductor device to improve the mobility of electrons or holes in the channel according to prior art.
- FIGS. 1A ⁇ 1D are sectional flow charts of a method of fabricating a semiconductor device according to an embodiment of the present invention.
- an isolation structure 101 is formed in a substrate 100 to define an active area 150 .
- a transistor 102 is formed in the active area 150 .
- the transistor 102 includes a gate structure 103 and a source/drain region 118 .
- the substrate 100 is, for example, a substrate of bulk semiconductor, or a silicon-on-insulator (SOI) substrate, such as a substrate containing silicon, epitaxial silicon, germanium, silicon germanium silicon carbide, or the combinations thereof.
- SOI silicon-on-insulator
- the method of forming the transistor 102 is, for example, first forming a patterned gate dielectric layer 104 and a gate conductor layer 106 on the substrate 100 .
- the gate dielectric layer 104 is, for example, a silicon oxide layer, silicon oxynitride layer, silicon nitride layer or high dielectric constant material layer with a dielectric constant higher than the silicon oxide, such as an HfSi x O y layer, an HfSi x N y O z layer, a ZrO 2 layer, an HfO 2 layer, a TiO 2 layer, an La 2 O 3 layer, a Ta 2 O 5 layer, a CeO 2 layer, a Y 2 O 3 layer, or an Al 2 O 3 layer, which can be formed by a thermal oxidization process or deposition process.
- the material of the gate conductor layer 106 is, for example, polysilicon, and the method of forming the gate conductor layer 106 is, for example, chemical vapor deposition. Then, a lightly doped source/drain region 112 or a source/drain extension region 112 of the source/drain region 118 is formed in the substrate 100 . In the present embodiment, the illustration is based on the lightly doped source/drain region 112 . Then, a spacer 114 is formed on the side wall of the gate conductor layer 106 . Then, a heavily doped source/drain region 116 , or a source/drain contact region 116 of the source/drain region 118 is formed in the substrate 100 .
- the illustration is based on the heavily doped source/drain region 116 .
- the material of the spacer 114 is, for example, silicon oxide or silicon nitride.
- a liner layer 108 (as shown in FIG. 1A ) or two liner layers 108 and 110 can be formed on the side wall of the gate conductor layer 106 .
- the material of the spacer 114 when the material of the spacer 114 is silicon oxide, the material of the liner layer 108 can be silicon oxide.
- the materials of the liner layers 108 and 110 can be silicon oxide and silicon nitride respectively.
- one or two offset spacers can be formed on the side wall of the gate conductor layer 106 before the liner layer 108 is formed according to the process requirements.
- the fabricating process of the semiconductor device of the present invention is illustrated with reference to FIG. 1A .
- the dopant of the source/drain region 118 is, for example, an n-type dopant or a p-type dopant.
- the n-type dopant uses phosphor or arsenic
- the p-type dopant uses boron.
- the method of forming the source/drain region 118 is ion implantation, and the lightly doped source/drain region 112 and the heavily doped source/drain region 116 are formed by directly implanting the dopant into the substrate 100 . Referring to FIG.
- the method of forming the source/drain region 118 comprises: after forming the gate conductor layer 106 , etching and removing the areas on both sides of the gate conductor layer 106 where the source/drain region 118 is to be formed, so as to form recesses 130 ; next, refilling the recesses 130 with material layers 132 of a material other than the substrate 100 ; and then performing the ion implantation process to form the lightly doped source/drain region 112 and the heavily doped source/drain region 116 .
- the method of refilling the material layers 132 can be the chemical vapor deposition or epitaxy process.
- the refilled material layers 132 are, for example, silicon germanium and in the example of the n-type MOS transistor, the refilled material layers 132 are, for example, silicon carbide.
- a metal layer 120 is formed on the substrate 100 , wherein the material of the metal layer 120 is, for example, titanium, cobalt, nickel, platinum, palladium, molybdenum, or alloys or combinations thereof.
- a annealing process is performed, such that the metal layer 120 reacts with the silicon on the surface of the gate conductor layer 106 and the surface of the source/drain region 118 , so as to form metal silicide layers 122 and 124 on the gate conductor layer 106 and the source/drain region 118 respectively.
- the annealing process can be a rapid thermal process (RTP). The temperature and time of the annealing are related to the characteristics of the material of the metal layer 120 .
- the metal layer 120 that is not reacted is selectively removed, such that the metal silicide layers 122 and 124 on the gate conductor layer 106 and the source/drain region 118 are exposed.
- the method of selectively removing the metal layer that is not reacted can be a wet etching method, for example, with sulfuric acid hydrogen peroxide mixture (SPM), ammonia hydrogen peroxide mixture (APM) or hydrochloric peroxide mixture (HPM) functioning as an etchant.
- the second annealing can be performed according to different materials of the formed metal silicide layers 122 and 124 , so as to make the metal silicide layers 122 and 124 have better properties, such as lower resistance or better thermal stability.
- the second annealing process can be a rapid thermal process.
- the temperature and time of the annealing are related to the characteristics of the material of the metal layer 120 .
- an etching process is performed before the stress layer is formed, so as to reduce the width W 1 of the spacer 114 , which allows the stress layer formed subsequently to be closer to the channel, thus the mobility of electrons or holes in the channel is increased.
- the metal silicide layers 122 and 124 are directly exposed to the etching environment without any protection, the metal silicide layers 122 and 124 will be damaged after the etching process, especially after the over etching, resulting in unsatisfactory sheet resistance.
- a surface treatment step can be performed first, so as to form protection layers 126 , 128 on the metal silicide layers 122 , 124 respectively via surface reaction, and protect the metal silicide layers 122 and 124 from being damaged in the subsequent processes.
- the surface treatment step can be an oxidization step, a nitridation step or an oxynitridation step, so as to form the protection layers 126 , 128 by oxidizing, nitriding, or oxynitriding the surfaces of the metal silicide layers 122 and 124 respectively.
- the material of the protection layers 126 , 128 is preferably different from that of the spacer 114 , so as to provide better selectivity during the subsequent etching process for reducing the width of the spacer 114 .
- the material of the spacer 114 is silicon nitride
- the surface treatment step can be an oxidization step, which oxidizes the surfaces of the metal silicide layers 122 and 124 to form the metal oxide protection layers 126 , 128 .
- the oxidization step can be a wet oxidization process or a dry oxidization process.
- the wet oxidization process may use the hydrogen peroxide water solution, ozone water solution or acidic solution such as nitric acid or sulfuric acid as an oxidizer.
- the dry oxidization process can be an oxygen ashing or a plasma oxidization process.
- the material of the spacer 114 is silicon oxide
- the surface treatment step can be a nitridation step, which nitrides the surfaces of the metal silicide layers 122 and 124 to form the metal nitride protection layers 126 , 128 .
- the nitridation step can be a dry nitridation process.
- the dry nitridation process can be a plasma nitridation process.
- nitrogen and hydrogen or ammonia are introduced to serve as a reacting gas.
- the material of the spacer 114 is silicon oxide
- the surface treatment step can be an oxynitridation step, which oxynitrides the surfaces of the metal silicide layers 122 and 124 to form the metal oxynitride protection layers 126 , 128 .
- the oxynitridation step can be a dry oxynitridation process.
- the dry oxynitridation process can be an oxynitridation reaction in a plasma environment containing nitrogen and oxygen such as nitrous oxide or nitrogen monoxide serving as a reacting gas.
- an etching process is performed after the protection layers 126 , 128 are formed, so as to reduce the width W 1 of the spacer 114 , such that a space 140 exists between the remained spacer 114 a with a width W 2 and the metal silicide layer.
- the protection layers 126 , 128 function as a mask to protect the silicide layers 122 , 124 from being damaged. Therefore, in the present invention, the extra width of the spacer 114 can be removed by etching, such that the stress layer formed subsequently is closer to the channel.
- the etching process for reducing the width of the spacer 114 can be a wet etching process, a dry etching process or a vapor etching process.
- the spacer 114 is silicon nitride
- hot phosphoric acid can be used as the etchant.
- the temperature of the substrate 100 is maintained to be higher than that of the introduced etching gas, and the etching is performed with hydrogen fluoride-containing gas and vapor predetermined oxidizing agents such as nitric acid, ozone, hydrogen peroxide, hypochlorous acid, chloric acid, oxygen, sulfuric acid or chlorobromide as the etching gas.
- the temperature of the substrate 100 is maintained at 125° C., and anhydrous hydrogen fluoride is introduced to function as an etching gas to perform etching.
- the hydrofluoric acid can be used as an etchant in the wet etching process, the plasma of fluorine-containing gases such as CF 4 can be used in the dry etching process, and the hydrofluoric acid steam can be used in the vapor etching process.
- a stress layer 129 is formed on the substrate 100 , so as to cover the spacer 114 a , the protection layers 126 , 128 , and the space 140 .
- the stress layer 129 is a compressive stress layer, which forms the compressive stress along the channel direction in the p-type MOS transistor to improve the mobility of carriers.
- the stress layer 129 is a tensile stress layer, which forms the tensile stress along the channel direction in the n-type MOS transistor to improve the mobility of carriers.
- the remained spacer 114 a is narrower, and the space 140 is formed between the spacer 114 a and the metal silicide layer 124 . Therefore, the stress layer 129 is closer to the channel, and has better stress performance.
- the metal silicide layers 122 and 124 can be protected by only performing the surface treatment step 312 of the present invention before the step of reducing the width of the spacer 114 .
- the time to perform the surface treatment step 312 is after Step 302 of forming the transistor 102 on the substrate 100 and Step 310 of forming the metal silicide layers 122 and 124 on the source/drain region 118 , and is before Step 314 of reducing the width W 1 of the spacer 114 and Step 316 of forming the stress layer 129 .
- the surface treatment step 312 may be performed before the second annealing step, or after the second annealing step.
- the surface treatment step 312 is performed before the second annealing step. More particularly, Step 302 is performed first to form the transistor 102 on the substrate 100 . Then, Step 304 is performed to form the metal layer 120 on the substrate 100 . After that, Step 306 of the first annealing is performed to form the metal silicide layers 122 and 124 . Next, Step 308 is performed to selectively remove the metal layer 120 that is not reacted. Then, Step 312 is performed to process the surface treatment on the metal silicide layers 122 and 124 .
- Step 313 is performed to process the second annealing on the metal silicide layers 122 and 124 .
- Step 314 is performed to reduce the width W 1 of the spacer 114 .
- Step 316 is performed to form the stress layer 129 .
- the method of surface treatment can be a wet process or a dry process. As the method of selectively removing the metal layer 120 that is not reacted is normally the selective wet etching, if the surface treatment also adopts the wet process, it can be performed in-situ concurrently, and the process is convenient and rapid.
- the surface treatment step 312 is performed after the second annealing step. More particularly, Step 302 is performed first to form the transistor 102 on the substrate 100 . Then, Step 304 is performed to form the metal layer 120 on the substrate 100 . Next, Step 306 of the first annealing is performed to form the metal silicide layers 122 and 124 . After that, Step 308 is performed to remove the metal layer 120 that is not reacted. Then, Step 313 is performed to process the second annealing on the metal silicide layers 122 and 124 . Next, Step 312 is performed to process the surface treatment on the metal silicide layers 122 and 124 . Afterward, Step 314 is performed to reduce the width W 1 of the spacer 114 . And then, Step 316 is performed to form the stress layer 129 .
- a step of reducing the width of the spacer is performed prior to the step of forming the stress layer, the distance between the stress layer and the channel is shorter, and the compressive stress or the tensile stress along the channel direction is increased, therefore the mobility of electrons or holes in the channel is improved effectively.
- a surface treatment step is performed before the step of reducing the width of the spacer to form a protection layer on the metal silicide layers via surface reaction, thus preventing the metal silicide layers from being damaged during the subsequent etching process of reducing the width of the spacer.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (18)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/309,740 US7390729B2 (en) | 2006-09-21 | 2006-09-21 | Method of fabricating a semiconductor device |
US11/829,087 US7482668B2 (en) | 2006-09-21 | 2007-07-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/309,740 US7390729B2 (en) | 2006-09-21 | 2006-09-21 | Method of fabricating a semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/829,087 Division US7482668B2 (en) | 2006-09-21 | 2007-07-27 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080076213A1 US20080076213A1 (en) | 2008-03-27 |
US7390729B2 true US7390729B2 (en) | 2008-06-24 |
Family
ID=39224029
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/309,740 Active US7390729B2 (en) | 2006-09-21 | 2006-09-21 | Method of fabricating a semiconductor device |
US11/829,087 Active US7482668B2 (en) | 2006-09-21 | 2007-07-27 | Semiconductor device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/829,087 Active US7482668B2 (en) | 2006-09-21 | 2007-07-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
US (2) | US7390729B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080199999A1 (en) * | 2007-02-21 | 2008-08-21 | Texas Instruments Incorporated | Formation of a Selective Carbon-Doped Epitaxial Cap Layer on Selective Epitaxial SiGe |
US20080315322A1 (en) * | 2007-06-25 | 2008-12-25 | Texas Instruments Incorporated | Method for reliably removing excess metal during metal silicide formation |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4395179B2 (en) * | 2007-05-31 | 2010-01-06 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
KR100967479B1 (en) * | 2007-12-24 | 2010-07-07 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
US8138077B2 (en) * | 2008-05-13 | 2012-03-20 | Hynix Semiconductor Inc. | Flash memory device and method of fabricating the same |
US8132676B2 (en) | 2008-08-18 | 2012-03-13 | Emd Millipore Corporation | Hydrophilic, high protein binding, low fluorescence, western blotting membrane |
FR2938376B1 (en) * | 2008-11-07 | 2010-12-31 | Commissariat Energie Atomique | PROCESS FOR THE PREPARATION OF A NISI NICKEL MONOSILICIDE LAYER ON A SILICON SUBSTRATE |
US8030154B1 (en) * | 2010-08-03 | 2011-10-04 | International Business Machines Corporation | Method for forming a protection layer over metal semiconductor contact and structure formed thereon |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4877755A (en) * | 1988-05-31 | 1989-10-31 | Texas Instruments Incorporated | Method of forming silicides having different thicknesses |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7053400B2 (en) * | 2004-05-05 | 2006-05-30 | Advanced Micro Devices, Inc. | Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility |
US20070224745A1 (en) * | 2006-03-21 | 2007-09-27 | Hui-Chen Chang | Semiconductor device and fabricating method thereof |
-
2006
- 2006-09-21 US US11/309,740 patent/US7390729B2/en active Active
-
2007
- 2007-07-27 US US11/829,087 patent/US7482668B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4877755A (en) * | 1988-05-31 | 1989-10-31 | Texas Instruments Incorporated | Method of forming silicides having different thicknesses |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080199999A1 (en) * | 2007-02-21 | 2008-08-21 | Texas Instruments Incorporated | Formation of a Selective Carbon-Doped Epitaxial Cap Layer on Selective Epitaxial SiGe |
US8835263B2 (en) * | 2007-02-21 | 2014-09-16 | Texas Instruments Incorporated | Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGe |
US20080315322A1 (en) * | 2007-06-25 | 2008-12-25 | Texas Instruments Incorporated | Method for reliably removing excess metal during metal silicide formation |
US7700481B2 (en) * | 2007-06-25 | 2010-04-20 | Texas Instruments Incorporated | Method for reliably removing excess metal during metal silicide formation |
Also Published As
Publication number | Publication date |
---|---|
US20080073727A1 (en) | 2008-03-27 |
US7482668B2 (en) | 2009-01-27 |
US20080076213A1 (en) | 2008-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7482668B2 (en) | Semiconductor device | |
US7462528B2 (en) | CMOS (Complementary metal oxide semiconductor) technology with leakage current mitigation | |
US8652908B2 (en) | Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same | |
US8673757B2 (en) | Structure and method for using high-k material as an etch stop layer in dual stress layer process | |
JP5126930B2 (en) | Manufacturing method of semiconductor device | |
CN100568468C (en) | Semiconductor element and manufacture method thereof | |
KR102256421B1 (en) | Integration of non-volatile charge trap memory devices and logic cmos devices | |
JP2007335834A (en) | Semiconductor device and manufacturing method thereof | |
JP4011024B2 (en) | Semiconductor device and manufacturing method thereof | |
JPWO2007091302A1 (en) | Semiconductor device and manufacturing method thereof | |
US8008204B2 (en) | Method of manufacturing semiconductor device | |
US7883960B2 (en) | Method of manufacturing semiconductor device | |
US8928051B2 (en) | Metal oxide semiconductor (MOS) device with locally thickened gate oxide | |
KR100936577B1 (en) | A semiconductor device and method for the same | |
CN103137491B (en) | For improving the conversion zone of the thickness evenness of strain structure | |
JP2008130797A (en) | Semiconductor device, and manufacturing method thereof | |
JP2007142024A (en) | Method of manufacturing semiconductor device | |
JP3614782B2 (en) | Manufacturing method of semiconductor device and semiconductor device manufactured by the method | |
US20120056270A1 (en) | Semiconductor device and method for fabricating the same | |
JP4193638B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
WO2023123762A1 (en) | Semiconductor structure and method for forming same | |
JP2005252192A (en) | Method for manufacturing complementary semiconductor device | |
KR20000054890A (en) | Method for field effect transistor using selective epitaxial growth | |
JP2005159336A (en) | Method for manufacturing semiconductor device | |
JP2005012075A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, CHAO-CHING;CHANG, CHUN-CHIEH;HUNG, TZUNG-YU;REEL/FRAME:018283/0249 Effective date: 20060906 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |