JP4193638B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MOS transistor structure having an extension region and a semiconductor device obtained by the manufacturing method.

  Along with the demand for higher performance of semiconductor devices, the miniaturization of transistor structures is progressing in MOS type silicon semiconductor devices. In the generation where the design rule of the gate electrode is 90 nm or less, the channel length becomes 60 nm or less, and the deterioration of the transistor characteristics due to the short channel effect becomes remarkable. Further, diffusion of ions implanted in the formation of the low concentration extension forms a capacitor composed of gate electrode-gate insulating film-extension, resulting in deterioration of transistor operation speed.

  In order to prevent such deterioration of the transistor characteristics, an insulating film made of silicon oxide or silicon nitride is formed by CVD in a state of covering the gate electrode before ion implantation for extension formation, and this insulating film is anisotropically etched. Thus, a method of forming a sidewall-shaped offset spacer on the side wall of the gate electrode has been proposed. According to such a method, ion implantation for forming the extension is performed after the offset spacer is provided, thereby preventing the extension from reaching the gate electrode and forming the above-described capacitor (described below). Patent Document 1).

JP 2000-216373 A (FIG. 3 and 0025 to 0027)

  However, in the manufacturing method described above, in the anisotropic etching of the insulating film for forming the offset spacer, the underlying semiconductor substrate is over-etched, and the surface of the semiconductor substrate recedes. As a result, the distance between the extension and the gate electrode becomes unnecessarily large, and there is a concern about deterioration of transistor characteristics such as deterioration of on-current (Ion) and reduction of threshold voltage (Vth).

  In addition, the offset spacer is formed by anisotropic etching of an insulating film formed by a CVD method or the like, but the insulating film formed by such a deposited film easily varies in film thickness. Also, the amount of recession on the surface of the semiconductor substrate due to the over-etching described above also varies. As a result, the transistor characteristics also vary due to the above-described deterioration of the on-current (Ion) and the variation of the threshold voltage (Vth).

  Therefore, the present invention suppresses the recession of the semiconductor substrate when forming the sidewall-shaped offset spacer for forming the low-concentration diffusion layer (extension) of the MOS transistor, and suppresses the variation in the formation of the offset spacer. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing deterioration of the semiconductor device, and a semiconductor device formed thereby.

A method for manufacturing a semiconductor device of the present invention for achieving such an object is characterized in that it is carried out by the following procedure. First, in step (a), a gate electrode is formed on a semiconductor substrate via a gate insulating film, and in the next step (b), a first insulating film is formed on the semiconductor substrate so as to cover the gate electrode. Thereafter, in step (c), the surface of the first insulating film is treated to grow a second insulating film on the surface layer of the first insulating film, and in the next step (d), the second insulating film is formed on the second insulating film. A third insulating film is formed. After the above, in the step (e), the third insulating film is anisotropically etched using the second insulating film as a stopper, and the second insulating film and the first insulating film are anisotropically etched. A sidewall made of the first insulating film, the second insulating film, and the third insulating film is formed. In step (f), impurities are introduced into the surface layer of the semiconductor substrate using the gate electrode and the sidewall as a mask. By introducing this impurity, a diffusion layer (extension region) having a lower concentration than the source / drain diffusion layer is formed. In the subsequent step (g), a second sidewall is formed on the side wall of the gate electrode via the sidewall. Thereafter, in step (h), impurities for forming a source / drain diffusion layer are introduced into the surface layer of the semiconductor substrate using the gate electrode, the sidewall, and the second sidewall as a mask.

  In such a manufacturing method, by etching the third insulating film using the second insulating film as an etching stopper, the etching amount variation caused by the film thickness variation of the third insulating film reaches the second insulating film. It will be canceled once. Therefore, the subsequent etching of the thin film-like second insulating film and the first insulating film can proceed without being affected by the film thickness variation of the third insulating film. Moreover, since the second insulating film is a film grown by surface treatment of the first insulating film, the film thickness variation is small. For this reason, compared with the case where the second insulating film is deposited, the etching variation of the second insulating film itself can be suppressed small. Therefore, the side wall is formed while minimizing the amount of shaving and the amount of shaving of the semiconductor substrate.

  The present invention is also a semiconductor device formed by the above-described manufacturing method. In a MOS type semiconductor device having a low concentration diffusion layer (extension region) together with a source / drain diffusion layer, the low concentration diffusion layer is a gate. The first sidewall is formed by introducing impurities using the electrode and the first sidewall as a mask. In particular, the first sidewall is formed by treating the first insulating film and the surface of the first insulating film. A second insulating film grown on the surface layer of the first insulating film; and a third insulating film formed on the second insulating film and made of a material that can be selectively etched with respect to the second insulating film. It is characterized by having.

  As described above, according to the manufacturing method of the present invention, it is possible to suppress the recession of the surface of the semiconductor substrate when forming the sidewall-shaped offset spacer on the side wall of the gate electrode, and to suppress the formation variation of the offset spacer. Therefore, it is possible to form the diffusion layer region formed by introducing the impurity using the gate electrode and the sidewall as a mask with good positional accuracy. As a result, a semiconductor device having a MOS transistor with good characteristics can be obtained. Furthermore, the semiconductor device of the present invention has a structure manufactured by the above-described manufacturing method, and has a MOS transistor with good characteristics while having a low concentration diffusion layer.

  Hereinafter, embodiments of the present invention will be described in order from the manufacturing method based on the cross-sectional process diagrams of FIGS.

  First, as shown in FIG. 1A, a gate electrode 5 is formed on a semiconductor substrate 1 made of, for example, single crystal silicon with a gate insulating film 3 interposed therebetween. Here, first, a gate insulating film 3 made of silicon oxide or silicon nitride and a gate electrode material film made of polysilicon or silicide are formed on the semiconductor substrate 1 subjected to ion implantation and activation annealing for channel formation. Then, the gate electrode material and the gate insulating film 3 are patterned.

Next, as shown in FIG. 1B, a first insulating film 7 is formed on the semiconductor substrate 1 so as to alleviate deterioration due to patterning in the vicinity of the edge of the gate insulating film 3 while covering the gate electrode 5. To do. Here, as an example, first, pre-cleaning for removing the natural oxide film and chemical oxide film on the surface of the gate electrode 5 and the semiconductor substrate 1 is performed, and then heat treatment is performed in a gas containing oxygen gas (O ₂ ). As a result, the first insulating film 7 made of a thermal oxide film is grown. Such a thermal oxidation treatment causes the surface of the semiconductor substrate 1 to recede which causes deterioration of the on-current (Ion) of the transistor. For this reason, in order to suppress such recession of the surface of the semiconductor substrate 1, the first insulating film 7 made of a thermal oxide film is preferably formed as a thin film of 4 nm or less.

  Next, as shown in FIG. 1 (3), the surface of the first insulating film 7 made of a thermal oxide film is subjected to nitriding treatment, whereby the second insulating film 9 made of silicon nitride is formed on the surface layer of the first insulating film 7. Grow. As the nitriding process at this time, for example, a plasma process is performed.

Hereinafter, an example of forming the second insulating film 9 by plasma nitriding will be described. First, in a chamber having a plasma source and a nitrogen gas (N ₂ ) line, the semiconductor substrate 1 subjected to the formation of the first insulating film 7 is accommodated, and the pressure in the chamber is maintained at 2.67 × 10 ² Pa. The temperature of the semiconductor substrate 1 is kept at 400 ° C. In this state, N ₂ is introduced into the chamber at a flow rate of 100 sccm, and a power of 500 W is applied to the plasma source. Thus, nitrogen plasma is generated in the chamber, and the surface of the first insulating film 7 on the semiconductor substrate 1 is plasma-nitrided to grow a second insulating film 9 made of silicon nitride.

  The formation of the second insulating film 9 is not limited to nitriding treatment. That is, the second insulating film 9 may be formed not as a deposited film but as a processing film grown on the surface layer of the first insulating film 7 by processing. Therefore, depending on the film quality of the first insulating film 7, when the first insulating film 7 is a thermal oxide film, it may be a carbonizing process in addition to the nitriding process. On the other hand, if the first insulating film 7 is a nitride film, it may be an oxidation process, a carbonization process, or an oxycarbonization process. Furthermore, these film forming processes are not limited to plasma processes.

After the above, as shown in FIG. 1 (4), the third insulating film 11 made of a material that can be selectively etched with respect to the second insulating film 9 is formed on the second insulating film 9. Therefore, when the second insulating film 9 is made of silicon nitride, the third insulating film 11 made of silicon oxide is formed. The third insulating film 11 constitutes, together with the first insulating film 7 and the second insulating film 9, a sidewall for an offset spacer for forming a low-concentration diffusion layer formed in the subsequent steps. For this reason, the film thickness of the third insulating film 11 is set so that the sidewall has the set film thickness. The film thickness of the third insulating film 11 is, for example, in the range of 15 nm or less, and is thicker than the first insulating film 7 and the second insulating film 9, although it depends on the characteristics of the MOS transistor manufactured here. It is supposed to be formed with a thickness.

  The third insulating film 11 having a thickness larger than that of the first insulating film 7 and the second insulating film 9 is formed by deposition such as LP-CVD (low pressure-chemical vapor deposition). The film method may be used.

  Next, as shown in FIG. 2 (5), the third insulating film 11 made of silicon oxide is anisotropically etched using the second insulating film 9 made of silicon nitride as a stopper, and only on the side wall of the gate electrode 5. The third insulating film 11 is left. Next, when the third insulating film 11 on the second insulating film 9 is removed, the second insulating film 9 made of silicon nitride and the first insulating film 7 made of a thermal oxide film are anisotropically etched to obtain a gate electrode. The second insulating film 9 and the first insulating film 7 are left only on the side wall 5. As a result, the first sidewall 13 including the first insulating film 7, the second insulating film 9, and the third insulating film 11 is formed on the sidewall of the gate electrode 5.

In the anisotropic etching of the third insulating film 11, the second insulating film 9, and the first insulating film 7 described above, for example, octafluorocyclobutane (C) having a high selectivity with respect to the semiconductor substrate 1 made of single crystal silicon. Reactive ion etching (RIE) using an etching gas containing ₄ F ₈ ) or trifluoromethane (CHF ₃ ) is performed.

  Next, as shown in FIG. 2 (6), a low-concentration diffusion layer 15 serving as a so-called source / drain extension region is formed on the surface layer of the semiconductor substrate 1 using the gate electrode 5 and the first sidewall 13 as a mask. Impurities are introduced for this purpose. This impurity introduction is performed, for example, by ion implantation. At this time, impurities are introduced into the surface layer portion of the semiconductor substrate 1 beside the gate electrode 5 with an interval using the first sidewall 13 as an offset spacer.

  Thereafter, as shown in FIG. 2 (7), a second sidewall 17 is formed on the sidewall of the gate electrode 5 via the first sidewall 13. The second sidewall 17 is formed by, for example, forming a silicon oxide film and anisotropic etching of the silicon oxide film. The second sidewall 17 is not limited to one made of silicon oxide, and is not limited to one layer such as a two-layer structure of silicon oxide and silicon nitride.

  Next, as shown in FIG. 2 (8), a source / drain diffusion layer (on the surface layer of the semiconductor substrate 1 is formed using the gate electrode 5, the first sidewall 13, and the second sidewall 17 as a mask). Impurities are introduced to form (source / drain) 19. This impurity introduction is performed, for example, by ion implantation.

  After the above, a heat treatment for activating the impurities introduced into the surface layer of the semiconductor substrate 1 is performed to complete the semiconductor device 20 having a MOS transistor structure.

  In the semiconductor device 20 obtained in this manner, the first sidewall 13 used as an offset spacer when forming the low concentration diffusion layer 15 includes the first insulating film 7 and the first insulating film 7. A second insulating film 9 grown on the surface layer of the first insulating film 7 by treating the surface and a second insulating film 9 formed on the second insulating film 9 can be selectively etched. The third insulating film 11 is made of a material.

  According to the manufacturing method described above, as described with reference to FIG. 2 (5), when the first sidewall 13 is formed, the third insulating film 9 is used as the etching stopper. 11 is etched. Thereby, the variation in the etching amount caused by the variation in the film thickness of the third insulating film 11 made of the deposited film can be temporarily canceled when the etching reaches the second insulating film 9. Therefore, the subsequent etching of the second insulating film 9 and the first insulating film 7 can proceed without being affected by the film thickness variation of the third insulating film 11. Moreover, since the second insulating film 9 is a film grown by the surface treatment of the first insulating film 7, the film thickness variation is small. For this reason, compared with the case where the second insulating film 9 is a deposited film, the etching variation of the second insulating film 9 itself can be reduced. Therefore, the first sidewall 13 can be formed while minimizing the amount of shaving and the amount of shaving of the semiconductor substrate 1.

  As a result, as described with reference to FIG. 2 (6), when the low concentration diffusion layer 15 is formed using the first sidewall 13 as an offset spacer, the distance between the low concentration diffusion layer 15 and the gate electrode 5 is increased. Therefore, it is possible to prevent deterioration of the on-current (Ion) and the threshold voltage (Vth) in the formed semiconductor device 20. This makes it possible to obtain a semiconductor device 20 with good characteristics.

  In the step described with reference to FIG. 1B, when the first insulating film 7 is formed as a thermal oxide film for alleviating deterioration due to patterning in the vicinity of the edge in the gate insulating film 3, the following FIG. In the step of forming the second insulating film 9 described with reference to (3), the thermal oxide film (first insulating film 7) in contact with the gate insulating film 3 is not nitrided. For this reason, the deterioration alleviating function of the gate insulating film 3 which is the original purpose is not impaired. In addition, since the second insulating film 9 is formed by nitriding the pole surface of the first insulating film 7, it is not necessary to form the first insulating film 7 (thermal oxide film) thick. Therefore, the recession of the surface of the semiconductor substrate 1 due to the formation of the first insulating film 7 made of the thermal oxide film can be minimized. This also suppresses the above-described deterioration of the on-current (Ion) and the threshold voltage (Vth).

  In the above embodiment, as described with reference to FIG. 1B, the first insulating film 7 is formed by thermal oxidation. However, the first insulating film 7 is not necessarily a treatment film, and may be a deposited film. Even in such a configuration, since the second insulating film 9 serving as an etching stopper for the third insulating film 11 is a processing film, the semiconductor substrate 1 is prevented from being scraped when the first sidewall 13 is formed. And the same effect can be obtained.

  As an application example of the present invention, the present invention can be widely applied to applications in which etching of a film formed on a substrate is indispensable while suppressing the recession of the substrate surface to a minimum and uniformly.

It is sectional process drawing (the 1) which shows the manufacturing method of this invention. It is sectional process drawing (the 2) which shows the manufacturing method of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... Gate insulating film, 5 ... Gate electrode, 7 ... 1st insulating film, 9 ... 2nd insulating film, 11 ... 3rd insulating film, 13 ... 1st side wall, 15 ... Low concentration diffusion Layer, 17 ... second sidewall, 19 ... source / drain, 20 ... semiconductor device

Claims (4)

Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming a first insulating film on the semiconductor substrate so as to cover the gate electrode;
(C) growing a second insulating film on a surface layer of the first insulating film by treating the surface of the first insulating film;
Forming a third insulating film on the second insulating film (d);
The third insulating film is anisotropically etched using the second insulating film as a stopper, and further, the second insulating film and the first insulating film are anisotropically etched, whereby the side wall of the gate electrode is etched. A step (e) of forming a sidewall made of one insulating film, a second insulating film, and a third insulating film;
Introducing an impurity into the surface layer of the semiconductor substrate using the gate electrode and the sidewall as a mask (f) ;
Forming a second sidewall on the side wall of the gate electrode via the sidewall;
And (h) introducing an impurity for forming a source / drain diffusion layer into a surface layer of the semiconductor substrate using the gate electrode, the sidewall, and the second sidewall as a mask. A method for manufacturing a semiconductor device.
The semiconductor device according to claim 1,
In the step (c), at least one of nitridation, oxidation, and carbonization is performed. The semiconductor device according to claim 1,
In the step (c), a plasma process is performed. A gate electrode provided on a semiconductor substrate via a gate insulating film;
A first sidewall provided on a sidewall of the gate electrode and the gate insulating film;
A lightly doped diffusion layer formed on the surface layer of the semiconductor substrate by introducing impurities using the gate electrode and the first sidewall as a mask, and sidewalls of the gate electrode and the gate insulating film via the first sidewall A second sidewall provided in
In a semiconductor device comprising a source / drain diffusion layer formed on a surface layer of the semiconductor substrate by introducing impurities using the gate electrode, the first sidewall, and the second sidewall as a mask,
The first sidewall includes a first insulating film, a second insulating film grown on a surface layer of the first insulating film by treating the surface of the first insulating film, and the second insulating film And a third insulating film made of a material that can be selectively etched with respect to the second insulating film.

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