KR100427535B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100427535B1 KR100427535B1 KR10-2001-0081944A KR20010081944A KR100427535B1 KR 100427535 B1 KR100427535 B1 KR 100427535B1 KR 20010081944 A KR20010081944 A KR 20010081944A KR 100427535 B1 KR100427535 B1 KR 100427535B1
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- Prior art keywords
- gate electrode
- semiconductor device
- manufacturing
- insulating film
- silicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
Abstract
본 발명의 반도체 소자의 제조 방법에 관한 것으로, SEG(Selective Epitaxial Growing)공정을 이용하여 T자형으로 게이트 전극 상부를 확장시킴으로써 저 저항의 게이트 전극을 형성하여 소자의 특성향상 및 원가절감 할 수 있는 반도체 소자의 제조 방법을 제공한다.The present invention relates to a semiconductor device manufacturing method of the present invention, which uses a selective epitaxial growing (SEG) process to extend a gate electrode in a T-shape to form a low resistance gate electrode to improve device characteristics and reduce cost. Provided is a method of manufacturing a device.
Description
본 발명의 반도체 소자의 제조 방법에 관한 것으로, 반도체 소자가 고집적화되어감에 따라 증가하는 게이트의 저항을 제거하기 위해서 게이트 전극(Gate electrode) 상부를 확장 시켜 금속 샐리사이드막이 형성되는 부분의 면적을 증가 시켜 저항을 감소시키고 열적 안정성을 높일 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, wherein an area of a metal salicide film is formed by extending an upper portion of a gate electrode in order to remove resistance of a gate which increases as the semiconductor device becomes highly integrated. The present invention relates to a method for manufacturing a semiconductor device capable of reducing resistance and increasing thermal stability.
고집적 CMOS 소자의 제조에 있어서 게이트의 저항감소는 소자의 속도를 증가시키는 작용을 한다. 종래에 게이트 저항을 감소시키기 위해 여러 가지 방법이 시도되고 있으나 가장 널리 쓰이는 방법이 폴리 실리콘 게이트 상에 금속 샐리사이드막을 형성시켜 저항을 감소시키는 것이다.In the fabrication of highly integrated CMOS devices, the reduced resistance of the gate serves to increase the device speed. Conventionally, various methods have been tried to reduce the gate resistance, but the most widely used method is to reduce the resistance by forming a metal salicide film on the polysilicon gate.
도 1 은 종래 기술에 따른 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 1을 참조하면, 트랜치(2)가 형성된 반도체 기판(1)상에 게이트 산화막(Gate oxide)(3) 및 폴리 실리콘(Poly-Si)(4)을 증착하고 게이트 전극 패터닝 하여 게이트 전극(5)을 형성한 후 LDD이온주입공정을 실시하여 LDD영역(LDD1)을 형성한다. 전체 구조상부에 산화막(6) 및 질화막(7)을 증착한 후 건식식각을 수행하여 게이트 전극(5) 측벽에 스페이서(Spacer)를 형성한다. 다음으로 소스(Source) 및 드레인(Drain) 이온주입공정을 실시하여 소스(S1)및 드레인(D1)을 형성하고, 소정의 공정을 통하여 게이트(5), 소스(S1) 및 드레인부(D1)에 금속 샐리사이드막(8)을 증착하여 반도체 소자를 형성한다.Referring to FIG. 1, a gate oxide 3 and a poly-Si 4 are deposited on a semiconductor substrate 1 on which a trench 2 is formed, and a gate electrode is patterned to form a gate electrode 5. ) And then the LDD ion implantation process is performed to form the LDD region LDD1. After the oxide film 6 and the nitride film 7 are deposited on the entire structure, a dry etching is performed to form spacers on the sidewalls of the gate electrode 5. Next, a source and a drain ion implantation process are performed to form a source S1 and a drain D1, and the gate 5, the source S1, and the drain D1 are formed through a predetermined process. A metal salicide film 8 is deposited on it to form a semiconductor device.
상기와 같이 게이트 전극(5) 상부에 금속 샐리사이드막(8)을 증착하는 방법은 게이트 저항을 크게 감소시키는 효과를 주지만 최근 게이트 선 폭이 감소함에 따라 저항값 자체가 증가하는 현상과 또한 후속 열공정에서 금속 샐리사이드막(8)이 열화되어 저항이 증가하는 현상이 발생하고 있다.As described above, the method of depositing the metal salicide layer 8 on the gate electrode 5 greatly reduces the gate resistance, but the resistance value itself increases with the recent decrease of the gate line width, and also subsequent columns. In the process, the metal salicide film 8 deteriorates and a phenomenon in which resistance increases is occurring.
따라서 본 발명은 상술한 단점을 해소할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned disadvantages.
본 발명의 다른 목적은 게이트 전극의 상부를 T자형으로 확장하여 게이트 전극과 금속 샐리사이드막이 접촉되는 면적을 증가할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing the area where the gate electrode is in contact with the metal salicide film by extending the upper portion of the gate electrode in a T-shape.
본 발명의 특징에 의하면 게이트 전극 과 금속 샐리사이드막이 형성되는 면적을 증가시켜 후속 열공정시 금속 샐리사이드막이 열화되는 것을 방지하고 게이트 전극의 저항을 감소시킬 수 있다.According to a feature of the present invention, the area in which the gate electrode and the metal salicide film are formed may be increased to prevent the metal salicide film from deteriorating during subsequent thermal processes and to reduce the resistance of the gate electrode.
본 발명의 특징에 의하면 저 저항의 게이트 전극을 형성함으로써 고속의 동작이 가능한 소자를 제조할 수 있다.According to the characteristics of the present invention, a device capable of high-speed operation can be manufactured by forming a low resistance gate electrode.
도 1 은 종래 기술에 따른 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2a 내지 2j는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도.2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1, 11 : 반도체 기판 2, 12 : 트랜치1, 11: semiconductor substrate 2, 12: trench
3, 18 : 게이트 산화막 4, 15 : 폴리 실리콘3, 18: gate oxide film 4, 15: polysilicon
8, 17 : 샐리사이드막 6 : 산화막8, 17: salicide film 6: oxide film
7, 16 : 질화막 5, 13 : 게이트 전극7, 16: nitride film 5, 13: gate electrode
14 : 절연막14: insulating film
게이트 전극이 형성된 반도체 기판내에 LDD영역이 형성되는 단계, 전체 구조 상부에 절연막을 증착한 후 평탄화 공정을 수행하여 상기 게이트 전극을 노출시키는 단계, 상기 절연막의 일부를 제거하여 상기 게이트 전극의 일부를 돌출 시킨 후 상기 돌출된 게이트 전극의 표면에 실리콘층을 형성시키는 단계, 상기 실리콘층을 마스크로 하여 노출된 상기 절연막을 제거한 후 상기 전체구조 상부에 질화막을 형성하는 단계, 식각공정을 실시하여 상기 게이트 전극 측벽에 상기 절연막과 상기 질화막으로 이루어진 스페이서를 형성하는 단계, 상기 반도체 기판에 이온을 주입하여 소스 및 드레인을 형성하는 단계 및 전체 구조 상부에 코발트 및 티타늄을 증착한 후 열처리하여 샐리사이드막을 형성하는 단계를 포함하여 이루어 진 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.Forming an LDD region in a semiconductor substrate having a gate electrode, depositing an insulating film over the entire structure, and then performing a planarization process to expose the gate electrode, and removing a portion of the insulating film to protrude a portion of the gate electrode And forming a silicon layer on the surface of the protruding gate electrode, removing the exposed insulating layer using the silicon layer as a mask, and then forming a nitride film on the entire structure, followed by an etching process. Forming a spacer comprising the insulating film and the nitride film on sidewalls, implanting ions into the semiconductor substrate to form a source and a drain, and depositing cobalt and titanium on the entire structure, followed by heat treatment to form a salicide film Peninsula, characterized in that made, including It provides a process for the production of the device.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2j는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도이다.2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 게이트산화막(18), 게이트 전극(Gate electrode)(13)이 형성된 반도체 기판(11)에 LDD(Lighty doped drain) 이온주입을 시행하여 반도체 기판(11)내의 활성 영역에 LDD영역(LDD2)을 형성한다.As shown in FIG. 2A, LDD (Lighty doped drain) ion implantation is performed on the semiconductor substrate 11 on which the gate oxide film 18 and the gate electrode 13 are formed, thereby forming an active region in the semiconductor substrate 11. An LDD region LDD2 is formed in this.
도 2b 및 2c에 도시한 바와 같이, 전체 구조 상부에 절연막(14)을 게이트 전극의 두께보다 200 내지 2000Å 두껍게 증착한다. 절연막(14)을 게이트전극(13)이 노출될 때까지 CMP(Chemical Mechanical Polishing)를 이용하여 평탄화 공정을 수행한다. 이때 절연막(14)으로는 TEOS 또는 CVD 및 PVD로 제조되는 산화막이 사용될 수 있다.As shown in Figs. 2B and 2C, the insulating film 14 is deposited 200 to 2000 Å thicker than the thickness of the gate electrode on the entire structure. The insulating film 14 is planarized by using chemical mechanical polishing (CMP) until the gate electrode 13 is exposed. In this case, an oxide film made of TEOS or CVD and PVD may be used as the insulating film 14.
도 2d에 도시한 바와 같이, 절연막(14)의 일부를 제거하여 게이트 전극(13)의 상부를 돌출 시킨다. 구체적으로 절연막(14)은 BOE 및 HF를 이용한 습식 식각이나 통상적인 건식 식각공정을 통하여 약 50 내지 500Å의 두께만큼 제거된다. 이때 잔존하는 절연막(14)은 게이트 측벽을 보호하는 버퍼(Buffer)역할을 한다.As shown in FIG. 2D, a portion of the insulating film 14 is removed to protrude the upper portion of the gate electrode 13. Specifically, the insulating film 14 is removed by a thickness of about 50 to 500 kW through wet etching using BOE and HF or a general dry etching process. At this time, the remaining insulating layer 14 serves as a buffer to protect the gate sidewall.
도 2e에 도시한 바와 같이, SEG(Selective Epitaxial Growing)공정을 이용하여 돌출된 게이트 전극(13) 상부에 실리콘층(15)을 성장시킨다.As shown in FIG. 2E, the silicon layer 15 is grown on the protruding gate electrode 13 by using a selective epitaxial growing (SEG) process.
구체적으로 SEG공정은 500 내지 1000℃의 온도와 1 내지 600Torr의 압력 하에서 DCS, SiH4,Si2HCl2또는 Si2H6를 실리콘 소스가스(Source gas)로 이용하여 게이트 전극(13)의 돌출부의 표면에 실리콘층(15)을 성장시킨다. 상기 돌출부 이외에 성장된 실리콘은 HCl 및 Cl과 같은 식각가스(Etchant gas)를 사용하여 제거한다. 상기와 같은 조건의 SEG공정을 통하여 게이트 전극(13)의 돌출부에 10 내지 500Å의 두께의 실리콘층(15)이 형성된다.Specifically, the SEG process uses the DCS, SiH 4 , Si 2 HCl 2 or Si 2 H 6 as a silicon source gas at a temperature of 500 to 1000 ° C. and a pressure of 1 to 600 Torr. The silicon layer 15 is grown on the surface of the. Silicon grown in addition to the protrusions is removed using an etchant gas such as HCl and Cl. Through the SEG process under the above conditions, the silicon layer 15 having a thickness of 10 to 500 Å is formed on the protrusion of the gate electrode 13.
도 2f 및 2g에 도시한 바와 같이, 성장된 실리콘층(15)을 식각 배리어(Barrier)층으로 식각공정을 실시하여 절연막(14)을 제거한 후 전체 구조 상부에 LDD 질화막(16a)을 증착한다. 게이트 전극(13)의 돌출부에 성장된 실리콘층(15)에 의해 게이트 전극(13) 상부가 확장되어 이후 형성될 샐리사이드막(17)과의 접촉면이 더 넓어진다.As shown in FIGS. 2F and 2G, the grown silicon layer 15 is etched with an etch barrier layer to remove the insulating layer 14, and then the LDD nitride layer 16a is deposited on the entire structure. The upper portion of the gate electrode 13 is extended by the silicon layer 15 grown on the protrusion of the gate electrode 13, thereby making the contact surface with the salicide layer 17 to be formed later wider.
도 2h에 도시한 바와 같이, LDD 질화막(16a)의 일부를 건식식각하여 제1 LDD 스페이서(16b)를 형성한다. 이는 후속 공정에 의한 게이트 전극(13)의 측벽이 손상되는 것을 방지함으로써 게이트 CD를 확보할 수 있고 채널길이를 보호해준다.As shown in FIG. 2H, a portion of the LDD nitride film 16a is dry etched to form the first LDD spacer 16b. This can secure the gate CD and protect the channel length by preventing the side wall of the gate electrode 13 from being damaged by a subsequent process.
또한 도 2i에 도시한 바와 같이 제1 LDD 스페이서(16b)을 과도 식각하여 제 2 LDD 스페이서(16c)를 형성한다. 이는 성장된 실리콘층(15)과 절연막(14)의 경계면까지 식각함으로써 게이트 전극(13)과 이후 형성될 샐리사이드막(17)의 접촉면을 극대화 할 수 있다.In addition, as illustrated in FIG. 2I, the first LDD spacer 16b is excessively etched to form the second LDD spacer 16c. This may maximize the contact surface between the gate electrode 13 and the salicide layer 17 to be formed later by etching to the interface between the grown silicon layer 15 and the insulating layer 14.
도 2j에 도시한 바와 같이, 제2 LDD 스페이서(16c)가 형성된 결과물의 반도체 기판(11)에 이온주입하여 소스(S2) 및 드레인(D2)을 형성한다. 소스(S2) 및 드레인(D2)이 형성된 반도체기판(11)에 코발트 또는 티타늄을 증착한 후 열처리하여 게이트(13), 소스(S2) 및 드레인(D2) 상부에 샐리사이드막(17)를 형성함으로써 반도체 소자의 제조를 완료한다.As shown in FIG. 2J, the source S2 and the drain D2 are formed by ion implantation into the semiconductor substrate 11 of the resultant formed second LDD spacer 16c. Cobalt or titanium is deposited on the semiconductor substrate 11 on which the source S2 and the drain D2 are formed, and then heat-treated to form the salicide layer 17 on the gate 13, the source S2, and the drain D2. This completes the manufacture of the semiconductor device.
게이트 전극(13)의 돌출부에 성장된 실리콘(15)에 의해 T자형으로 게이트 전극(13) 상부가 확장되어 게이트 전극(13)과 샐리사이드막(17)의 접촉면적이 늘어나 게이트 저항을 크게 감소 시켜주고 또한 후속 열처리 공정에서 샐리사이드막(17)이 열화 되어 저항이 증가하는 현상을 막을 수 있다.The silicon 15 grown on the protrusion of the gate electrode 13 extends the upper portion of the gate electrode 13 in a T-shape to increase the contact area between the gate electrode 13 and the salicide layer 17, thereby greatly reducing the gate resistance. In addition, in the subsequent heat treatment process, the salicide layer 17 may be deteriorated, thereby preventing the increase in resistance.
이와 같이 본 발명에 따른 반도체 소자의 제조 방법은 SEG(Selective Epitaxial Growing)공정을 이용하여 게이트 전극의 상부를 성장시킴으로써 T자형으로 게이트 전극을 확장하여 게이트 전극상부의 면적을 증가 킬 수 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an upper portion of the gate electrode is grown by using a selective epitaxial growing (SEG) process, thereby increasing the area of the upper portion of the gate electrode by extending the gate electrode in a T shape.
또한 게이트 전극상부의 면적이 증가됨에 따라 금속 샐리사이드막과 게이트 전극의 접촉면이 넓어짐으로 인해 게이트 전극의 저항을 감소시키고 금속 샐리사이드가 열화되는 것을 방지할 수 있다.In addition, as the area of the gate electrode is increased, the contact surface between the metal salicide film and the gate electrode is widened, thereby reducing the resistance of the gate electrode and preventing the metal salicide from deteriorating.
또한 게이트 전극의 측벽에 충분한 스페이서 영역을 확보함으로써 게이트 CD를 확보할 수 있고 채널길이를 보호해준다.In addition, by securing a sufficient spacer area on the sidewall of the gate electrode can secure the gate CD and protect the channel length.
Claims (11)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0974199A (en) * | 1995-01-12 | 1997-03-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| KR19990009248A (en) * | 1997-07-08 | 1999-02-05 | 문정환 | Transistors and manufacturing methods thereof |
| KR19990023737A (en) * | 1997-08-28 | 1999-03-25 | 푸르셀 데이비드 지. | Method and resulting structure for forming an integrated circuit structure with enhanced metal silicide contacts using notched sidewall spacers on the gate electrode |
| KR19990084304A (en) * | 1998-05-04 | 1999-12-06 | 김영환 | Semiconductor device and manufacturing method thereof |
| KR20010054169A (en) * | 1999-12-03 | 2001-07-02 | 박종섭 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0974199A (en) * | 1995-01-12 | 1997-03-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| KR19990009248A (en) * | 1997-07-08 | 1999-02-05 | 문정환 | Transistors and manufacturing methods thereof |
| KR19990023737A (en) * | 1997-08-28 | 1999-03-25 | 푸르셀 데이비드 지. | Method and resulting structure for forming an integrated circuit structure with enhanced metal silicide contacts using notched sidewall spacers on the gate electrode |
| KR19990084304A (en) * | 1998-05-04 | 1999-12-06 | 김영환 | Semiconductor device and manufacturing method thereof |
| KR20010054169A (en) * | 1999-12-03 | 2001-07-02 | 박종섭 | Method for manufacturing semiconductor device |
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