KR20030051038A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20030051038A KR20030051038A KR1020010081936A KR20010081936A KR20030051038A KR 20030051038 A KR20030051038 A KR 20030051038A KR 1020010081936 A KR1020010081936 A KR 1020010081936A KR 20010081936 A KR20010081936 A KR 20010081936A KR 20030051038 A KR20030051038 A KR 20030051038A
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- Prior art keywords
- gate
- oxide film
- gate electrode
- semiconductor substrate
- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 38
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 3
- 239000010941 cobalt Substances 0.000 claims abstract description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010936 titanium Substances 0.000 claims abstract description 3
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 3
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000005498 polishing Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명의 반도체 소자의 제조 방법에 관한 것으로, 반도체 소자가 고집적화 되어감에 따라 증가하는 게이트의 저항을 감소시키기 위해서 상감법을 이용하여 T자형 게이트를 제조함으로써 금속 샐리사이드막이 형성되는 부분의 면적을 증가 시켜 저항을 감소시키고 열적 안정성을 높일 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, wherein the area of the metal salicide film is formed by fabricating a T-shaped gate using the damascene method to reduce the resistance of the gate, which increases as the semiconductor device becomes highly integrated. It relates to a method for manufacturing a semiconductor device that can increase the resistance to reduce the thermal stability.
고집적 CMOS 소자의 제조에 있어서 게이트의 저항감소는 소자의 속도를 증가시키는 작용을 한다. 종래에 게이트 저항을 감소시키기 위해 여러 가지방법이 시도되고 있으나 가장 널리 쓰이는 방법이 폴리 실리콘 게이트 상에 금속 샐리사이드막을 형성시켜 저항을 감소시키는 것이다.In the fabrication of highly integrated CMOS devices, the reduced resistance of the gate serves to increase the device speed. Conventionally, various methods have been tried to reduce the gate resistance, but the most widely used method is to form a metal salicide film on the polysilicon gate to reduce the resistance.
도 1 은 종래 기술에 따른 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 1을 참조하면, 트랜치(2)가 형성된 반도체 기판(1)상에 게이트 산화막(Gate oxide)(3) 및 폴리 실리콘(Poly-Si)(4)을 증착하고 게이트 전극 패터닝 하여 게이트 전극(5)을 형성한 후 LDD이온 주입공정을 실시한다. 전체 구조상부에 산화막(6) 및 질화막(7)을 증착한 후 건식식각을 수행하여 게이트 전극(5) 측벽에 스페이서를 형성한다. 다음으로 소스 및 드레인 이온주입을 실시하고 소정의 공정을 통하여 게이트, 소스 및 드레인부에 금속 샐리사이드막(8)을 증착하여 반도체 소자를 형성한다.Referring to FIG. 1, a gate oxide 3 and a poly-Si 4 are deposited on a semiconductor substrate 1 on which a trench 2 is formed, and a gate electrode is patterned to form a gate electrode 5. ), Then LDD ion implantation process is performed. After the oxide film 6 and the nitride film 7 are deposited on the entire structure, a dry etching is performed to form spacers on the sidewalls of the gate electrode 5. Next, a source and a drain ion implantation are performed, and a metal salicide film 8 is deposited on the gate, source and drain portions through a predetermined process to form a semiconductor device.
상기와 같이 게이트 전극(5) 상부에 금속 샐리사이드막(8)을 증착하는 방법은 게이트 저항을 크게 감소시키는 효과를 주지만 최근 게이트 선 폭이 감소함에따라 저항값 자체가 증가하는 현상과 또한 후속 열공정에서 금속 샐리사이드막(8)이 열화되어 저항이 증가하는 현상이 발생하고 있다.As described above, the method of depositing the metal salicide film 8 on the gate electrode 5 greatly reduces the gate resistance, but the resistance value itself increases with the recent decrease of the gate line width, and also the subsequent column. In the process, the metal salicide film 8 deteriorates and a phenomenon in which resistance increases is occurring.
따라서 본 발명은 상술한 단점을 해소할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned disadvantages.
본 발명의 다른 목적은 상감법을 이용하여 T자형 게이트를 형성하여 게이트 전극 상부에 금속 샐리사이드막이 형성되는 부분의 면적을 증가할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing the area of a portion where a metal salicide film is formed on the gate electrode by forming a T-shaped gate using the damascene method.
본 발명의 특징에 의하면 게이트 전극 상부에 금속 샐리사이드막이 형성되는 면적을 증가시켜 후속 열공정시 금속 샐리사이드막이 열화되는 것을 방지하고 게이트 전극의 저항을 감소시킬 수 있다.According to an aspect of the present invention, an area in which a metal salicide film is formed on the gate electrode may be increased to prevent deterioration of the metal salicide film during subsequent thermal processes and to reduce resistance of the gate electrode.
도 1 은 종래 기술에 따른 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2a 내지 2m은 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도.2A to 2M are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1, 11 : 반도체 기판2, 12 : 트랜치1, 11: semiconductor substrate 2, 12: trench
3, 22 : 게이트 산화막4, 23 : 폴리 실리콘3, 22: gate oxide film 4, 23: polysilicon
8, 25 : 샐리사이드막6, 13, 16, 20 : 산화막8, 25: salicide film 6, 13, 16, 20: oxide film
7, 17, 19 : 질화막14 : 포토레지스트 패턴7, 17, 19: nitride film 14: photoresist pattern
15 : 가상 게이트18 : 그루브15 virtual gate 18 groove
21 : 스페이서5, 24 : 게이트 전극21: spacer 5, 24: gate electrode
소자 분리막이 형성된 반도체 기판상에 제 1 산화막을 증착한 후 게이트 마스크 패터닝을 통해 가상 게이트가 형성되는 단계, 상기 반도체 기판 내에 LDD영역이 형성되는 단계, 전체 구조 상부에 제 2 산화막 및 제 1 질화막을 증착한 후 평탄화 공정을 수행하여 상기 가상 게이트를 노출시키는 단계, 상기 제 2 산화막의 일부 및 상기 가상 게이트를 제거하여 그루브를 형성하여 상기 반도체 기판의 일부가 노출되는 단계, 상기 그루브 내측벽에 제 2 질화막 및 제 3 산화막으로 이루어진 스페이서가 형성되는 단계, 상기 노출된 반도체 기판상에 게이트 산화막이 형성되는 단계, 상기 전체 구조 상부에 폴리 실리콘을 증착한 후 평탄화 공정을 수행하여 상기 제 1 질화막을 노출시키는 단계, 상기 제 1 질화막, 상기 제 2 질화막의 일부 및 상기 제 2 산화막을 제거하여 게이트 전극을 형성하는 단계, 및 상기 반도체 기판에 이온을 주입하여 소스및 드레인을 형성하는 단계를 포함하여 이루어 진것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.Depositing a first oxide film on the semiconductor substrate on which the device isolation layer is formed, and then forming a virtual gate through gate mask patterning, forming an LDD region in the semiconductor substrate, and forming a second oxide film and a first nitride film over the entire structure Exposing the virtual gate by performing a planarization process after the deposition; removing a portion of the second oxide layer and the virtual gate to form a groove to expose a portion of the semiconductor substrate; Forming a spacer including a nitride film and a third oxide film, forming a gate oxide film on the exposed semiconductor substrate, depositing polysilicon over the entire structure, and then performing a planarization process to expose the first nitride film. Step, removing the first nitride film, part of the second nitride film and the second oxide film To provide a step of forming a gate electrode, and a method of manufacturing a semiconductor device, characterized by jingeot made, including forming source and drain by ion implantation in the semiconductor substrate.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2m은 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도이다.2A to 2M are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 소자분리막(12)이 형성된 반도체 기판(11)상에 제 1 산화막(13)을 증착한 후 포토레지스트 패턴(Photo-Resist pattern)(14)을 형성한다. 구체적으로 상기 제 1 산화막(13)은 열산화막 이나 TEOS로 약 1500 내지 2500Å의 두께로 증착한다. 상기 제 1 산화막(13) 상부에 포토레지스트를 도포한 후 게이트 마스크(Gate mask)를 이용하여 게이트용 포토레지스트 패턴(14)을 형성한다. 이때 게이트용 포토레지스트 패턴(14)은 종래의 측벽 스페이서까지 포함한 크기의 패턴으로 형성한다.As shown in FIG. 2A, after the first oxide layer 13 is deposited on the semiconductor substrate 11 on which the device isolation layer 12 is formed, a photo-resist pattern 14 is formed. Specifically, the first oxide film 13 is deposited with a thermal oxide film or TEOS to a thickness of about 1500 to 2500Å. After the photoresist is coated on the first oxide layer 13, a gate photoresist pattern 14 is formed using a gate mask. At this time, the gate photoresist pattern 14 is formed in a pattern having a size including a conventional sidewall spacer.
도 2b 및 2c에 도시한 바와 같이, 게이트용 포토레지스트 패턴(14)을 이용하여 제 1 산화막(13)을 건식식각 공정을 이용하여 측벽 스페이서까지 포함한 크기의가상 게이트(Virtual gate) 전극(15)을 형성하고 게이트용 포토레지스트 패턴(14)을 제거한 후 LDD(Lighty doped drain) 이온주입을 시행하여 반도체 기반내의 활성 영역에 LDD영역을 형성한다. 제 1 산화막(13)의 잔존부분이 추후에 게이트(24)가 될 부분으로써 가상 게이트(15)라고 명명하였다. 구체적으로 가상 게이트(15)는 종래의 게이트 전극 측벽에 형성된 스페이서를 포함한 폭을 갖도록 형성한다. 또한 제 1 산화막(13)의 두께 즉 가상 게이트(15)의 두께도 제조하고자 하는 게이트의 두께와 동일하게 형성한다.As shown in FIGS. 2B and 2C, a virtual gate electrode 15 having a size including a first oxide film 13 to a sidewall spacer using a dry etching process using a photoresist pattern 14 for gate is used. LDD (Lighty doped drain) ion implantation is performed after removing the gate photoresist pattern 14 to form an LDD region in the active region of the semiconductor substrate. The remaining portion of the first oxide film 13 is referred to as the virtual gate 15 as a portion that will be the gate 24 later. Specifically, the virtual gate 15 is formed to have a width including a spacer formed on a sidewall of a conventional gate electrode. In addition, the thickness of the first oxide film 13, that is, the thickness of the virtual gate 15, is also formed to be the same as the thickness of the gate to be manufactured.
도 2d 및 2e에 도시한 바와 같이, 전체 구조상부에 제 2 산화막(16) 및 제 1 질화막(17)을 증착한 후 가상 게이트 전극(15)이 노출되도록 평탄화 한다.As shown in FIGS. 2D and 2E, the second oxide film 16 and the first nitride film 17 are deposited on the entire structure, and then planarized to expose the virtual gate electrode 15.
구체적으로 가상 게이트(15) 측벽에 형성된 제 2 산화막(16)은 반도체 소자에서 LDD로 이용될 부분이므로 제 2 산화막(16)의 두께를 제조하고자 하는 LDD 스페이서(Spacer)(21)의 두께만큼 증착한다. 즉 제 2 산화막(16)은 CVD를 이용하여 약 600 내지 800Å의 두께로 증착된다. 또한 상기 제 2 산화막(16)을 포함한 전체 기판상부에 제 1 질화막(17)을 1500 내지 3000Å의 두께로 증착한 후 상기 가상 게이트 전극(15)을 식각 정지층으로 하는 CMP(Chemical mechenical polishing)공정을 수행하여 제 1 질화막(17) 및 제 2 산화막(16)의 일부를 제거하여 평탄화 한다.Specifically, since the second oxide layer 16 formed on the sidewall of the virtual gate 15 is a portion to be used as the LDD in the semiconductor device, the second oxide layer 16 is deposited by the thickness of the LDD spacer 21 to manufacture the thickness of the second oxide layer 16. do. That is, the second oxide film 16 is deposited to a thickness of about 600 to 800 kW using CVD. In addition, after the first nitride film 17 is deposited on the entire substrate including the second oxide film 16 to a thickness of 1500 to 3000 GPa, a chemical mechenical polishing (CMP) process is performed in which the virtual gate electrode 15 is an etch stop layer. A portion of the first nitride film 17 and the second oxide film 16 is removed and planarized.
도 2f에 도시한 바와 같이, 평탄화 공정에 의해 노출된 가상 게이트 전극(15)과 제 2 산화막(16)의 일부를 식각의 방향성을 가진 건식식각을 실시하여 수직으로만 식각되도록 하여 반도체 기판(11)의 일부를 노출시킨다. 즉 산화막 건식식각을 수행하면 산화막 만이 제거되어 그루브(Groove)(18)가 형성된다.As shown in FIG. 2F, a portion of the virtual gate electrode 15 and the second oxide film 16 exposed by the planarization process are subjected to dry etching with an etching direction so that the semiconductor substrate 11 is etched only vertically. Part of the That is, when the oxide film is dry etched, only the oxide film is removed to form a groove 18.
도 2g 및 2h에 도시한 바와 같이, 전체 구조 상부에 제 2 질화막(19) 및 제 3 산화막(20)을 증착한 후 건식 식각을 실시하여 LDD 스페이서(21)를 형성한다. 구체적으로 제 2 질화막(19)은 100 내지 300Å의 두께로 증착하고 제 3 산화막(20)을 형성할 LDD 스페이서(21)의 두께인 600 내지 800Å으로 증착한다. 건식식각공정을 수행하여 제 3 산화막(20) 및 제 2 질화막(19)의 일부를 제거하여 반도체 기판(11)의 일부를 노출시키고 그루브(18)측벽에 LDD 스페이서(21)를 형성한다.As shown in FIGS. 2G and 2H, the LDD spacer 21 is formed by performing dry etching after depositing the second nitride film 19 and the third oxide film 20 over the entire structure. Specifically, the second nitride film 19 is deposited to a thickness of 100 to 300 kW, and is deposited to 600 to 800 kW, which is the thickness of the LDD spacer 21 to form the third oxide film 20. A dry etching process is performed to remove a portion of the third oxide film 20 and the second nitride film 19 to expose a portion of the semiconductor substrate 11 and to form the LDD spacer 21 on the sidewall of the groove 18.
도 2i 및 2j에 도시한 바와 같이, 노출된 반도체 기판(11)에 게이트 산화막(22)을 형성한 후 전체 구조 상부에 폴리 실리콘층(23)을 증착한 다음 제 1 질화막(17)이 노출되도록 평탄화 한다. 상기 그루브(18)가 매립되도록 폴리 실리콘(23)을 1500내지 2500Å의 두께로 증착한 다음 상기 제 1 질화막(17)을 연마 정지층으로 CMP공정을 수행하여 폴리 실리콘(23)의 일부를 하여 게이트 전극(24)을 형성한다. 상기의 과정에 의해 T형의 게이트 전극(24)을 형성하여 종래의 게이트 전극보다 상부의 사이즈(Size)가 증가된 게이트 전극(24)를 형성할 수 있다.As shown in FIGS. 2I and 2J, after forming the gate oxide layer 22 on the exposed semiconductor substrate 11, the polysilicon layer 23 is deposited on the entire structure, and then the first nitride layer 17 is exposed. Flatten. The polysilicon 23 is deposited to a thickness of 1500 to 2500Å so that the grooves 18 are embedded, and then the first nitride film 17 is subjected to a CMP process using a polishing stop layer to form a part of the polysilicon 23 as a gate. The electrode 24 is formed. Through the above process, the T-type gate electrode 24 may be formed to form the gate electrode 24 having an increased size above the conventional gate electrode.
도 2k 및 2l에 도시한 바와 같이, 건식 또는 습식 식각공정에 의해 제 1 질화막(17) 및 제 2 질화막(19)의 일부가 제거된다. 이때 제 2 질화막(19)의 일부가 스페이서(21) 하부에 잔존하여 후속 식각 공정에 의해 게이트 CD가 줄어드는 것을 방지한다. 즉 게이트 채널길이(Channel length)를 보호해 주는 역활을 한다. 또한 건식 혹은 습식 식각공정에 의해 제 2 산화막(16)이 제거되어 반도체 기판(11)의 일부가 노출된다. 노출된 반도체 기판(11)에 소스 및 드레인 이온주입을 실시하여 소스 및 드레인 영역을 형성한다.As shown in FIGS. 2K and 2L, a part of the first nitride film 17 and the second nitride film 19 is removed by a dry or wet etching process. At this time, a part of the second nitride film 19 remains below the spacer 21 to prevent the gate CD from being reduced by the subsequent etching process. In other words, it protects the gate channel length. In addition, the second oxide layer 16 is removed by a dry or wet etching process to expose a part of the semiconductor substrate 11. Source and drain ion implantation is performed on the exposed semiconductor substrate 11 to form source and drain regions.
도 2m에 도시한 바와 같이, 게이트 전극, 소스 및 드레인영역 상부에 코발트 및 티타늄을 증착한 후 열처리하여 샐리사이드(Salicide)막(25)를 증착함으로써 반도체 소자가 형성된다. T자형으로 형성된 게이트 전극(24)에 의해 게이트 전극(24)과 샐리사이드(25)의 접촉면적이 늘어나 게이트 저항을 크게 감소 시켜주고 또한 후속 열처리 공정에서 금속 샐리사이드막(25)이 열화 되어 저항이 증가하는 현상을 막을 수 있다.As illustrated in FIG. 2M, a semiconductor device is formed by depositing a salicide layer 25 by depositing cobalt and titanium on a gate electrode, a source, and a drain region and then performing a heat treatment. The T-shaped gate electrode 24 increases the contact area between the gate electrode 24 and the salicide 25, greatly reducing the gate resistance, and deteriorating the metal salicide film 25 in a subsequent heat treatment process. This increasing phenomenon can be prevented.
이와 같이 본 발명에 따른 반도체 소자의 게이트 전극 제조 방법은 상감법을 이용하여 T자형으로 게이트를 형성하여 게이트 상부의 면적을 증가 킬 수 있다.As described above, in the method of manufacturing a gate electrode of the semiconductor device according to the present invention, an area of an upper portion of the gate may be increased by forming a gate in a T-shape using an inlay method.
또한 게이트 전극상부의 면적이 증가됨에 따라 금속 샐리사이드막과 게이트 전극의 접촉면이 넓어짐으로 인해 게이트 전극의 저항을 감소시키고 금속 샐리사이드막이 열화되는 것을 방지할 수 있다.In addition, as the area of the gate electrode is increased, the contact surface between the metal salicide film and the gate electrode is widened, thereby reducing the resistance of the gate electrode and preventing the metal salicide film from deteriorating.
또한 플로팅 게이트 측벽 하부에 질화막의 일부가 잔존하여 게이트 전극의 CD를 보호할 수 있다.In addition, a portion of the nitride film may remain under the floating gate sidewall to protect the CD of the gate electrode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7419879B2 (en) | 2005-01-12 | 2008-09-02 | Samsung Electronics Co., Ltd. | Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same |
| US7622764B2 (en) | 2003-12-31 | 2009-11-24 | Dongbu Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
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| US7622764B2 (en) | 2003-12-31 | 2009-11-24 | Dongbu Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
| US7795084B2 (en) | 2003-12-31 | 2010-09-14 | Dongbu Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
| US7419879B2 (en) | 2005-01-12 | 2008-09-02 | Samsung Electronics Co., Ltd. | Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same |
| US8044451B2 (en) | 2005-01-12 | 2011-10-25 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device having notched gate MOSFET |
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