WO2005067354A1 - プリント配線基板、その製造方法および回路装置 - Google Patents
プリント配線基板、その製造方法および回路装置 Download PDFInfo
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- WO2005067354A1 WO2005067354A1 PCT/JP2004/018500 JP2004018500W WO2005067354A1 WO 2005067354 A1 WO2005067354 A1 WO 2005067354A1 JP 2004018500 W JP2004018500 W JP 2004018500W WO 2005067354 A1 WO2005067354 A1 WO 2005067354A1
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- metal layer
- layer
- base metal
- wiring board
- printed wiring
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- C—CHEMISTRY; METALLURGY
- C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
- C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
- C02F1/00—Treatment of water, waste water, or sewage
- C02F1/02—Treatment of water, waste water, or sewage by heating
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0346—Deburring, rounding, bevelling or smoothing conductor edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/067—Etchants
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
Definitions
- the present invention relates to a printed wiring board in which a wiring pattern is formed directly on the surface of an insulating film without using an adhesive, a method for manufacturing the printed wiring board, and a circuit device on which electronic components are mounted. More specifically, the present invention relates to a printed wiring board formed from a two-layer board composed of an insulating film and a metal layer formed on the surface of the insulating film, a method for manufacturing the printed wiring board, and an electronic printed circuit board. It relates to a circuit device on which components are mounted.
- a wiring board has been manufactured using a copper-clad laminate obtained by laminating a copper foil on the surface of an insulating film such as a polyimide film using an adhesive.
- the copper-clad laminate as described above is manufactured by heat-pressing a copper foil on an insulating film having an adhesive layer formed on the surface. Therefore, when manufacturing such a copper-clad laminate, the copper foil must be handled alone. However, the lower the copper foil becomes, the thinner the copper foil becomes.The lower limit of the copper foil that can be handled alone is about 91, and when using a thinner copper foil, for example, copper foil with a support The handling becomes very complicated, such as the necessity of using foil. In addition, if a wiring pattern is formed using a copper-clad laminate on which a thin copper foil as described above is attached using an adhesive on the surface of the insulating film, the adhesive used to attach the copper foil is used.
- the printed wiring board is warped by the heat shrinkage of the printed wiring board.
- printed wiring boards are becoming thinner and lighter.
- Such printed wiring boards have a three-layer copper-clad structure consisting of an insulating film, an adhesive, and copper foil. It is becoming impossible to cope with laminates.
- a laminate having a two-layer structure in which a metal layer is directly laminated on the surface of an insulating film without using an adhesive is used.
- Such a laminate having a two-layer structure is manufactured by depositing a seed layer metal on the surface of an insulating film such as a polyimide film by a vapor deposition method, a sputtering method or the like. And as above After depositing a copper plating on the surface of the deposited metal, a desired wiring pattern can be formed by applying a photoresist, exposing and developing, and then etching.
- a two-layer laminate is suitable for manufacturing very fine wiring patterns with a wiring pattern pitch width of less than 30 m formed due to the thin metal copper layer.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2003-188495 discloses a first metal layer formed on a polyimide resin film by a dry film forming method, and a first metal layer formed on the first metal layer by a plating method.
- a method of manufacturing a printed wiring board wherein a pattern is formed by etching on a metal-coated polyimide film having a conductive second metal layer, the etching surface is cleaned with an oxidizing agent after the etching.
- An invention of a method for manufacturing a wiring substrate such as a pudding, which is characterized by the above, is disclosed.
- Example 5 of Patent Document 1 shows an example in which a nickel-chromium alloy is plasma-deposited to a thickness of lOnm, and then copper is deposited to a thickness of 8 m by a plating method.
- the metal-coated polyimide film having a two-layer structure formed in this manner By using the metal-coated polyimide film having a two-layer structure formed in this manner, a force capable of forming a fine wiring pattern is obtained. Migration occurs from the metal layer, and short-circuiting between adjacent wiring patterns easily occurs due to migration. In particular, when metals such as nickel and chromium are sputtered onto a polyimide film, some of these metals combine with the components that form the polyimide film, and the metals combined with such polyimide components come into contact with the etchant. Some of them are easily removed and remain on the surface of the polyimide film.
- a comb-shaped electrode is formed, and a force applied to a wiring pattern formed between the comb-shaped electrodes is applied.
- a solder resist ink is applied so that a line pattern is formed and the terminal parts (inner leads and outer leads) are exposed, and then cured to form a solder resist layer.
- the terminal portion is subjected to a plating process, and the terminal portion formed through the process described in the above-mentioned publication is subject to occurrence of migration from the first metal layer formed on the polyimide film. It is difficult to prevent it effectively.
- Patent Document 2 Japanese Unexamined Patent Application Publication No. 2003-282651 discloses the bonding of the flexible insulating film and the wiring pattern to the surface of the flexible insulating film 2.
- a metal layer 1 made of an alloy of copper and a metal other than copper is provided, and a composite power flexible circuit board having a copper foil disposed on the surface of the metal layer 1 is described. I have. Further, as shown in FIG. 5, the lead portion of the wiring pattern formed using such a composite is described as remaining in the lower part of the periphery as a non-removed portion, as shown in FIG.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2003-188495
- Patent Document 2 JP 2003-282651 A
- an object of the present invention is to eliminate the problems inherent in a printed wiring board using a two-layer metal-coated polyimide film. [0010] That is, an object of the present invention is to provide a method for manufacturing a printed wiring board whose insulation resistance value is less likely to fluctuate using a two-layer metal-coated polyimide film. Another object of the present invention is to provide a printed wiring board formed as described above, in which the insulation resistance value is less likely to fluctuate.
- a further object of the present invention is to provide a circuit device in which an electronic component is mounted on a printed wiring board as described above.
- the printed wiring board of the present invention has a printed wiring board having a wiring pattern comprising a base metal layer and a conductive metal layer formed on the base metal layer on at least one surface of the insulating film.
- the width of the lower end of the conductive metal layer in the cross section of the wiring pattern is smaller than the width of the upper end of the base metal layer in the cross section.
- the printed wiring board of the present invention is a printed wiring board in which a wiring pattern comprising a base metal layer and a conductive metal layer formed on the base metal layer is formed on the surface of the insulating film.
- the substrate also includes a mode in which at least the base metal layer exposed on the side wall of the wiring pattern is concealed by the concealment layer.
- a conductive metal is deposited on the surface of the base metal layer, and the conductive metal is deposited.
- Forming a wiring pattern by forming a conductive metal layer and then selectively etching the base metal layer and the conductive metal layer to form a wiring pattern.
- the conductive metal layer is brought into contact with an etching solution that dissolves the conductive metal to form a wiring pattern, and then is brought into contact with a first treatment solution that dissolves the metal that forms the base metal layer, and then the conductive pattern is formed.
- the method comprises depositing a base metal layer containing Ni and Cr on at least one surface of the insulating film, and then depositing a conductive metal on the surface of the base metal layer. Forming a conductive metal layer, and then selectively etching the base metal layer and the conductive metal layer to form a wiring pattern.
- the method comprises contacting the base metal layer and the conductive metal layer with an etching solution that dissolves the conductive metal to form a wiring pattern, and then forming Ni from the metal forming the base metal layer.
- a contact is made with a first processing solution that dissolves, and then the formed wiring pattern is brought into contact with a microetching solution that dissolves copper to retreat the conductive metal layer and form a contoured base metal layer around the wiring pattern.
- the method for producing a printed wiring board of the present invention comprises, after depositing a base metal layer on the surface of the insulating film, forming a conductive metal layer by depositing a conductive metal on the surface of the base metal layer, A method of manufacturing a printed wiring board having a step of forming a wiring pattern by selectively etching a base metal layer and a conductive metal layer, wherein the base metal layer and the conductive metal layer are formed of a conductive metal. After forming a wiring pattern by contacting the wiring pattern with an etching solution that dissolves the metal forming the base metal layer, the formed wiring pattern is subjected to a concealment plating process. As
- an electronic component is mounted on the printed wiring board as described above.
- the printed wiring board of the present invention is preferably such that the width of the lower end of the conductive metal layer in the cross section of the wiring pattern is smaller than the width of the upper end of the base metal layer in the cross section.
- the width of the lower end (bottom) of the conductive metal layer in the cross section of the wiring pattern is usually within a range of 0.1 to 4 m from the width of the upper end of the contoured base metal layer in contact with the conductive metal layer.
- the electric resistance between the wiring patterns formed on the printed wiring board is stable over time as described above, so that the circuit device of the present invention can be used for a long time. Can be used stably.
- FIG. 1 is a view showing a cross section of a substrate in a step of manufacturing a printed wiring board according to the present invention.
- FIG. 2 is a view showing a cross section of the substrate in another embodiment of the process of manufacturing the printed wiring board of the present invention.
- FIG. 3 is a cross-sectional view showing a cross section of the printed wiring board of the present invention.
- FIG. 4 is a cross-sectional view showing a cross section of another example of the printed wiring board of the present invention.
- FIG. 5 shows an end of the wiring along the insulating film before the microetching process.
- FIG. 6 is a SEM photograph of an end of the wiring along the insulating film after microetching.
- FIG. 7 schematically shows wiring patterns before (FIG. 7 (A)), after (FIG. 7 (B)), and after microetching (FIG. 7 (C)) treatments with the first treatment liquid.
- FIG. 7 schematically shows wiring patterns before (FIG. 7 (A)), after (FIG. 7 (B)), and after microetching (FIG. 7 (C)) treatments with the first treatment liquid.
- FIG. 1 and 2 are views showing a cross section of a substrate in a step of manufacturing a printed wiring board according to the present invention.
- common members are assigned common numbers. Is attached.
- the printed wiring board of the present invention has a wiring pattern formed on at least one surface of the insulating film. Therefore, in the printed wiring board of the present invention, the wiring pattern is formed on one surface of the insulating film. Or may be formed on two surfaces, the front surface and the back surface of the insulating film.
- the following description is an example in which a wiring pattern is formed on one surface of an insulating film, and the same can be applied to a case where a wiring pattern is formed on the other surface.
- the insulating film 11 used is a polyimide film, a polyimide amide film, a polyester, Examples include lensulphide, polyetherimide and liquid crystal polymer. That is, these insulating films 11 have heat resistance to such an extent that they are not deformed by heat when forming a base metal layer 12 described later. Further, the insulating film 11 has acid resistance and alkali resistance to the extent that it is not eroded by an etching solution used for etching or an alkaline solution used for cleaning. As a preference, a polyimide film is preferred! /.
- Such an insulating film 11 usually has an average thickness of 7 to 80 ⁇ m, preferably 7 to 50 ⁇ m, and particularly preferably 15 to 40 / zm. Since the printed wiring board of the present invention is suitable for forming a thin substrate, it is preferable to use a thinner polyimide film.
- the surface of the insulating film 11 may be subjected to a roughening treatment using hydrazine or a solution, a plasma treatment, or the like in order to improve the adhesion of the base metal layer 13 described below. Good.
- a base metal is deposited on at least one surface of such an insulating film to form a base metal layer 12.
- the base metal layer 12 is formed on at least one surface of the insulating film 11 and improves the adhesion between the conductive metal layer formed on the surface of the base metal layer 12 and the insulating film 11. is there.
- Examples of the metal forming the base metal layer 12 include copper, nickel, chromium, molybdenum, tungsten, silicon, palladium, titanium, vanadium, iron, cono- lt, manganese, aluminum, zinc, and tin. And tantalum. These metals are They can be used alone or in combination. Nickel among these metals
- the base metal layer 12 is formed using chromium or an alloy thereof.
- a base metal layer 12 is preferably formed on the surface of the insulating film 11 by using a dry film forming method such as an evaporation method or a sputtering method.
- the thickness of such a base metal layer 12 is usually in the range of 100 nm, preferably 2 to 50 nm.
- the base metal layer 12 is for stably forming the conductive metal layer 20 on this layer, and has a kinetic energy such that a part of the base metal physically digs into the insulating film surface. It is preferably formed by holding and colliding with the insulating film.
- the base metal layer 12 is particularly preferably a sputtering layer of the base metal as described above.
- a conductive metal layer 20 is formed on the surface of the base metal layer 12, as shown in FIG.
- examples of the metal forming the conductive metal layer 20 include copper or copper alloy.
- Such a conductive metal layer 20 can be formed by a plating method.
- examples of the plating method include an electric plating method and an electroless plating method.
- the thickness of the conductive metal layer 20 as shown in FIG. 2 (D) is usually in a range of 118 m, preferably 2 to 12 m.
- the sputtering metal layer 13 can be formed in the same manner as the base metal layer 12.
- the base metal layer 12 is formed by a sputtering method using nickel and chromium and the conductive metal layer 20 is a copper layer
- the sputtering metal layer 13 can be a sputtered copper layer.
- the thickness of the sputtered copper layer 13 is usually 10 to 2000 nm, preferably 20 to 500 nm.
- the ratio between the average thickness of the base metal layer 12 and the thickness of the sputtered copper layer 13 is usually in the range of 1: 20-1: 100, preferably 1: 25-1: 60.
- a conductive metal layer is further formed on the surface of the sputtering copper layer 13 as shown in FIG. 1 (D).
- the conductive metal layer shown in FIG. 1 (D) is indicated by reference numeral 14 (mesh conductive metal layer).
- the conductive metal layer with the number 14 can be formed by a method such as a sputtering method or a vapor deposition method, but is preferably formed by a plating method such as an electrolytic plating method or an electroless plating method. That is, the plating conductive metal layer 14 needs to have a certain thickness to form a wiring pattern. Therefore, plating methods such as an electrolytic plating method or an electroless plating method are required.
- the average thickness of the metal conductive layer 14 thus formed is usually 0.5-40 / zm, preferably 0.5-17.5 / 5 ⁇ , more preferably 1.5-11.
- the total thickness of the sputtered copper layer 13 and the conductive metal layer 14 is usually 1 to 40 ⁇ m, preferably 1 to 18 ⁇ m, and more preferably 1 to 18 ⁇ m. Is in the range of 2-12 m. Note that it is extremely difficult to find the boundary between the sputtered copper layer 13 and the plating conductive metal layer 14 after the plating conductive metal layer 14 is formed from the cross-sectional structure thereof. Yes, especially when both are formed with the same conductive metal force, the two are integrated. Therefore, in the present invention, when it is not particularly necessary to distinguish between the two, the two are integrated into a conductive metal. Sometimes referred to as the conductive metal layer 20.
- a photosensitive resin is applied to the surface of the conductive metal layer 20, and The photosensitive resin is exposed and developed to form a desired pattern 15 made of the photosensitive resin.
- a photosensitive resin that cures when irradiated with light can be used, and a photosensitive resin that cures when exposed to light can be used.
- sexual fats can also be used.
- the pattern 15 formed using the photosensitive resin as described above is used as a masking material to selectively form the conductive metal layer 20. Etching is performed to form a desired wiring pattern.
- the etching agent used here is an etching agent for a conductive metal.
- a conductive metal etching agent include an etching solution containing ferric chloride as a main component, and a chloride.
- An etchant containing cupric copper as a main component, an etchant such as sulfuric acid + hydrogen peroxide, and an etchant for such a conductive metal can be used to select the conductive metal layer 20 with an excellent selectivity.
- Ability to form a wiring pattern by etching with a property The substrate metal layer 12 between the conductive metal layer 20 and the insulating film 11 also has a considerable etching function.
- the base metal layer 12 is formed on the surface of the insulating film 11 by several nm.
- the base metal layer 12 can be etched to such an extent that it remains as a very thin layer. That is, the base metal layer forms an extremely thin layer between the wiring patterns, and the base metal layer is formed without being etched under the wiring pattern composed of the conductive metal layer. It has the same thickness as.
- the desired pattern 15 made of a photosensitive resin at the time of forming the wiring pattern as described above is subjected to, for example, the above-described etching step and, before being subjected to the next step, for example. It is removed by alkaline washing.
- the surface of the conductive metal layer 20 forming the wiring pattern and the base metal Is preferably etched as shown in FIG. 1 (G) to perform micro-etching for removing an oxide film or the like on the surface.
- an etching solution generally used as an etching solution for a conductive metal can be used.
- an etchant used for pickling such as HC1 or HSO.
- the conductive metal layer 20 is selectively etched as described above, and micro-etching (pickling treatment) is performed as necessary. Then, as shown in FIG. It is treated with a first treatment liquid that can dissolve Ni and Ni alloy such as Ni—Cr alloy forming the base metal layer.
- a first treatment liquid that can dissolve Ni and Ni alloy such as Ni—Cr alloy forming the base metal layer.
- Ni here means to dissolve a Ni-Cr alloy or other Ni alloy, leaving almost no Ni residue, but leaving some metals other than Ni (Cr in the case of Ni-Cr alloy ).
- examples of the first processing solution in which Ni can be dissolved include a mixed solution of sulfuric acid and hydrochloric acid having a concentration of about 5 to 15% by weight.
- a part of the metal contained in the base metal layer 12 is removed by performing treatment using the first treatment liquid capable of dissolving Ni.
- the treatment temperature is usually 30 to 55 ° C, preferably 35 to 45 ° C, and the treatment time is usually not longer. It is usually 2-40 seconds, preferably 2-30 seconds.
- the shortest distance W between the base metal layers varies depending on the wiring pitch. For example, when the wiring pitch is 30 m (designed line width 15 ⁇ m, space width 15 ⁇ m), the shortest distance between the base metal When measured by an electron micrograph (SEM image), the distance W is within the range of 5 to 18 m. This distance W is 33% to 120% of the design space width, and is within the range of 10 to 16 / zm. Often become. For example, when the wiring pitch is 100 / zm (designed line width 50 m, space width 50 m), the width is often 10 to 120% of the design space width.
- the wiring pattern is formed by adding the thickness of the metal layer to the base metal layer of the wiring pattern to prevent oxidation and to form an alloy layer during bonding of an IC chip or the like. It is preferable that the shortest distance W between them is 5 ⁇ m or more.
- the fact that the protrusion 21a of the base metal is dissolved and removed here depends on the wiring pitch. However, when the wiring pitch is 30 m, the base metal layer at the base of the protrusion is insulated from the base metal layer. The distance from the boundary to the film to the tip of the projection is the force indicated by "SA" in Fig. 7. This distance SA force SO-6 m (0-40% of the design space width), preferably 0 -5 ⁇ m, more preferably 0-3 m, most preferably 0-2 m, and those within this range are not referred to as protrusions in the present invention.
- FIG. 7 (C) schematically shows an example of the wiring board in a state where the base metal layer is exposed by micro-etching.
- the Cu solution is treated with one of solutions such as potassium persulfate (KSO), sodium persulfate (NaSO), and sulfuric acid + HO.
- KSO potassium persulfate
- NaSO sodium persulfate
- sulfuric acid + HO sulfuric acid + HO
- the turns are selectively microetched to selectively dissolve (retreat) the pattern made of the conductive metal so that the base metal layer (seed layer) projects from the bottom of the pattern.
- the contact time with the etching solution is long, copper, which is a conductive metal forming a wiring pattern, is dissolved.
- the contact time between the etchant and the wiring pattern in this micro-etching step is usually about 2 to 60 seconds, preferably about 10 to 45 seconds, because the amount of output increases and the wiring pattern itself becomes thinner.
- the wiring pattern is formed with a second processing liquid capable of dissolving Cr and dissolving an insulating film such as polyimide.
- the surface layer of the insulating film 11 that has not been formed is treated. That is, according to the present invention, after the treatment using the first treatment solution capable of dissolving Ni, and further, if necessary, the micro opening etching, the Cr remaining as the base metal layer (seed layer) is obtained. Is partially dissolved, and the undissolved Cr layer portion is treated with a second treatment solution for oxidizing and passivating, thereby removing most of the base metal layer 12 and performing the second treatment.
- the liquid can passivate the Cr remaining on the surface of the insulating film 11 by several tens of A, and passivate the Cr. Therefore, as shown in FIG. 1 (1) and FIG. 2 (1), by using this second treatment liquid, the base metal layer 12 is removed, and the residual Cr is oxidized to passivation. Can be
- Examples of the second treatment liquid used here include an aqueous solution of potassium permanganate + KOH, an aqueous solution of potassium dichromate, and an aqueous solution of sodium permanganate + NaOH.
- the concentration of potassium permanganate is usually 10 to 60 gZl, preferably 25 to 55 gZl, and the concentration of KOH is preferably 10 to 30 gZl. is there.
- the treatment temperature is usually 40 to 70 ° C., preferably 50 to 65 ° C.
- the treatment time is usually 10 to 60 seconds. , Preferably for 15-45 seconds.
- the width W1 of the upper end of the base metal layer 12 at the lower end of the wiring pattern of the obtained printed wiring board is equal to the width of the conductive metal layer 20 (sputtered phosphorus).
- the width is formed wider than the width W2 of the lower end portion of the sputtering copper layer (the value of W1-W2 is usually 0.1-4.0 m, preferably 0.4-m).
- the width W3 of the overhang portion of the base metal layer 12 on one side is usually equal to the width (cross-sectional width) of the base metal layer 12 on one side of the overhang portion of the base metal layer 12. It is desirable that the width W3 is generally 0.05 to 2.0 m, preferably 0.2 to 1.0 m wider than the width W2 of the lower end portion of the conductive metal layer.
- FIGS. 5 and 6 show SEM photographs (FE-SEM photographs) of the end of the wiring along the insulating film before and after the microetching process.
- the white part at the lower right is the conductive metal layer (copper layer) of the wiring, and the micro-etching process performed in the state shown in FIG.
- W3 about 0.4 / zm
- the wiring patterns After forming the wiring patterns as described above, it is preferable to perform a concealing process so as to conceal at least the base metal formed at the lower part of the side wall of each of the formed wiring patterns. That is, as shown in FIG. 1 (J) and FIG. 2 (J), and FIG. 3 and FIG. 4, in the printed wiring board of the present invention, after forming the wiring pattern and before forming the solder resist layer, The exposed portion of the base metal layer 12 at the lower end of the pattern may be concealed by the concealment layer 16.
- the concealed plating layer 16 can be formed on the entire wiring pattern by concealing at least the base metal layer 12 at the lower end of the wiring pattern.
- the concealed plating layer thus formed includes a tin plating layer, a gold plating layer, a nickel-gold plating layer, a solder plating layer, a lead-free solder plating layer, a Pd plating layer, a Ni plating layer, a Zn plating layer, and a Cr plating layer.
- a tin plating layer, a gold plating layer, a nickel plating layer, and a nickel-gold plating layer are preferable as long as they are at least one kind of plating layer from which the group strength is also selected. Further, as described later, after the pattern is partially covered with a solder resist before plating, the exposed portion may be plated with the above-described metal.
- the thickness of such a concealing plating layer can be appropriately selected depending on the type of plating.
- the thickness of the plating layer is usually 0.005 to 5. O ⁇ m, preferably 0.005. — 3.
- the thickness is set within the range of O / zm.
- plating may be performed on the entire surface, a solder resist may be partially printed, and then the same metal may be plated again on exposed portions. Concealment message of such thickness Even when the key layer is formed, migration from the base metal layer 12 does not occur.
- Such a concealed plating layer can be formed by an electrolytic plating method or an electroless plating method.
- the concealment plating process on the wiring pattern in this manner, the surface of the passivated base metal layer on the insulating substrate side of the wiring pattern is concealed by the concealment plating layer, and a potential difference is generated between dissimilar metals.
- the insulation resistance between the wires is sufficiently high, migration from the base metal layer can be effectively prevented.
- the base metal layer 12 serving as a base is passivated! / Don't happen! / ,.
- solder resist ink After concealing the side surface of the base metal layer on which the wiring pattern is formed by concealment treatment or without concealment, the solder resist ink is so exposed that the terminal portion of the wiring pattern is exposed. Is applied and cured to form a solder resist layer.
- the terminal portions exposed from the solder resist layer are plated.
- the plating process is usually performed for bonding to an electronic component, and the plating layer obtained by this process forms a surface of the internal connection terminal and a surface of the external connection terminal formed on the printed wiring board. Is formed.
- the plating layer may have the same plating layer strength as formed on the entire wiring pattern before the formation of the solder resist layer.
- the first plating layer may be formed on the entire wiring pattern, and the plating layer may be formed on portions other than the terminal portions.
- the second plating layer may be formed only on the terminal portion after the formation of the solder resist layer.
- Examples of such a plating layer include an electroless tin plating, an electrolytic tin plating, a solder plating, a nickel plating, a nickel gold plating, a Cu-Sn plating, and a Sn-Bi plating.
- This plating layer may be the same as or different from the concealing plating layer for concealing the base metal layer forming the wiring pattern. No migration occurs due to this treatment, even if the concealment scheme is porous so that the base metal layer is not sufficiently covered, or the plating layer is extremely thin and porous.
- the concealed plating layer formed over the entire wiring pattern can be used in combination as a plating layer for ordinary bonding and the like.
- the thickness of the plating layer formed in this manner is usually 0 to 5 ⁇ m, preferably 0 to 3 ⁇ m.
- the plating layer in this case is heated due to curing of the solder resist layer, etc., and alloying with these metals may progress on the surface side in contact with the base metal layer and Z or the conductive metal layer. is there.
- a tin plating layer is formed, a Cu—Sn alloy layer is formed at the interface with conductive metal copper (particularly a copper layer).
- the alloying of the outermost surface of the plating layer provided in the terminal portion, which is to be joined to the external electrode or the like does not proceed, and if not, the original metal composition is maintained.
- the base metal layer 12 serving as a base is passivated, so that the tin plating layer force from this portion does not generate a whistling force.
- the electric resistance value between the wiring patterns fluctuates significantly due to migration or the like.
- the printed wiring board and the circuit device of the present invention have a practical property between the insulation resistance after the voltage is continuously applied for a long time during which migration and the like do not occur and the insulation resistance before the voltage is applied. No fluctuation is observed, and the printed wiring board has very high reliability.
- the printed wiring board of the present invention has a wiring pattern (or lead) having a width of 30 m or less, preferably 25 to 5 ⁇ m, and a pitch width of 50 ⁇ m or less. It is suitable for a printed wiring board having a pitch width of 40 to 10 ⁇ m.
- Such printed circuit boards include printed circuit boards (PWB), TAB (Tape Automated Bonding) tape, COF (Chip On Film), CSP (Chip Size Package), BGA (Ball Grid Array), ⁇ ⁇ ⁇ -Ball Grid Array), FPC (Flexible Printed Circuit), etc.
- the printed wiring board of the present invention has a structure in which a wiring pattern is formed on the surface of a polyimide film which is an insulating film. An electronic component is mounted on a part of the wiring pattern. Is also good. The electronic component mounted in this manner is usually sealed with a sealing resin to form a circuit device.
- the printed wiring board and the method of the present invention will be described specifically with reference to examples. The present invention is not limited to these.
- insulation resistance values in the following Examples and Comparative Examples are all measured values at room temperature outside a thermo-hygrostat.
- One surface of a polyimide film having an average thickness of 38 ⁇ m was subjected to roughing treatment by reverse sputtering, and then a nickel-chromium alloy was sputtered under the following conditions.
- a chromium-nickel alloy layer having an average thickness of 40 nm was formed as a base metal layer.
- Copper was deposited on the surface of the sputtered copper layer formed as described above by an electric plating method to form an electrolytic copper layer (electric plating copper layer) having a thickness of 8 ⁇ m.
- a photosensitive resin is applied to the surface of the electrolytic copper layer thus formed, exposed and developed, so that the wiring pitch becomes 30 m (line width: 15 ⁇ m, space width: 15 ⁇ m).
- a pattern of a comb-shaped electrode is formed on the substrate, and using this pattern as a masking material, the copper layer is etched for 30 seconds using a 12% concentration copper salt etching solution containing HCl; 100 g / liter and containing 12%. Manufactured.
- the film carrier was treated at 50 ° C. for 30 seconds to dissolve Ni in the base metal layer having a Ni—Cr alloy strength.
- the formed wiring pattern was subjected to electroless tin plating to a thickness of 0.01 ⁇ m.
- solder resist layer was formed so as to expose the connection terminals and the external connection terminals.
- a 0.5 m thick Sn plating is applied to the internal connection terminals and the external connection terminals exposed from the solder resist layer, and heated to a predetermined pure Sn layer (Sn plating total thickness: 0.51 ⁇ m). m, pure Sn layer thickness: 0.25 ⁇ m). After the Sn plating, FE-SEM randomly changed the location and observed 10 places. The shortest distance between the base metal of the wiring was 15. It was present independently between the protrusions and lines of the base metal layer. No base metal layer was observed.
- the printed wiring board on which the comb electrodes were formed was subjected to a continuity test (HHBT) for 1000 hours by applying a voltage of 40 V under the conditions of 85 ° C. and 85% RH.
- the continuity test is accelerated test, the time period force eg insulation resistance to a short circuit occurs is to below 1 X 10 8 ⁇ is, those less than 1000 hours, be used as a general substrate Cannot be done.
- the insulation resistance before the insulation reliability test was 4 4 10 14 ⁇ , which is higher than that of the comparative example.
- the insulation resistance measured after the insulation reliability test was 2 ⁇ 10 14 ⁇ . No substantial difference was found in the insulation resistance due to the applied voltage.
- a photosensitive resin is applied to the surface of the thus formed electrolytic copper layer, exposed and developed, and a comb-shaped electrode is formed so that the wiring pitch becomes 30 m (line width: 15 ⁇ m, space width: 15 ⁇ m).
- the copper layer is etched for 30 seconds using a 12% concentration of a copper salt etchant containing HCl; 100 g / liter and containing 12% to form a wiring pattern. Manufactured.
- the film carrier was treated at 50 ° C. for 30 seconds to dissolve Ni in the base metal layer having a Ni—Cr alloy strength.
- the mixture was treated at 65 ° C for 30 seconds to dissolve Cr contained in the base metal layer.
- This second treatment liquid can dissolve and remove chromium in the base metal layer and passivate a small amount of remaining chromium by passivation.
- the formed wiring pattern was subjected to electroless tin plating to a thickness of 0.01 ⁇ m.
- solder resist layer was formed so as to expose the connection terminals and the external connection terminals.
- a 0.5 m thick Sn plating is applied to the internal connection terminals and the external connection terminals exposed from the solder resist layer, and heated to a predetermined pure Sn layer (Sn plating total thickness: 0.51 ⁇ m). m, pure Sn layer thickness: 0.25 ⁇ m).
- Sn plating total thickness 0.51 ⁇ m
- m, pure Sn layer thickness 0.25 ⁇ m
- FE-SEM randomly changed the location and observed 10 places.
- the shortest distance between the base metal of the wiring was 15. It was present independently between the protrusions and lines of the base metal layer. No base metal layer was observed.
- the printed wiring board on which the comb electrodes were formed was subjected to a continuity test (HHBT) for 1000 hours by applying a voltage of 40 V under the conditions of 85 ° C. and 85% RH.
- the insulation resistance before the insulation reliability test was 4 ⁇ 10 14 ⁇ , which is higher than that of the comparative example.
- the insulation resistance measured after the insulation reliability test was 3
- Example 1 a polyimide film having an average thickness of 75 m (UPILEX S, manufactured by Ube Industries, Ltd.) was used, and one surface of the polyimide film was roughened by reverse sputtering. In the same manner as in Example 1, a nickel-chromium alloy was sputtered to form a chromium-nickel alloy layer having an average thickness of 30 nm, which was used as a base metal layer.
- UPILEX S manufactured by Ube Industries, Ltd.
- Copper was deposited on the surface of the sputtered copper layer formed as described above by an electric plating method to form an electrolytic copper layer having a thickness of 8 ⁇ m.
- a photosensitive resin is applied to the surface of the copper layer thus formed, exposed and developed to form a comb-shaped electrode pattern having a wiring pitch force of S30 ⁇ m, and this pattern is used as a masking material.
- the copper layer using HCl; a 12% concentration of copper salt etchant containing lOOg / liter.
- the wiring pattern was manufactured by etching for 30 seconds.
- the formed masking material was removed, and then a treatment was performed at 30 ° C. for 10 seconds using an HC1 solution as a pickling solution to pickle the copper layer and the base metal layer (Ni—Cr alloy).
- the first treatment liquid containing 13g / L of HC1 + 13g / L of HSO was included.
- Ni of the base metal layer made of Ni—Cr alloy was dissolved at 55 ° C. for 20 seconds.
- solder resist layer was formed so as to expose the connection terminals and the external connection terminals.
- a 0.45 ⁇ m thick Sn plating is applied to the internal connection terminals and the external connection terminals exposed from the solder resist layer, and heated to a predetermined pure Sn layer (pure Sn layer thickness: 0.2 m). ) was formed. After the Sn plating, FE-SEM randomly changed the location and observed 10 places. The shortest distance between the base metal of the wiring was 16.O / zm. No residual base metal layer was observed.
- the printed wiring board on which the comb-shaped electrodes were formed was subjected to a continuity test (HHBT) for 1000 hours by applying a voltage of 40 V under the conditions of 85 ° C. and 85% RH.
- the insulation resistance before the insulation reliability test was 5 ⁇ 10 14 ⁇ higher than that of the comparative example, and the insulation resistance measured after the insulation reliability test was 3 ⁇ 10 " ⁇ . No substantial difference in insulation resistance was observed due to the application of.
- Example 2 a polyimide film having an average thickness of 75 m (UPILEX S manufactured by Ube Industries, Ltd.) was used, and one surface of the polyimide film was roughened by reverse sputtering.
- a nickel-chromium alloy was sputtered to form a chromium-nickel alloy layer having an average thickness of 30 nm, which was used as a base metal layer.
- Copper was deposited on the surface of the sputtered copper layer formed as described above by an electric plating method to form an 8 ⁇ m-thick electrolytic copper layer (conductive metal layer).
- a photosensitive resin is applied to the surface of the copper layer thus formed, exposed and developed to form a comb-shaped electrode pattern having a wiring pitch force of S30 ⁇ m.
- the layer was etched for 30 seconds using a 12% concentration of a copper salt etchant containing HC1; 100 g / liter to produce a wiring pattern.
- the formed masking material was removed, and then a treatment was carried out at 30 ° C. for 10 seconds using an HC1 solution as a pickling solution to pickle the copper layer and the base metal layer (Ni—Cr alloy).
- the first treatment liquid containing 13 g / l of HC1 + 13 g / l of H 2 SO 4 was contained.
- the Ni in the base metal layer made of Ni—Cr alloy was dissolved at 55 ° C. for 20 seconds using the solution.
- solder resist layer was formed so as to expose the connection terminals and the external connection terminals.
- a 0.45 ⁇ m thick Sn plating is applied to the internal connection terminals and the external connection terminals exposed from the solder resist layer, and heated to a predetermined pure Sn layer (pure Sn layer thickness: 0.2 m). ) was formed. After the Sn plating, FE-SEM randomly changed the location and observed 10 places. The shortest distance between the base metal of the wiring was 16.O / zm. No residual base metal layer was observed.
- the printed wiring board on which the comb-shaped electrodes were formed was subjected to a continuity test (HHBT) for 1000 hours by applying a voltage of 40V under the conditions of 85 ° C and 85% RH.
- the insulation resistance before the insulation reliability test was 5 ⁇ 10 14 ⁇ higher than that of the comparative example, and the insulation resistance measured after the insulation reliability test was 2 ⁇ 10 " ⁇ . No substantial difference in insulation resistance was observed due to the application of.
- a printed wiring board was manufactured in the same manner as in Example 1, except that the Cu conductor was dissolved by 1.0 / zm in the depth direction by microetching.
- a continuity test was performed on the printed wiring board on which the comb electrodes were formed in this manner by applying a voltage of 40 V at 85 ° C and 85% RH for 1000 hours.
- the insulation resistance before the insulation reliability test was 6 ⁇ 10 14 ⁇ higher than that of the comparative example, and the insulation resistance measured after the insulation reliability test was 5 ⁇ 10 " ⁇ . No substantial difference in insulation resistance was observed due to the application of. [0095] The results are shown in Table 1.
- a printed wiring board was manufactured in the same manner as in Example 2, except that the Cu conductor was dissolved in the depth direction by 1.0 / zm by microetching.
- a continuity test was performed on the printed wiring board on which the comb electrodes were formed in this manner by applying a voltage of 40 V at 85 ° C and 85% RH for 1000 hours.
- the insulation resistance before the insulation reliability test was 6 ⁇ 10 14 ⁇ higher than that of the comparative example.
- the insulation resistance measured after the insulation reliability test was 5 510 " ⁇ , and the voltage between No substantial difference in insulation resistance was observed due to the application of.
- a 25 ⁇ m-thick polyimide film manufactured by Toray DuPont under the trade name “Kapton 100ENJ” was treated in a 30% hydrazine KOH aqueous solution for 60 seconds. Then, it was washed with pure water for 10 minutes and dried at room temperature.
- This polyimide film was placed in a vacuum deposition apparatus, and after a plasma treatment, a Ni'Cr alloy was deposited to a thickness of 40 nm by sputtering, and copper was deposited to a thickness of 8 ⁇ m by a plating method to form a metal-coated polyimide substrate. Obtained.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Metallurgy (AREA)
- Hydrology & Water Resources (AREA)
- Water Supply & Treatment (AREA)
- Environmental & Geological Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Electroplating Methods And Accessories (AREA)
- ing And Chemical Polishing (AREA)
- Structure Of Printed Boards (AREA)
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Abstract
Description
Claims
Priority Applications (1)
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US10/583,846 US20070145584A1 (en) | 2003-12-26 | 2004-12-10 | Printed wiring board, method for manufacturing same, and circuit device |
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JP2003435685 | 2003-12-26 | ||
JP2003-435685 | 2003-12-26 | ||
JP2004-222185 | 2004-07-29 | ||
JP2004222185A JP3736806B2 (ja) | 2003-12-26 | 2004-07-29 | プリント配線基板、その製造方法および回路装置 |
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PCT/JP2004/018500 WO2005067354A1 (ja) | 2003-12-26 | 2004-12-10 | プリント配線基板、その製造方法および回路装置 |
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US (1) | US20070145584A1 (ja) |
JP (1) | JP3736806B2 (ja) |
KR (1) | KR100864562B1 (ja) |
TW (1) | TW200522219A (ja) |
WO (1) | WO2005067354A1 (ja) |
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JP2016152262A (ja) * | 2015-02-16 | 2016-08-22 | イビデン株式会社 | プリント配線板 |
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JPWO2018221183A1 (ja) * | 2017-05-29 | 2020-03-26 | 住友金属鉱山株式会社 | 透明導電性基板の製造方法、透明導電性基板 |
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- 2004-12-10 KR KR1020067015014A patent/KR100864562B1/ko active IP Right Grant
- 2004-12-10 US US10/583,846 patent/US20070145584A1/en not_active Abandoned
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KR100864562B1 (ko) | 2008-10-20 |
JP3736806B2 (ja) | 2006-01-18 |
JP2005210058A (ja) | 2005-08-04 |
KR20060135724A (ko) | 2006-12-29 |
TW200522219A (en) | 2005-07-01 |
US20070145584A1 (en) | 2007-06-28 |
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