TWI618821B - 製造印刷電路板線路的方法 - Google Patents

製造印刷電路板線路的方法 Download PDF

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TWI618821B
TWI618821B TW106113528A TW106113528A TWI618821B TW I618821 B TWI618821 B TW I618821B TW 106113528 A TW106113528 A TW 106113528A TW 106113528 A TW106113528 A TW 106113528A TW I618821 B TWI618821 B TW I618821B
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copper layer
plating
reverse
ratio
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葉錠強
楊豐吉
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萬億股份有限公司
葉錠強
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Priority to US15/876,140 priority patent/US10306768B2/en
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Priority to US16/115,326 priority patent/US20180368266A1/en
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Abstract

本發明是關於一種製造印刷電路板線路的方法，可提昇高密度互連(HDI)技術中有關類載板型態PCB線路之佈線等級。第一段係藉由還原氧化石墨烯(rGO)導電層的運用，完成電鍍填孔及超薄表面銅層。第二段則以週期性脈衝反向(PPR)電鍍程序增厚線路，再蝕刻去除不需要的銅層。本發明方法製作的線路不僅滿足線寬/線距小於30/30um的要求，且高度均勻而線型方正。

Description

製造印刷電路板線路的方法
本發明是關於一種製造印刷電路板線路方法，特別是藉由還原氧化石墨烯(rGO)導電層及週期性脈衝反向(PPR)電鍍的運用，可提昇高密度互連(HDI)技術中有關類載板型態PCB線路之佈線等級。
印刷電路板(Printed Circuit Board，PCB)是在絕緣基材上，配以電導線路的一種結構性電子元件。當積體電路製程進入微米(um)時代時，PCB之線寬、線距則以毫米(mm)為設計目標。如今，積體電路已進入奈米(nano)製程，而PCB亦步入微米時代，因此，高密度互連(High-Density Interconnection，HDI)技術已廣泛應用在PCB產業。
由於PCB與IC的線寬/線距有相當差異，傳統製程上會先封裝IC於載板上，例如覆晶載板(Flip Chip，FC)，再黏貼於PCB上。藉由載板線路，可將IC線路與PCB線路連結。然而，隨著電子產品以輕、薄、短小為發展方向，省略IC載板而將IC直接封裝所謂類載板型態之PCB上，必然成為趨勢。但首先必須克服PCB線路極細化這個難題。
改良半加成法(Modified Semi-Additive Process，MSAP)為目前用於PCB較可行之製程，主要包括：在鑽孔的銅箔基板上化學沉積形成表面銅層，接著以圖形電鍍填孔及增厚線路，最後去除抗鍍膜及蝕刻掉非線路區的銅箔及表面銅層，得到獨立的線路。
然而，習知MSAP在製作30/30um以下的細線路時，如第1圖所示，仍存在下列問題：
A.表面銅層的厚度不均勻。
B.去除面銅層時易發生側蝕。
C.電鍍增厚線路的高度不均勻。
D.線路無法達到線型方正之截面
本發明的目的在於提供一種製造印刷電路板線路的方法，在無需大幅修改既有製程，亦不需要昂貴的器材或材料的情況下，便可製作高密度且線型優異的細電路。
本發明方法主要包括下列步驟：A.提供一完成鑽孔的覆銅基板，將還原氧化石墨烯(rGO)導電層修飾在孔內壁；B.實施電鍍程序，同時完成該孔內部鍍填銅與表面銅層，該表面銅層的厚度為1~20um，且高低差不大於10%；C.在該表面銅層表面的非線路區形成抗鍍乾膜，線路區則包括寬度為5~50um的細線路，線距為5~50um；D.實施週期性脈衝反向電鍍程序，於線路區 形成一增厚銅層，其高度為5~50um，且高低差不大於15%；E.去除抗鍍乾膜；F.實施蝕刻程序，去除非線路區的表面銅層。
週期性脈衝反向電鍍程序的正向電流密度較佳為0.5~5 ASD，正向與反向的電流密度比較佳為1：1~1：10，更佳為1：1~1：5；正向與反向的時間比較佳為2：1~50：1，更佳為10：1~25：1。
第1圖顯示習知MSAP在製作30/30um以下的細線路時，電鍍增厚線路的高度不均勻且無法達到線型方正之截面。第2圖為第1圖之比較圖，但盲孔底部保留金屬層。
第2圖顯示互連基板之盲孔，可藉由rGO之運用，得到極薄之表面銅層及良好之填孔效果。
第3圖顯示以PPR方式進行圖型電鍍，無論高低電流區其大平面、密集線路區、或孔疏孔密，其厚度均勻度及線型方正之截面均可得良好之效果。
以下實施步驟的操作條件可視環境逕行調整搭配，文中所述僅為建議之較佳範圍。
實施例1
A. 修飾rGO於孔洞中(SLOTOGO)
取表面鑽好盲孔的銅箔基板，銅箔厚度為3um，盲孔 的直徑為75um，深度為50um，盲孔間距最小為0.3mm。將基板浸入調節劑(PVI金屬鹽類Polyvinylimidazole，PVI)水溶液中，使盲孔底面及內壁形成高分子層。調節劑水溶液濃度為4-10g/L，控制在pH 3-6，溫度為60℃。10分鐘後，取出水洗並吹乾。
接著，將基板浸入氧化石墨烯(Graphene Oxide，GO)水溶液中，使氧化石墨烯吸附並鍵結於孔洞內壁的PVI層。氧化石墨烯溶液濃度為0.1-1g/L，控制在pH 3-6，溫度為60℃。10分鐘後，取出水洗並吹乾。
對基板施予H2之電漿，進行還原作業10分鐘。使孔洞內壁的氧化石墨烯(GO)還原為還原氧化石墨烯(rGO)。
B. 電鍍填孔及表面銅層
電鍍前，先以酸性清潔劑(SCHLOTTER公司的產品SLOTOCLEAN S 20，0.5-5%)清洗基板，除去表面的雜質。15-30℃下進行3-10分鐘後，取出水洗。接著，將基板浸入微蝕刻溶液(SCHLOTTER公司的產品SLOTOETCH 584，10-40g/L)中，進一步除去氧化皮膜。15-30℃下進行3-10分鐘後，取出水洗。
將清洗後的基板浸入電鍍溶液中進行電鍍作業，使用SCHLOETTER的2.5L電解槽。電鍍溶液包括CuSO4(220g/L)，H2SO4(40g/L)，氯離子(60ppm)，載運劑(SCHLOTTER公司的產品SLOTOCOUP 31，5ml/L)，光澤劑(SCHLOTTER公司的產品SLOTOCOUP 32，0.2ml/L)，整平劑(SCHLOTTER公司的產品 SLOTOCOUP 33，0.18ml/L)。電流密度為10 ASF，較低攪拌強度，時間為50分鐘。銅離子與rGO鍵結後沉積在盲孔中，並在基板表面形成均勻銅層，含銅箔的總厚度只有6.2um，如第2圖所示。
C. 非線路區抗鍍處理
對表面銅層進行清潔、微蝕刻後，貼覆一層抗電鍍油墨。藉由曝光顯影，在非線路區的表面形成抗鍍乾膜。線路區的細線路設計寬度為30um，線距為30um。
D. PPR電鍍增厚線路
對線路區實施週期性脈衝反向(Periodic Pulse Reverse，PPR)垂直電鍍程序，電鍍溶液包括CuSO4(80g/L)，H2SO4(200g/L)，氯離子(100ppm)，添加劑(SCHLOTTER公司的產品SLOTOCOUP CU211，10ml/L；SLOTOCOUP CU212，0.15ml/L)。正向電流密度為2 ASD，正向與反向的電流密度比為1：2，正向與反向的時間比為20：1，正常攪拌強度，電鍍時間為60分鐘。
E. 去除抗鍍乾膜及表面銅層
將抗鍍乾膜剝除後，實施差分蝕刻(differential etching)程序，快速去除非線路區的面銅層，留下獨立的細線路。
第3圖顯示以進行PPR電鍍所得到的細線路，其中(a)為平行線路方向的縱剖面，線高範圍為22.02~22.81um，高低差僅 3.5%；(b)~(d)為垂直的縱剖面，線高範圍為20.59~21.73um，高低差僅5.2%。
由上圖可得知，本發明製程具有下列特徵及優點：
A.以rGO運用之PTH製程，實施全板填孔電鍍(PANEL PLATING)不僅填孔效果良好，表面銅層的厚度及均勻度皆可達到要求。
B.最後進行蝕刻程序時，可快速移除薄而均勻的表面銅層，不會有側蝕問題發生。
C.以PPR電鍍方式實施圖電增厚(PATTERN PLATING)，不僅線寬線距滿足精細線路規格(表層均勻及線型方正)，且線路高度均勻。

Claims (3)

  1. 一種製造印刷電路板線路的方法，包括下列步驟：A.提供一完成鑽孔的覆銅基板，將還原氧化石墨烯(rGO)導電層修飾在孔內壁；B.實施電鍍程序，同時完成該孔內部鍍填銅與表面銅層，該表面銅層的厚度為1~20um，且高低差不大於10%；C.在該表面銅層表面的非線路區形成抗鍍乾膜，線路區則包括寬度為5~50um的細線路，線距為5~50um；D.實施週期性脈衝反向電鍍程序，於線路區形成一增厚銅層，其高度為5~50um，且高低差不大於15%；E.去除抗鍍乾膜；F.實施蝕刻程序，去除非線路區的表面銅層。
  2. 如請求項1的方法，其中該週期性脈衝反向電鍍程序的正向電流密度為0.5~5 ASD，正向與反向的電流密度比為1：1~1：10，正向與反向的時間比為2：1~50：1。
  3. 如請求項2的方法，其中該正向與反向的電流密度比為1：1~1：5，正向與反向的時間比為10：1~25：1。
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