WO2004079816A1 - 半導体装置の試験装置 - Google Patents
半導体装置の試験装置 Download PDFInfo
- Publication number
- WO2004079816A1 WO2004079816A1 PCT/JP2003/002445 JP0302445W WO2004079816A1 WO 2004079816 A1 WO2004079816 A1 WO 2004079816A1 JP 0302445 W JP0302445 W JP 0302445W WO 2004079816 A1 WO2004079816 A1 WO 2004079816A1
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- WIPO (PCT)
- Prior art keywords
- output
- signal
- test
- circuit
- latch
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C2029/2602—Concurrent test
Definitions
- the present invention relates to a test apparatus for a semiconductor device, and more particularly to a test apparatus for a semiconductor device for simultaneously testing a plurality of semiconductor devices.
- semiconductor devices are often designed and manufactured according to user's required specifications by means of ASIC or the like. Such semiconductor devices are often subjected to tests such as acceptance inspection on the design and manufacturing sides as well as on the delivery side.
- test device for simultaneously testing a plurality of semiconductor devices with one device (for example, see Patent Document 1).
- Such a test device for a semiconductor device is mainly used for designing and manufacturing of the semiconductor device for failure analysis, and is a device for analyzing which part is defective.
- Patent Document 1
- the present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device test apparatus capable of simultaneously testing semiconductor devices with a simple configuration.
- the present invention provides a semiconductor device test apparatus for simultaneously testing a plurality of semiconductor devices, as shown in FIG. 1, comprising a plurality of semiconductor devices under test (DUT) to which the same test signal is input. 1 2a to l 2d Within the latch period, the latch circuits 13 a to l 3 d to be switched and the expected values of the signals to be output by the plurality of semiconductor devices under test 12 a to l 2 d in response to the latched output signal and the test signal are latched.
- DUT semiconductor devices under test
- An output circuit that outputs the latched output signal in order, a comparison circuit that compares the latched output signal with the expected value, and an output signal and the expected value output from the output circuit when the output signal does not match the expected value.
- a test apparatus for a semiconductor device is provided. According to such a semiconductor device test apparatus, the latch circuits 13a to 13d output from a plurality of semiconductor devices under test 12a to 12d to which the same test signal is input.
- the latched output signal is latched by the output circuit, and the latched output signal and the expected value are sequentially output within the latch period, and the expected value and the output signal are compared by the comparison circuit. If the output signal does not match the expected value, the output signal and the expected value output from the output circuit are stored by the memory 18, and are stored in the memory 18 by the determination circuit 19. Since the quality of the semiconductor devices under test 12a to 12d is determined from the stored output signal and the expected value, the configuration is simplified.
- FIG. 1 is a circuit configuration diagram of a semiconductor device test apparatus according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a timing chart of the semiconductor device test apparatus of FIG.
- FIG. 3 is a circuit configuration diagram of a semiconductor device test apparatus according to a second embodiment of the present invention.
- FIG. 4 is a diagram showing details of the wafer and the jig wafer of FIG.
- FIG. 5 is a circuit configuration diagram of a semiconductor device test apparatus according to a third embodiment of the present invention.
- BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.
- FIG. 1 is a circuit configuration diagram of a semiconductor device test apparatus according to a first embodiment of the present invention.
- the test equipment for semiconductor devices consists of test signal input terminal 11a, expected value input terminal 11b, clock input terminal 11c, semiconductor device under test (DUT) 12a to l2d.
- PS parallel-serial
- a test signal t e st for performing a functional test of the DUTs 12 a to 12 d is input to the test signal input terminal 11 a.
- the function test is a test to input H-state and L-state signals to the DUTs 12a to 12d and to check whether the signals are output according to the functions of the DUTs 12a to 12d. It is.
- the test signal input terminal 11a is connected to the input of the DUT 12a to l2d, and the test signal t e st is output to the DUT 12a to l2d.
- the expected value signal e XP is input to the period input terminal 1 1 b.
- the expected value signal ep p is a signal that the DUTs 12 a to l 2 d should output in response to the input of the test signal t e st to the DUTs 12 a to l 2 d.
- the expected value signal ep p input to the expected value input terminal 11 b is output to the PS conversion circuit 15 and the encoder circuit 16.
- the clock CLK is input to the clock input terminal 11c.
- the clock CLK is a synchronizing signal of the test signal t e st and the expected value signal e x p.
- the clock CLK input to the clock input terminal 11 c is output to the latch circuits 13 a to 13 d and the doubling circuit 14.
- the DUTs 12a to 12d are semiconductor devices to be functionally tested.
- the DUTs 12a to 12d are packaged and inserted into, for example, a socket included in a test device of a semiconductor device, although not shown.
- the input terminal to which the test signal t e st of the DUTs 12 a to 12 d is input by the insertion into the socket is connected to the test signal input terminal 11 a.
- Output terminals for outputting output signals responsive to the test signals t e st of the DUTs 12 a to l 2 d are connected to the latch circuits 13 a to l 3 d.
- the latch circuits 13 a to l 3 d synchronize with the clock CLK, and the DUTs 12 a to l 2
- the output signal output from d is latched, and the latch signals D outl to D out 4 are output to the P-S conversion circuit 15 and the encoder circuit 16.
- the clock CLK is a synchronization signal of the test signal test as described above. Therefore, the latch circuits 13a to 13d latch the output signals output by the DUTs 12a to 12d during one state of the test signal test.
- the doubling circuit 14 multiplies the clock CLK and outputs a doubled clock mu 1 CLK.
- the doubling circuit 14 multiplies the clock C LK by adding 1 to the number of DUTs to be tested. In FIG. 1, the number of DUTs 12a to l2d is four. Therefore, the multiplication circuit 14 outputs a multiplied clock mu 1 CLK obtained by multiplying the clock CLK by 5 quadrants.
- the double clock mu 1 CLK is output to the P-S conversion circuit 15 and the address decoder 17.
- the P-S conversion circuit 15 receives the expected value signal epp and the latch signals Dout1 to Dout4 simultaneously in parallel.
- the P-S conversion circuit 15 outputs the expected value signal e X ⁇ and the latch signal Doutl to Doout 4 that are input in order from one output port in synchronization with the double clock mu 1 CLK.
- the doubling clock mu 1 CLK is a clock obtained by adding 1 to the number of DUTs to be tested, which is a doubling of the clock CLK.
- the P-S conversion circuit 15 converts the expected value signal exp and the latch signals Do utl to Do ut 4 during the period when the latch circuits 13 a to 13 d latch the output signal in synchronization with the clock CLK. Output in order.
- the P-S conversion circuit 15 outputs the expected value signal e XP and the latch signals Dout 1 to Dout 4 to the memory 18 as the conversion signal P-Sout.
- the encoder circuit 16 receives the expected value signal e X p input to the expected value input terminal 11 b and the latch signals D out 1 to D out 4 output from the latch circuits 13 a to l 3 d. .
- the encoder circuit 16 compares the expected value signal eXp with each of the latch signals Dout1 to Dout4. If any one of the latch signals Dout 1 to Dout 4 does not match the expected value signal e p, the encoder circuit 16 outputs a write signal / W indicating this to the memory 18.
- the encoder circuit 16 outputs an L-state signal when at least one of the latch signals D out 1 to D out 4 does not match the expected value signal e XP. Output signal / W.
- the address decoder 17 counts up the address of the memory 18 in synchronization with the double clock mu1CLK.
- the memory 18 has a write enable terminal .ZWE which receives a write signal / W from the encoder circuit 16.
- the PS conversion circuit 15 receives a write signal / W from the encoder circuit 16.
- the PS conversion circuit 15 receives a write signal / W from the encoder circuit 16 to the write enable terminal ZWE indicating that the latch signals Doutl to Dout4 did not match the expected value signal exp
- the PS conversion circuit 15 The converted signal P—S out output from the memory is stored. Since the address of the memory 18 is counted up by the address decoder 17 in synchronization with the multiplied clock mu 1 CLK, the expected value signal e X p and the latch signal D output sequentially from the P-S conversion circuit 15 are output. outl to Dout 4 (conversion signal P—S out) are stored one at a time. In the memory 18, the same value is stored as an initial value at all addresses.
- the decision circuit 19 compares the expected value signal e Xp stored in the memory 18 with the latch signals Do utl to Do ut 4 and determines that the latch signals D outl to Do ut 4 do not match the expected value signal exp.
- DUTs 12a to 12d corresponding to are judged to be defective.
- the same value is stored as an initial value at all addresses as described above.
- the memory 18 stores the expected value signal exp and the latch signal Do out 1 in the address that is restored by the address decoder 17.
- ⁇ D out 4 are stored one by one. Accordingly, the judgment circuit 19 compares the expected value signal e X p and the latch signals D out 1 to D out 4 with reference to the address, thereby determining which DUT 12 a to l 2 d is defective. Can be determined.
- FIG. 2 is a diagram showing a timing chart of the semiconductor device test apparatus of FIG. CLK shown in the figure indicates the clock CLK input to the clock input terminal 11c.
- mu l CLK indicates the multiplied clock mu 1 CLK multiplied by the multiplying circuit 14.
- the number shown in the double clock mu 1 CLK indicates the number of clocks of the double clock niu 1 CLK.
- the doubling circuit 14 multiplies the clock CLK by the number obtained by adding 1 to the number of DUTs 4 to be tested, so that the doubling clock mu 1 CLK is 5 doubling times of the clock CLK.
- e X p indicates the expected value signal e X p input to the expected value input terminal lib.
- D out 1 to D out 4 indicate latch signals D out 1 to D out 4 output from the latch circuits 13 a to 13 d.
- P-Sout indicates the converted signal P_Sout output from the P-S conversion circuit 15.
- / W indicates the write signal ZW output from the encoder circuit 16.
- test signal t e st input to the test signal input terminal 11 a is input to the DUTs 12 a to 12 d.
- the DUTs 12a to 12d output output signals in accordance with the input test signal t e st.
- the latch circuits 13 a to l 3 d latch output signals output from the DUTs 12 a to l 2 d for one cycle of the clock CLK, and latch signals D out 1 to D out Outputs 4.
- the latch signals Doutl to Doout4 output from the latch circuits 13a to 13d are output to the PS conversion circuit 15 and the encoder circuit 16.
- the P—S conversion circuit 15 and the encoder circuit 16 also receive the expected value signal e p input to the expected value input terminal l i b.
- the P-S conversion circuit 15 synchronizes the input expected value signal e X ⁇ and the latched signals D out 1 to D out 4 in synchronization with the quadrupled clock mu 1 CLK output from the quadruple circuit 14. Output.
- the PS conversion circuit 15 outputs the expected value signal e XP as the converted signal P-S out at the first clock of the multiplied clock mu l CLK.
- the PS conversion circuit 15 outputs the latch signal D out 1 as a conversion signal P—S out at the second clock of the double clock mu 1 CLK.
- the PS conversion circuit 15 outputs the latch signal Double 2 as the conversion signal P-S out at the third clock of the multiplied clock mu 1 CLK. ?
- the latch signal D out 3 is output as the converted signal P—S out at the fourth clock of the clock mu 1 CLK.
- the P-S conversion circuit 15 outputs the latch signal D out 4 as the conversion signal P-S out at the fifth clock of the multiplied clock mu 1 CLK.
- the P—S conversion circuit 15 synchronizes the multiplication clock mu 1 CLK with the expected value signal e XP and the latch signals D outl to Dout 4 in order, and converts the conversion signal P—S 0 ut Is output as
- the encoder circuit 16 compares the expected value signal XP with each of the latch signals Dout1 to Dout4.
- the encoder circuit 16 outputs the L-state write signal ZW to the memory 18 when at least one of the latch signals Dout 1 to Dout 4 does not match the expected value signal epp.
- the write signal ZW is in the H state since the expected value signal e XP and the latch signals D outl to Do out 4 match between 1 to 5 clocks of the double clock mu 1 CLK. . Since the expected value signal e XP and the latch signal D out 4 do not match between 6 and 10 clocks of the multiplied clock m u1 CLK, the write signal / W is in the L state.
- the write signal / W is in the L state. Since the expected value signal exp and the latch signals Doutl to Dout4 match between the 16 and 20 clocks of the double clock mu1CLK, the write signal is in the H state.
- Memory 18 receives a write signal ZW of L state from the encoder circuit 16, converted signal is output from the P- S conversion circuit 15 P- S out (expected value signal e chi [rho, the latch signal Do utl ⁇ Do ut 4)
- the memory 18 stores the expected value signal e XP and the latch signal D out1 to D out 4 only when the DUT 12 a to l 2 d outputs an output signal different from the expected value signal exp. Since the address of the memory 18 is counted up by the address decoder 17 in synchronization with the double clock mu 1 CLK, the expected value signal e Xp and the latch signals D outl to Dot 4 are stored in one address. It is memorized.
- the determination circuit 19 compares the expected value signal e XP stored in the memory 18 with the latch signals Do utl to Do ut 4, and determines whether the DUT 12a to: I 2 d is defective. Is determined. For example, in FIG. 2, the expected signal e Xp and the latch signal D out 4 do not match between 6 and 10 clocks of the double clock mu 1 CLK, so the expected signal e X p and the latch signal D out 4 do not match. outl to D out 4 are stored in the memory 18.
- the judgment circuit 19 compares the expected value signal e xp stored in the memory 18 with the latch signals D out1 to D out 4, and determines whether the DUT 12 d that has output the output signal corresponding to the latch signal D out 4 is invalid. Judge as good. Similarly, the determination circuit 19 outputs the output signal (latch signal Dout 3) different from the expected value signal exp between the 1-to: 15 clocks of the double clock mu l CLK. Determine c as defective.
- the output signals output from the DUTs 12 a to 12 d are latched by the latch circuits 13 a to 13 d, and the latch circuits 13 a to 13 d latch and output by the P-S conversion circuit 15.
- the latch signals D out1 to D out 4 and the expected value signal exp are sequentially output (conversion signal P—S out), and the encoder circuits 16 compare the latch signals D out 1 to D out 4 with the expected value signal exp.
- the conversion signal P—S out force S output from the -3 conversion circuit 15 by the memory 18 is output.
- the quality of the DUTs 12 a to 12 d is determined from the latch signals Dout 1 to Dout 4 and the expected value signal exp stored and stored in the memory 18 by the determination circuit 19. Therefore, multiple DUTs 12a to 12d can be tested simultaneously with a simple configuration.
- the cost of the semiconductor device test device is reduced, which leads to a reduction in the semiconductor device test cost.
- the latch signals Dout 1 to Dout 4 are 1-bit signals, but may be multi-bit signals.
- the PS conversion circuit 15 sequentially outputs the multi-bit latch signals Doutl to Dout4 in parallel one by one.
- the memory 18 stores a multi-bit latch signal Dout 1 to Dout 4 in one address one by one.
- FIG. 3 is a circuit configuration diagram of a test device for a semiconductor device according to a second embodiment of the present invention. Second embodiment Then, a defective semiconductor device formed on the wafer is determined. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
- FIG. 3 shows the wafer 21 and the jig wafer 22.
- a semiconductor device (DUT) to be tested is formed on the wafer 21, a semiconductor device (DUT) to be tested is formed.
- the jig wafer 22 has a terminal that comes into contact with an input terminal and an output terminal of the DUT by being superimposed on the wafer 21.
- the terminal that contacts the DUT input terminal of the jig wafer 22 is connected to the test signal input terminal 11a, and the terminal that contacts the DUT output terminal is connected to each of the latch circuits 13a to 13d.
- FIG. 4 is a diagram showing details of the wafer and the jig wafer of FIG.
- the DUTs 21 a to 21 d are formed in the wafer 21.
- the DUTs 21 a to 21 d have input terminals 21 aa, 21 b a, 21 c a, and 21 d a to which a test signal t e st is input.
- the DUTs 21 a to 21 d have output terminals 2 l ab, 21 b b, 21 c b and 21 db for outputting output signals in response to the test signal t e st.
- the jig ⁇ Aha 22 has test input terminals 22A ⁇ 22D that are superimposed on the ⁇ Aha 21 and come into contact with the input terminals 21Aa ⁇ 21Da of the DUTs 21A ⁇ 21D.
- the jig 22 has test output terminals 22 aa to 22 da that are in contact with the output terminals 2 lab to 21 db of the DUTs 21 a to 21 d by being superimposed on the evaporator 21.
- test input terminals 22a to 22d of the jig ⁇ Aha 22 are short-circuited with each. Therefore, for example, by connecting the probe connected to the test signal input terminal 11a in Fig. 3 to any of the test input terminals 22a to 21d, the test can be performed on all of the test input terminals 22a to 21d.
- the signal test is input.
- the output signals of the DUTs 21a to 21d can be output.
- the signals can be output to the latch circuits 13a to 13d.
- Output terminals of DUT21 a to 21 d The test pieces 21 ab to 21 db and the test output terminals 22 aa to 22 da of the fixture 22 are brought into contact with each other. Then, connect the test signal input terminal 11a to one of the test input terminals 22a to 22d of the jig ⁇ Aha 22 and input the test signal test, and connect the input of the latch circuit 13a to l3d.
- the test output terminals 22 aa to 22 daa of the fixture 22 were connected to output the output signals of the DUTs 21 a to 21 d to the latch circuits 13 a to 13 d.
- the test signal test can be easily input to the DUTs 21 a to 21 d formed on the wafer 21, and the output signals output from the DUTs 21 a to 21 d are latched by the latch circuit 13. It can output to a to l 3 d. Further, damage to the wafer 21 can be prevented.
- the probe is connected to the jig A22 and the jig A22 is connected to the test signal input terminal 11a and the latch circuits 13a to 13d.
- the fixture 22, the wafer 22, the test signal input terminal 11a, and the latch circuits 13a to 13d may be connected and fixed by a lead wire.
- FIG. 5 is a circuit configuration diagram of a semiconductor device test apparatus according to the third embodiment of the present invention.
- the same test signal t e st as that of the semiconductor device under test is input to a semiconductor device that has been previously determined as a non-defective product. Then, the output signal output from the non-defective semiconductor device is used as the expected value signal eXp.
- the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
- the semiconductor device test apparatus shown in FIG. 5 includes a latch circuit 32 for latching SMPDUT 31 and SMPDUT 31 that are determined to be non-defective, instead of the expected value input terminal 11 b in FIG. Have.
- the input of the SMPDUT 31 is connected to the test signal input terminal 11a, and the same test signal t e st as the DUT 12a to l2d is input. Since SMPDUT 31 is a good semiconductor device, the output signal output by SMPDUT 31 is the expected value of the signal that DUT 12 a to l 2 d should output in response to test signal t e st.
- the latch circuit 32 latches the output signal output from the SMPDUT 31 in synchronization with the clock CLK input to the clock input terminal 11c.
- the signal output from the latch circuit 32 is a P-S conversion circuit 15 as an expected value signal exp. Output to coder circuit 16.
- the P-S conversion circuit 15 sequentially transmits the expected value signal e Xp output from the latch circuit 32 and the latch signals D out 1 to D out 4 to the memory 18. Output.
- the encoder circuit 16 compares the expected value signal e Xp output from the latch circuit 32 with each of the latch signals D out 1 to D out 4 in the same manner as described with reference to FIG. The result is output to memory 18.
- the test signal test is input to the SMPDUT 31 that has been determined as a non-defective product, and the output signal output from the SMPDUT 31 is changed to the expected value signal e Xp. According to this, DUT12a to l2d can be simultaneously tested with a simple configuration.
- the latch circuit latches the output signals output from the plurality of test semiconductor devices to which the same test signal has been input, and the output circuit latches the output signal and the expected
- the values are sequentially output within the latch period, and the expected value and the output signal are compared by the comparison circuit. If the output signal does not match the expected value, the memory stores the output signal output from the output circuit and the expected value, and the determination circuit detects the output signal and the expected value from the memory. The quality of the test semiconductor device is determined. Therefore, a plurality of semiconductor devices can be tested simultaneously with a simple configuration.
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- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/002445 WO2004079816A1 (ja) | 2003-03-03 | 2003-03-03 | 半導体装置の試験装置 |
CNB038218682A CN100345269C (zh) | 2003-03-03 | 2003-03-03 | 半导体器件测试装置 |
JP2004569073A JP4111955B2 (ja) | 2003-03-03 | 2003-03-03 | 半導体装置の試験装置 |
US11/072,237 US7526690B2 (en) | 2003-03-03 | 2005-03-07 | Semiconductor device-testing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/002445 WO2004079816A1 (ja) | 2003-03-03 | 2003-03-03 | 半導体装置の試験装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/072,237 Continuation US7526690B2 (en) | 2003-03-03 | 2005-03-07 | Semiconductor device-testing apparatus |
Publications (1)
Publication Number | Publication Date |
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WO2004079816A1 true WO2004079816A1 (ja) | 2004-09-16 |
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Family Applications (1)
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PCT/JP2003/002445 WO2004079816A1 (ja) | 2003-03-03 | 2003-03-03 | 半導体装置の試験装置 |
Country Status (4)
Country | Link |
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US (1) | US7526690B2 (ja) |
JP (1) | JP4111955B2 (ja) |
CN (1) | CN100345269C (ja) |
WO (1) | WO2004079816A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100512175B1 (ko) * | 2003-03-17 | 2005-09-02 | 삼성전자주식회사 | 출력 신호들을 선택적으로 출력가능한 반도체 집적 회로및 그것의 테스트 방법 |
US7913002B2 (en) * | 2004-08-20 | 2011-03-22 | Advantest Corporation | Test apparatus, configuration method, and device interface |
DE112014006642T5 (de) * | 2014-07-28 | 2017-01-19 | Intel Corporation | Halbleitervorrichtungs-Prüfgerät mit Dut-Daten-Streaming |
CN106205735A (zh) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | 嵌入式芯片测试方法及系统 |
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JPH04236440A (ja) * | 1991-01-21 | 1992-08-25 | Fujitsu Ltd | 半導体試験装置 |
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JP2000163989A (ja) * | 1998-11-30 | 2000-06-16 | Advantest Corp | Ic試験装置 |
JP2000314762A (ja) * | 1999-04-30 | 2000-11-14 | Asahi Kasei Microsystems Kk | 半導体試験装置 |
JP2001236797A (ja) * | 1999-12-17 | 2001-08-31 | Fujitsu Ltd | 自己試験回路及びそれを内蔵するメモリデバイス |
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JPH0778499A (ja) * | 1993-09-10 | 1995-03-20 | Advantest Corp | フラッシュメモリ試験装置 |
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US5621312A (en) * | 1995-07-05 | 1997-04-15 | Altera Corporation | Method and apparatus for checking the integrity of a device tester-handler setup |
JPH0963300A (ja) * | 1995-08-22 | 1997-03-07 | Advantest Corp | 半導体メモリ試験装置のフェイル解析装置 |
JPH1164454A (ja) | 1997-08-18 | 1999-03-05 | Advantest Corp | 半導体試験装置用同時測定制御回路 |
JP4251707B2 (ja) * | 1999-04-02 | 2009-04-08 | 株式会社アドバンテスト | 半導体デバイス試験装置及び試験方法 |
DE10112560B4 (de) * | 2001-03-15 | 2011-02-17 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Prüfen von Schaltungsmodulen |
US6961880B2 (en) * | 2001-07-30 | 2005-11-01 | Infineon Technologies Ag | Recording test information to identify memory cell errors |
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2003
- 2003-03-03 JP JP2004569073A patent/JP4111955B2/ja not_active Expired - Fee Related
- 2003-03-03 CN CNB038218682A patent/CN100345269C/zh not_active Expired - Fee Related
- 2003-03-03 WO PCT/JP2003/002445 patent/WO2004079816A1/ja active Application Filing
-
2005
- 2005-03-07 US US11/072,237 patent/US7526690B2/en not_active Expired - Fee Related
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JPH04236440A (ja) * | 1991-01-21 | 1992-08-25 | Fujitsu Ltd | 半導体試験装置 |
JPH04285875A (ja) * | 1991-03-14 | 1992-10-09 | Fujitsu Ltd | ディジタル電子回路モジュールの試験装置 |
JP2000163989A (ja) * | 1998-11-30 | 2000-06-16 | Advantest Corp | Ic試験装置 |
JP2000314762A (ja) * | 1999-04-30 | 2000-11-14 | Asahi Kasei Microsystems Kk | 半導体試験装置 |
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Also Published As
Publication number | Publication date |
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CN1682364A (zh) | 2005-10-12 |
JPWO2004079816A1 (ja) | 2006-06-08 |
JP4111955B2 (ja) | 2008-07-02 |
US20050166113A1 (en) | 2005-07-28 |
US7526690B2 (en) | 2009-04-28 |
CN100345269C (zh) | 2007-10-24 |
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