WO2003098684A1 - Dispositif de traitement de substrats et procede de traitement de substrat - Google Patents

Dispositif de traitement de substrats et procede de traitement de substrat Download PDF

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Publication number
WO2003098684A1
WO2003098684A1 PCT/JP2003/005597 JP0305597W WO03098684A1 WO 2003098684 A1 WO2003098684 A1 WO 2003098684A1 JP 0305597 W JP0305597 W JP 0305597W WO 03098684 A1 WO03098684 A1 WO 03098684A1
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WO
WIPO (PCT)
Prior art keywords
substrate
processing
processed
processing units
units
Prior art date
Application number
PCT/JP2003/005597
Other languages
English (en)
Japanese (ja)
Inventor
Masahiro Numakura
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to KR1020047018263A priority Critical patent/KR100949013B1/ko
Publication of WO2003098684A1 publication Critical patent/WO2003098684A1/fr
Priority to US10/987,035 priority patent/US20050129839A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67276—Production flow monitoring, e.g. for increasing throughput
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41865—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/32—Operator till task planning
    • G05B2219/32315—Machine with least work
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/45—Nc applications
    • G05B2219/45031—Manufacturing semiconductor wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the present invention relates to a substrate processing apparatus and a substrate processing method for performing processing such as film formation and etching on a substrate to be processed such as a semiconductor wafer or a glass substrate for a liquid crystal display device.
  • a substrate processing apparatus which performs processing such as deposition or etching on a substrate to be processed such as a semiconductor wafer or a glass substrate for a liquid crystal display, a plurality of processing units and a transfer mechanism connected to these processing units And the transport mechanism sequentially transports the substrate to a plurality of processing units, and each processing unit is configured to perform the same processing or different processing, effectively using resources, space, etc.
  • a substrate processing apparatus capable of efficiently processing a substrate to be processed.
  • a substrate processing apparatus provided with two processing units, a first processing unit and a second processing unit, for example, the same processing is performed in the first and second processing units.
  • the first semiconductor wafer is carried into the first processing unit, and the first processing is performed.
  • the second semiconductor wafer is loaded into the second processing unit while the first semiconductor wafer processing is being performed in the second processing unit, and the second semiconductor wafer processing is performed in the second processing unit.
  • the cassette containing the semiconductor wafer of the lot to be processed next is carried in, and When processing of the semiconductor wafer in the cassette is started, transfer of the semiconductor wafer is started from the first processing unit. Therefore, for example, when processing 25 semiconductor wafers in a cassette, the first processing unit processes 13 semiconductor wafers, and the second processing unit processes 12 2 wafers. Processing of the semiconductor wafer is performed, and the frequency of use in the first processing unit and the second processing unit is uneven, and a difference may occur in the maintenance cycle and the degree of wear of parts in the processing unit. There was sex. Disclosure of the invention
  • an object of the present invention is to provide a substrate processing apparatus and substrate processing that can equalize the usage frequency of each processing unit, and can suppress the occurrence of differences in the maintenance cycle and the degree of wear of components in the processing unit. It is an attempt to provide a method.
  • a substrate processing apparatus comprises: a plurality of processing units for performing predetermined processing on a substrate to be processed; a transport mechanism for transporting the substrate to be processed in a predetermined sequence to the plurality of processing units; Among the processing units, the processing unit where the processing of the substrate to be processed is lastly stored is stored, and when the processing is started next, the processing substrate from the processing unit in the next order of the stored processing unit is And control means for controlling the transfer mechanism to start the transfer.
  • a plurality of processing units for performing predetermined processing on a substrate to be processed, a transport mechanism for transporting the substrate to be processed to the plurality of processing units, and a plurality of processing units Store the integration processing time respectively, then open the processing Control means is provided to control the transport mechanism to start transport of the substrate from the processing unit with the smallest accumulated processing time stored, when the processing starts.
  • the control means controls the transport mechanism so as to transport the substrate to be processed in the order of the processing units having the smaller integration processing time stored.
  • a substrate processing apparatus includes a plurality of processing units for performing predetermined processing on a substrate to be processed, a transfer mechanism for transferring the substrate to be processed to the plurality of processing units, and a plurality of the processing units.
  • Control means for controlling the transport mechanism so as to start transport of the substrate to be processed from the processing unit with the smallest accumulated processing number stored when storing the integrated processing number of each and starting processing next time; It is characterized in that
  • the control means controls the transport mechanism so as to transport the substrate to be processed in the order of the stored processing units having the smaller integrated processing number. It is characterized by Further, in the substrate processing apparatus of the present invention, in the above-described substrate processing apparatus, the control unit can receive the substrate to be processed even after a predetermined time has passed, which is to transport the substrate to be processed. If this is not the case, control is performed such that the substrate to be processed is transported to the processing unit having the highest priority among the processing units capable of receiving the substrate to be processed.
  • the processing units each have a load lock chamber, and the transport mechanism is configured to transport the substrate to be processed to the load lock chamber. c also characterized in that there, the substrate processing apparatus of the present invention, in the above substrate processing apparatus, the processing unit of the multiple is characterized by applying the same process.
  • the substrate processing method of the present invention comprises a plurality of processing substrates for performing predetermined processing on a substrate to be processed.
  • a substrate processing method using a substrate processing apparatus comprising: a processing unit; and a transport mechanism for transporting the substrate to be processed to the plurality of processing units in a predetermined order
  • the processing unit in which the processing of the substrate to be processed is performed is stored, and when the processing is started next, the transfer of the substrate to be processed is started from the processing unit in the order following the stored processing unit.
  • the substrate processing method according to the present invention further comprises: a plurality of processing units for performing predetermined processing on the substrate to be processed; and a transport mechanism for transporting the substrate to be processed in a predetermined order to the plurality of processing units.
  • the integration processing time of each of the plurality of processing units is stored, and when the processing is started next, the processing unit with the smallest integration processing time stored is used. It is characterized in that the transfer of the substrate to be processed is started.
  • the substrate processing method of the present invention is characterized in that, in the above-mentioned substrate processing method, the substrate to be processed is transported in the order of the processing units with the shorter integration processing time which are stored.
  • the substrate processing method further comprises: a plurality of processing units for performing predetermined processing on the substrate to be processed; and a transport mechanism for transporting the substrate to be processed in a predetermined order to the plurality of processing units.
  • the integration processing time of each of the plurality of processing units is stored, and when the processing is started next, the processing unit with the smallest integration processing time stored is used. It is characterized in that the transfer of the substrate to be processed is started.
  • the substrate processing method of the present invention is characterized in that, in the above-mentioned substrate processing method, the substrate to be processed is transported in the order of the processing units with the shorter integration processing time which are stored.
  • the processing unit for transferring the substrate to be processed when the processing unit for transferring the substrate to be processed can not receive the substrate to be processed even after a predetermined time has elapsed.
  • Accept substrate to be processed It is characterized in that the substrate to be processed is transported to the processing unit having the highest priority among the possible processing units.
  • the processing units each have a load lock chamber, and the transport mechanism transports the substrate to be processed to the load lock chamber.
  • the substrate processing method of the present invention is characterized in that, in the above substrate processing method, the plurality of processing units perform the same processing.
  • FIG. 1 is a surface schematically showing a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention.
  • FIG. 2 is a flow chart illustrating the operation of one embodiment of the present invention.
  • FIG. 3 is a view schematically showing a schematic configuration of a substrate processing apparatus according to another embodiment of the present invention.
  • FIG. 4 is a flow chart showing the operation of another embodiment of the present invention.
  • FIG. 5 is a flowchart showing the operation of another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 schematically shows a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention.
  • the substrate processing apparatus comprises a plurality of (two in the apparatus of FIG. 1) process ships PS 1 and PS 2 constituting a processing unit for performing predetermined processing on a semiconductor wafer W, and a semiconductor wafer It is configured by combining a loader module LM that constitutes a transport mechanism that transports W.
  • Loader module LM performs positioning of a plurality of (three in the apparatus of FIG. 1) load ports LP 1 to LP 3 accommodating semiconductor wafer W, a transfer chamber TR for transferring semiconductor wafer W, and semiconductor wafer W. It consists of Orienta OR and.
  • the transfer room TR is connected to the orienta OR, and the process ships PS 1 and PS 2 are connected via the load lock doors LG 1 and LG 2, and further via the load port doors CG 1 to CG 3 Load ports LP1 to LP3 are connected.
  • the load ports LP 1 to LP 3 are force sets or hoops (FOUP) CS 1 to CS 3 (in the following, the case of cassettes) which accommodates the unprocessed semiconductor wafer W and the processed semiconductor wafer W. ) Will be installed.
  • loader arms L A 1 and LA 2 of a two-stage configuration are provided.
  • the loader arm LA 1, LA 2 is a semiconductor wafer W between the load port LP 1 to LP 3 and the process ship PS 1, PS 2 (load lock chamber LL 1, LL 2) or between the orienter OR Transport (the transport of 126 in Figure 1).
  • the loader arms LA 1 and LA 2 are configured in two stages, and while the semiconductor wafer W is carried in by one loader arm LA 1 and LA 2, the other loader arms LA 2 and LA I are used.
  • the semiconductor wafer W can be unloaded, and the semiconductor wafer W can be replaced efficiently.
  • load lock chambers L L 1 and L L 2 and process chambers PM 1 and PM 2 are provided in the process ship PS 1 and PS 2.
  • the load lock chambers L L l and L L 2 and the process chambers PM 1 and PM 2 are connected to each other through process gates P G 1 and P G 2.
  • wafer holder B 1 1, B 1 2, B 2 1 and B 2 2 and load lock arm LR 1 and LR 2 are installed respectively. It is broken.
  • the semiconductor wafer W carried in from the loader module LM is placed on the wafer mounting table B11, B21, and the semiconductor wafer W unloaded from the load lock chamber LL1, LL2 is placed on it. .
  • the semiconductor wafer W carried into the process chambers PM 1 and PM 2 is placed on the wafer mounting tables B 12 and B 22. Further, the load lock arms LR 1 and LR 2 transfer the semiconductor wafer W between the load lock chambers LL 1 and LL 2 and the process chamber PM 1.
  • PM 2 (transfer of 345 in FIG. 1) (here)
  • the transport chamber TR is open to the atmosphere, and the load port doors CG 1 to CG 3 are kept open ( to prevent contamination, in order to increase the efficiency of transport).
  • the process chamber PM 1 and PM 2 are maintained at a predetermined vacuum level, so that the load lock chamber LL 1 and LL 2 can be transported to and from the transfer chamber TR or the process chamber PM 1 and PM 2 and Depending on the conveyance between the stations, air supply / exhaust will be performed to correspond to each degree of vacuum.
  • the entire substrate processing apparatus is generally controlled by the controller MC, and the transport sequence is also controlled by the controller MC.
  • the loader arms LA 1 and LA 2 take out the semiconductor wafer W from the cassette C S 1 placed on the load port L P 1 and carry it into the orienter OR (1).
  • the orienter OR positions the semiconductor wafer W.
  • the loader arms LA 1 and LA 2 take out the semiconductor wafer W from the orienter OR.
  • the load lock door LG 1 of the load lock chamber LL 1 is opened.
  • Road lock door LG When 1 is opened, the loader arm LA I, LA 2 carries the semiconductor wafer W into the load lock chamber LL 1 and places it on the wafer mounting table B 11 (2).
  • the load lock door L G 1 When the semiconductor wafer W is placed on the wafer mounting table B 11, the load lock door L G 1 is closed. Then, the inside of the load lock chamber L L 1 is evacuated, and the load lock arm L R 1 transports the semiconductor wafer W on the wafer mounting table B 11 to the wafer mounting table B 12 (3).
  • the process gate PG 1 of the process chamber PM 1 is opened, and the load lock arm LR 1 is The semiconductor wafer W on the wafer mounting table B 12 is loaded into the process chamber PM 1 (4).
  • the process gate PG 1 is closed, and the semiconductor wafer W is processed in the process chamber PM 1.
  • the process gate PG 1 is closed, and the atmosphere in the load lock chamber LL 1 is opened.
  • the load lock door LG 1 is opened according to the loading timing of the next semiconductor wafer W, and one of the loader arms LA 1 and LA 2 is placed on the wafer mounting table B 1 1 1
  • the upper semiconductor wafer W is carried out to the load port LP 1 (6), and the other loader arm LA 1 or LA 2 carries the next semiconductor wafer W positioned by the orienter OR into the load lock chamber LL 1 Do it (2).
  • the recipe (execution recipe) executed in process chamber PM 1 and PM 2 is not the timing at which semiconductor wafer W is loaded into load lock chamber LL 1 and LL 2 force, etc., and process chamber PM 1 and PM 2. It is loaded at the timing when it is carried into the load lock chamber LL 1 and LL 2 from the loader module LM.
  • pretreatment for the next semiconductor wafer W for example, temperature setting, self-diagnosis of flow rate of FCS (Flow Control System), etc.
  • Process gate (PG 1, PG 2) between process chamber PM 1, PM 2 and load lock chamber LL 1, LL 2 can be processed without any problem), and the throughput can be improved. It becomes possible.
  • the substrate processing apparatus having the above configuration, for example, when a new port (one or more cassettes containing a semiconductor wafer W to be processed next) has been transferred to the load ports LP1 to LP3. From this cassette, specify one of the process chambers PM 1 and PM 2 (process ship PS 1 and PS 2), for example, only the specified process chamber PM 1 (process ship PS 1)
  • the wafer w can be transferred and processed while the semiconductor wafer W is transferred to the two process chambers PM 1 and PM 2 (process ships PS 1 and PS 2) in sequence, and these two process chambers PM can be selected. 1, It is possible to select the mode (OR (or) transfer mode) that enables processing in a short time using PM 2 (Process Ship PS 1 and PS 2).
  • the substrate processing apparatus is in the idle mode (101) shown in Fig. 2 and is in the standby state.
  • controller MC recognizes that the next new lot (cassette) has been loaded to load port LP 1 to LP 3 (1002), the entire device is idled first. Start the sequence to restore from normal state to normal state (1 0 3).
  • control device MC determines whether the next lot is in the OR transfer mode (104), and if it is in the OR transfer mode, the next process room PM (process ship PS) starts from the semiconductor Start loading of wafer W (10 5).
  • the process room PM (final process PM) in which the last process was performed is stored in the previous lot (107), and the process of this lot is started.
  • the loading of the semiconductor wafer W is started from the process room next to the final process PM (for example, the process room PM 2 when the final process PM is the process room PM 1).
  • the semiconductor wafers are sequentially carried into (out of) two process chambers PM 1 and PM 2 (process ships PS 1 and PS 2) for processing, and all the semiconductor wafers in one lot carried in are processed.
  • the process chamber PM final process PM that has been processed last is stored (1007), and the process ends.
  • the semiconductor wafer W is loaded and processed only in the designated process chamber PM (process ship PS) (108), All semiconductor wafers in a closed mouth
  • the process chamber PM final process PM in which the process was last performed this time is stored (10 7), and the process is ended.
  • the control apparatus MC when the control apparatus MC stores the process chamber PM (final process PM) processed last, and the next lot is in the OR conveyance mode, the next process room (for example, the next process room) If the final process PM is the process chamber PM 1, start the loading of the semiconductor wafer W from the process chamber PM 2).
  • the frequency of use of the two process chambers PM 1 and PM 2 (process ship PS 1 and PS 2) can be equalized, and differences in the degree of wear of parts in the maintenance cycle can be suppressed. .
  • the OR transfer mode when the OR transfer mode is selected, if transfer is always started from the process chamber PM 1 (process ship PS 1), if 25 semiconductor wafers W are processed, the process chamber PM 1 is processed. Processing of 1 2 semiconductor wafers W is performed in 1 (process ship PS 1) and 1 2 in process chamber PM 2 (process ship PS 2), and one lot (cassette) is used one at a time Can make a difference. Therefore, assuming that a maintenance cycle is performed every 150 0 (1 1 5 lots) of semiconductor wafers W, when the maintenance cycle is reached, process chamber PM 1 (process ship PS 1) and process chamber PM are processed.
  • the difference in frequency of use with 2 is 115 wafers in terms of the number of processed wafers W and the average process time is 3.5 minutes, the difference in the total use time is about 6.7 hours. Will occur.
  • the difference in the frequency of use is within one with the difference between the number of semiconductor wafers and the number of processed wafers, and the difference between the cumulative use times is one process time. It can be done within a minute.
  • the maintenance cycle of each process ship PS 1 and PS 2 and the degree of wear of parts differ. Can be prevented, and equipment can be used in good condition by performing similar maintenance on each process ship PS 1 and PS 2 at the same time.
  • the final processing PM (final processing process room)
  • the process room PM2 process ship PS 2
  • the loading of the semiconductor wafer W is started from the process room PM 3 (process ship PS 3), and the process room PM 3 ⁇ Load semiconductor wafer W in the order of process chamber PM 1 ⁇ process chamber PM 2.
  • the process room has been processed with (N – 1) pieces of semiconductor wafer W (where N is the number of process rooms to be OR transported) immediately before becoming idle.
  • N is the number of process rooms to be OR transported
  • the process room it is possible to decide the process room to carry out the next process. For example, in the case where there are three process chambers, if the process chamber in which the two semiconductor wafers W immediately before becoming idle are processed is PM 3 ⁇ PM 1 ⁇ (idle), the next process is to be performed.
  • the mouth set will be PM 2.
  • the difference in the frequency of use can be made within 1 wafer within the difference in the number of processed wafers W-within 1 minute of the processing time within 3 hours as the difference in the cumulative operating time.
  • the time to return from the idle state to the normal state may differ depending on the process ship PS depending on the state of the process ship PS.
  • loading of the semiconductor wafer W is started from the process chamber PM 2 (process ship PS 2), and the process chamber PM 2 (process ship PS 2) is started. If it takes a long time to allow the semiconductor wafer W to receive the semiconductor wafer W, the semiconductor wafer W can not be started to be carried in, and the throughput may be lowered.
  • process chamber PM 2 process ship PS 2
  • process chamber PM 1 process ship PS 1
  • process chamber PM 3 The process ship PS 3
  • the semiconductor wafer W when loading of the semiconductor wafer W is started, a timeout is set, and the semiconductor wafer W can be received if it can not be transported to the process chamber within the time set for the timeout.
  • the semiconductor wafer W may be transferred from the highest priority process chamber among the other process chambers.
  • next process room is determined to be PM 1 but can not be transported to PM 1 within the timeout setting time
  • next highest priority ie, next to PM 1
  • the next process room is PM 2 in the order of.
  • the process chamber having the highest priority next to the next process chamber that is, the integration processing time and the number of integration processing sheets are small. By starting transportation as the next process chamber, it is possible to suppress the decrease in throughput.
  • the setting time of this timeout is preferably configured to be able to be changed as appropriate.
  • the final process PM determines the process chamber PM to start loading of a new lot of semiconductor wafers W. For example, as shown in FIG. As shown, the accumulated processing time of each process room PM is stored and updated one by one (2 0 7), and loading is started from the process room PM (process ship PS) with the smallest accumulated processing time. (2 05), as shown in Fig. 5, store the cumulative processing number of each process chamber PM and update it one by one (3 0 7), and process chamber PM with the smallest number of cumulative processing number It is also possible to configure to start (305) loading from (Process Ship PS).
  • the loading order of the entire semiconductor wafer W may be in the order of smaller integration processing time and integration processing number.
  • the semiconductor wafer W is processed as follows: process chamber PM 2 ⁇ process chamber PM 1 ⁇ process It will be delivered in the order of room PM 3, and so on.
  • the method of carrying is carried out with the load port gates CG 1 to CG 3 opened, but if there is time before carrying, the gate ports CG 1 to CG 3 are used. It may be closed temporarily.
  • the transfer chamber TR is described as being open to the atmosphere, but the transfer chamber TR may be evacuated. Also, the case where two wafer mounting tables B11, B12, B21 and B22 are provided in each load lock chamber LL1 and LL2 has been described. One table may be provided, or the load lock arms LR 1 and LR 2 may be used also as a wafer table.
  • loader arm LA1 and LA2 demonstrated to an example the case where semiconductor wafer mounting base B11 and B21 on the near side were accessible, semiconductor wafer mounting base B12 and B2 2 in the back are demonstrated. You may access it directly.
  • the loader arms LA1 and LA2 may be one-stage described in the case of the two-stage configuration.
  • the frequency of use of each processing unit can be equalized, and differences in the degree of consumption of parts in the maintenance cycle or processing unit may occur. It can be suppressed.
  • the substrate processing apparatus and the substrate processing method according to the present invention can be used in, for example, the semiconductor manufacturing industry which manufactures semiconductor devices. Therefore, it has industrial applicability

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Dans un contrôleur MC, les informations relatives à une chambre de traitement (PM) (chambre de traitement du dernier traitement) qui a effectué le dernier traitement sur le lot précédent sont mémorisées. Lorsqu'on démarre le traitement du lot en cours, les plaquettes de semi-conducteur W sont chargées dans les chambres de traitement, en commençant par la chambre de traitement qui suit la chambre de traitement du dernier traitement (par exemple la chambre de traitement (PM2), lorsque la chambre de traitement du dernier traitement est la chambre (PM1)). On peut ainsi utiliser les processeurs de façon uniforme et minimiser les variations des cycles de maintenance et les variations d'usure des pièces dans les processeurs.
PCT/JP2003/005597 2002-05-15 2003-05-02 Dispositif de traitement de substrats et procede de traitement de substrat WO2003098684A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020047018263A KR100949013B1 (ko) 2002-05-15 2003-05-02 기판 처리 장치 및 기판 처리 방법
US10/987,035 US20050129839A1 (en) 2002-05-15 2004-11-15 Substrate processing apparatus and substrate processing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002139775A JP4334817B2 (ja) 2002-05-15 2002-05-15 基板処理装置及び基板処理方法
JP2002-139775 2002-05-15

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JP (1) JP4334817B2 (fr)
KR (1) KR100949013B1 (fr)
CN (1) CN1321448C (fr)
TW (1) TWI270956B (fr)
WO (1) WO2003098684A1 (fr)

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US8408158B2 (en) * 2005-03-11 2013-04-02 Tokyo Electron Limited Coating/developing device and method

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JP4796574B2 (ja) * 2006-02-07 2011-10-19 東京エレクトロン株式会社 基板処理装置の制御装置および基板処理装置の制御プログラム
JP5091413B2 (ja) * 2006-03-08 2012-12-05 東京エレクトロン株式会社 基板処理装置および基板処理装置の制御方法
JP5128080B2 (ja) * 2006-03-29 2013-01-23 東京エレクトロン株式会社 基板処理装置の制御装置およびその制御方法
JP2008135517A (ja) * 2006-11-28 2008-06-12 Tokyo Electron Ltd 基板処理装置の制御装置、制御方法および制御プログラムを記憶した記憶媒体
JP2008311365A (ja) * 2007-06-13 2008-12-25 Hitachi Kokusai Electric Inc 基板処理装置
JP5115727B2 (ja) * 2008-06-11 2013-01-09 Ｎｅｃアクセステクニカ株式会社 検査システム、検査方法および検査結果情報格納装置ならびに制御端末
JP5571122B2 (ja) * 2012-06-06 2014-08-13 東京エレクトロン株式会社 基板処理装置および基板処理装置の制御方法
JP6045946B2 (ja) * 2012-07-13 2016-12-14 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置、プログラムおよび記録媒体
US9947566B2 (en) 2014-03-25 2018-04-17 Kawasaki Jukogyo Kabushiki Kaisha Substrate angle alignment device, substrate angle alignment method, and substrate transfer method
JP6089082B1 (ja) 2015-09-29 2017-03-01 株式会社日立国際電気 基板処理装置、半導体装置の製造方法、プログラムおよび記録媒体
JP6704008B2 (ja) * 2018-03-26 2020-06-03 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 基板処理装置、半導体装置の製造方法および記録媒体
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JP6719523B2 (ja) 2018-09-18 2020-07-08 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 基板処理装置、半導体装置の製造方法および記録媒体

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TW200400584A (en) 2004-01-01
KR20040104734A (ko) 2004-12-10

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