1270956 ⑴ 玖、發明說明 【發明所屬之技術領域】 本發明是關於一種在半導體晶圓或液晶顯示裝置用的 玻璃基板等的被處理基板施以成膜或蝕刻等處理的基板處 理裝置及基板處理方法。 【先前技術】 習知，在半導體晶圓或液晶顯示裝置用的玻璃基板等 的被處理基板施以成膜或蝕刻等處理的基板處理裝置具備 :複數處理部，及被連接於此等處理部的搬運機構；藉由 搬運機構將被處理基板依次搬運至複數處理部，構成在各 處理部能施以同一處理或不相同的處理，眾知有可有效利 用資源、空間等，且有效率地進行被處理基板的處理的基 板處理裝置。 在此種習知的基板處理裝置，例如在具備第〗處理部 與第2處理部的基板處理裝置，藉由連續進行例如在第玉 及第2的處理部進行同一處理，而依次處理被收容在一個 晶盒的25枚半導體晶圓的場合，首先，在第i處理部搬 入第一枚的半導體晶圓，而在該第1處理部進行第一枚的 半導體晶圓，而在該第i處理部進行第一枚的半導體晶圓 的處理之期間，在第2處理部搬入第二枚的半導體晶圓， 在第2處理部進行第二枚的半導體晶_的處理之期間從第 1處理部搬出第一枚的半導體晶圓而搬入第三枚的半導體 晶圓的動作，能在短時間內有效率地進行25枚半導體晶 -4- (2) 1270956 圓的處理。 然而，在上述構成的習知的基板處理裝置，當終了一批 的處理，一旦中止處理之後，搬入收容進行下一處理的一批 的半導體晶圓的晶盒，而開始該晶盒內的半導體晶圓的處理 的場合，成爲開始從第1處理部搬運半導體晶圓。所以， 例如進行晶盒內的25枚的半導體晶圓的處理的場合，成爲 在第1處理部進行1 3枚半導體晶圓的處理，而在第2處理 部進行1 2枚的半導體晶圓的處理。在第1處理部與第2處 理部上在使用頻度會產生偏差，而在主維持週期，或在處 理內的構件的消耗度上發生相差的可能性。 【發明內容】 本發明之目的是在於提供一種可將各處理部的使用頻 度成爲均勻化，而可抑制在維修週期或處理部內的零件的 消耗度發生差異的基板處理裝置及基板處理方法。 本發明的基板處理裝置，其特徵爲具備：在被處理基板 施以所定處理所需的複數處理部；以所定順序將上述被處 理基板搬運至複數上述處理部的搬運機構；及記憶複數上 述處理部中最後進行上述被處理基板的處理的處理部，之 後開始處理之際，控制上述搬運機構成爲從上述被記憶的 處理部的下一順序的處理部開始上述被處理基板的搬運的 控制手段。 又，本發明的基板處理裝置，其特徵爲具備：在被處理 基板施以所定處理所需的複數處理部；將上述被處理基板 -5- (3) 1270956 搬運至複數上述處理部的搬運機構；及分別記憶複數上述. 處理部的累計處理時間，之後開始處理之際，控制上述搬 運機構成爲從上述被記憶的累計處理時間的最少處理部開 始上述被處理基板的搬運的控制手段。 又，本發明的基板處理裝置，是在上述基板處理裝置中 ，上述控制手段控制上述搬運機構成爲依上述被記憶的累計 處理時間的較少處理部的順序，進行上述被處理基板的搬 運，爲其特徵者。 又，本發明的基板處理裝置，其特徵爲具備：在被處理 基板施以所定處理所需的複數處理部；將上述被處理基板 搬運至複數上述處理部的搬運機構；及分別記憶複數上述 處理部的累計處理時間，之後開始處理之際，控制上述搬 運機構成爲從上述被記憶的累計處理時間的最少處理部開 始上述被處理基板的搬運的控制手段。 又’本發明的基板處理裝置，是在上述基板處理裝置中 ’上述控制手段控制上述搬運機構成爲依上述被記憶的累計 處理枚數的較少處理部的順序，進行上述被處理基板的搬 運，爲其特徵者。 又’本發明的基板處理裝置，是在以上的基板處理裝置 中’上述控制手段是欲搬運上述被處理基板的上述處理部 ’經過所定時間也無法接受上述被處理基板時，控制成將上 述被處理基板搬運至可接受上述被處理基板的處理部中優 先度最高的處理部，爲其特徵者。 又’本發明的基板處理裝置，是在以上的基板處理裝置 -6· (4) l27〇956 中，上述處理部分別具有真空隔絕室；上述搬運機構構成 將上述被處理基板搬運至上述真空隔絕室，爲其特徵者。 又，本發明的基板處理裝置，是在以上的基板處理裝置 中，上述複數處理部施以同一處理，爲其特徵者。 本發明的基板處理方法，屬於使用具備在被處理基板施 以所定處理所需的複數處理部，及以所定順序將上述被處 理基板搬運至複數上述處理部的搬運機構的基板處理裝置 的基板處理方法，其特徵爲：記憶複數上述處理部中最後 進行上述被處理基板的處理的處理部，之後開始處理之際 ’從上述被記憶的處理部的下一順序的處理部開始上述被 處理基板的搬運。 又，本發明的基板處理方法，屬於使用具備在被處理 基板施以所定處理所需的複數處理部，及將上述被處理基 板搬運至複數上述處理部的搬運機構的基板處理裝置的基 板處理方法，其特徵爲：分別記億複數上述處理部的累計 處理時間，之後開始處理之際，從上述被記憶的累計處理 時間的最少處理部開始上述被處理基板的搬運。 又，本發明的基板處理方法，是在上述基板處理方法 中’依上述被記憶的累計處理時間的較少處理部的順序， 進行上述被處理基板的搬運，爲其特徵者。 又，本發明的基板處理方法，屬於使用具備在被處理 基板施以所定處理所需的複數處理部，及將上述被處理基 板搬運至複數上述處理部的搬運機構的基板處理裝置的基 板處理方法，其特徵爲：分別記憶複數上述處理部的累計 -7 - (5) 1270956 處理枚數，之後開始處理之際，從上述被記憶的累計處理 枚數的最少處理部開始上述被處理基板的搬運。 又，本發明的基板處理方法，是在上述基板處理方法 中，依上述被記憶的累計處理枚數的較少處理部的順序， 進行上述被處理基板的搬運，爲其特徵者。 又，本發明的基板處理方法，是在以上的基板處理方 法中，欲搬運上述被處理基板的上述處理部，經過所定時 間也無法接受上述被處理基板時，將上述被處理基板搬運 至可接受上述被處理基板的處理部中優先度最高的處理部 ，爲其特徵者。 又，本發明的基板處理方法，是在以上的基板處理方 法中，上述處理部分別具有真空隔絕室；上述搬運機構構 成將上述被處理基板搬運至上述真空隔絕室，爲其特徵者 〇 又，本發明的基板處理方法，是在以上的基板處理方 法中，上述複數處理部施以同一處理，爲其特徵者。 【實施方式】 以下，將本發明的基板處理裝置的詳細，參照圖式說 明實施形態。 第1圖是模式地表示本發明的實施形態的基板處理裝 置的槪略構成者。 如第1圖所示地，基板處理裝置是組合構成在半導體 晶圓W施以所定處理部的複數（在第1圖的裝置爲兩個 -8- (6) 1270956 )的處理船PS 1、PS2，及構成將半導體晶圓w搬運至此 些的搬運機構的裝載機模組LM所構成。 裝載機模組LM是由容納半導體晶圓W的複數（在第 1圖的裝置爲三個）載入端口 LP1~LP3’及搬運半導體晶 圓W的搬運室TR，及進行半導體晶圓W的定位的定位器 Ο R所構成。 在搬運室TR，連結有定位器OR，同時經由真空隔絕 室門 LG1、LG2連接有處理船PS1、PS2，又，經由載入 端口門（CG1〜CG3連結有載入端口 LP1〜LP3。在該載入端 口 LP1〜LP3，設有容納未處理的半導體晶圓 W與經處理 的半導體晶圓W的晶盒或FOUP CS1~CS3 (在以下說明晶 盒的情形）。 在搬運室TR，設有兩段構成的載入臂LAI、LA2。該 裝載機臂LAI、LA2是進行載入端口 LP1〜LP3與處理船 PS1、PS2 (真空隔絕室LL1、LL2 )之間，或是與定位器 OR間的半導體晶圓W的搬運（第1圖的①②⑥的搬運） 。在此，藉由兩段構成裝載機臂LA 1、LA2，成爲以其中 一方的裝載機臂LA 1、LA2進行半導體晶圓W的搬入之 下，以另一方的裝載機臂LA2、LA1進行半導體晶圓 W 的搬出，成爲可有效率地進行半導體晶圓W的更換。 在處理船PS1、PS2，設有真空隔絕室LL1、LL2及處 理室PM1、PM2。真空隔絕室LL1、LL2與處理室PM1、 PM2，真空隔絕室LL1、LL2與處理室PM1、PM2是經由 處理閘P G 1、P G 2互相地連結。 (7) 1270956 在真空隔絕室 LL1、LL2，分別設有晶圓載置台 Bll 、B12、B21、B22及真空隔絕臂LR1、LR2。在晶圓載置 台Bll、B21，載置有從裝載機模組LM所搬入的半導體 晶圓W，同時載置有從真空隔絕室LL1、LL2所搬出的半 導體晶圓W。 又，在晶圓載置台B12、B22，載置有被搬入至處理 室PM1、PM2的半導體晶圓W。又，真空隔絕室臂LR1、 LR2是進行真空隔絕室LL1、LL2與處理室PM1、PM2之 間的半導體晶圓W的搬運（第1圖的③④⑤的搬運）。 在此’爲了得到搬運之效率地，搬運室TR是被大氣開 放’同時載入端口門CG1〜CG3是維持在被開放的狀態。又 ’爲了防止污染，處理室PM1、PM2是被維持在所定真空度 。所以，在真空隔絕室LL1、LL2，對應與搬運室TR之間 的搬運，或與處理室PM 1、PM2之間的搬運，進行對應於各 該真空度所需的供氣、排氣。 以下，列舉進行載入端口 LP1與處理船PS 1之間的搬運 情形’加以說明搬運次序。整體基板處理裝置是成爲藉由控 制裝置MC被總括地控，而搬運次序也藉由該控制裝置MC 被控制。 首先，裝載機臂LAI、LA2是從被裝置於載入端口 LP1 的晶盒CS1取出半導體晶圓W，並搬入至定位器〇R (①） 〇 定位器OR是當搬入半導體晶圓W，則進入半導體晶圓 w的定位。當完成半導體晶圓W的定位，則裝載機臂LA1 -10- (8) 1270956 、LA2是從定位器〇r取出半導體晶圓λν。 之後，當完成真空隔絕室LL1大氣開放，則打開真空 隔絕室LL 1的真空隔絕室門LG 1。當打開真空隔絕室門LG ] ，則裝載機臂LAI ' LA2是將該半導體晶圓w搬入至真空 隔絕室LL1內，並載置在晶圓載置台Β11上（②）。 當半導體晶圓W被載置於晶圓載置台β 1 1上時，則關 閉真空隔絕室門LG 1。之後，進行真空隔絕室l 1內的排氣 ’同時真空隔絕室臂LR1是將晶圓載置台BU上的半導體 晶圓W搬運至晶圓載置台B12(③）。 當半導體晶圓W被搬運至晶圓載置台Bi2，成爲可將半 導體晶圓W搬入至處理室PM 1的狀態，則處理室pm 1的處 理閘PG1被打開，真空隔絕室臂LR1，是將晶圓載置台B12 上的半導體晶圓W搬入至處理室PM1內（④）。 當半導體晶圓W被搬入至處理室pm 1內，則處理閘 P G 1被關閉’使得半導體晶圓w在處理室ρ μ I內被處理。 當完成在處理室PM 1內的半導體晶圓W的處理，成爲 可將半導體晶圓W搬出至真空隔絕室LL 1之狀態，則處理 閘PG1被打開，而真空隔絕臂LR1是將處理室PM 1內的半 導體晶圓W搬運至晶圓載置台β 1丨（⑤）。 之後，開閉處理閘PG1，進行真空隔絕室LL 1內的大氣 開放。當完成真空隔絕室LL 1內的大氣開放，則隨著下一 半導體晶圓W的搬入時機，真空隔絕門LG 1被打開，另一 方的裝載機臂LAI、LA2是將晶圓載置台Β11上的半導體晶 圓W搬出至載入端口 LP1 (⑥），同時另一方的裝載機臂 -11 - 1270956 Ο) LA 1、LA2是將在定位器〇R被定位的下一半導體晶圓w搬 入至真空隔絕室LL1 (②）。 又，在處理室PM 1、PM2所實行的順序（實行順序）， 是並不是半導體晶_ W從真空隔絕室LL1、LL2搬入至處理 室PM 1、PM2的時機，而是在從裝載機模組LM搬入至真空 隔絕室LL1、LL2的時機，成爲能讀入的狀態。結果，在半 導體晶圓W進入至處理室PM 1、PM2爲止的時間，可進行 下一半導體晶圓W所需的事先處理〔例如溫度設定，fcS ( Flow Control System)的流量的自我診斷等，即使打開處理 室PM1、PM2與真空隔絕室LL1、LL2之間的處理閘PG1、 PG2也不會有問題的處理），成爲可提高產量。 在上述構成的基板處理裝置中，新穎之一批（容納有下 一進仃處理的半導體晶圓W的一或複數晶盒）被搬運至載 入端口 LP1〜LP3時，從該晶盒，指定任何一方的處理室 PM1、PM2 (處理船PS1、PS2)，例如可選擇僅將半導體晶 圓W搬運至所指定的處理室PM 1 (處理船PS 1 )而加以處 理的模態，同時將半導體晶圓W依次搬運至兩個處理室 PM1、PM2 (處理船PS1、PS2)，成爲可選擇使用此些兩個 處理室PM1、PM2 (處理船PS1、PS2 )並能在短時間內處理 的模態（或（OR )搬運模態）。 亦即，在一個晶盒，通常容納有25枚半導體晶圓W， 而在上述OR搬運模態中，藉由將此些半導體晶圓W依次使 用兩個處理室PM1、PM2 (設定成實行同一處理），成爲在 短時間內可加以處理。 -12- (10) 1270956 以下，說明一旦成爲空間狀態的基板處理裝置開始處理 時的順序。 一旦完成一批分量的半導體晶圓的處理，一直到下一批 從上一工序被搬運來到爲止空著時間時，亦即，一旦沒有基 板處理裝置的半導體晶圓的處理時，則基板處理裝置是成爲 待機狀態的表示於第2圖的空閒模態（1 0 1 )。 在該狀態，當控制裝置MC認識到下一新穎批（晶盒） 被搬入至載入端口 LP1〜LP3 ( 102 )，首先，起動將整體裝 置從空間狀態恢復成正常狀態的順序（1 03 )。 然後’控制裝置MC是判斷下一批是否爲OR搬運模態 (104 )，若爲〇R模態時，則開如從下一處理室pm (處理 船PS )搬入半導體晶圓W。 亦即，在控制裝置MC，在前一批中，記憶有最後進行 處理的處理室PM (最後處理PM ) ( 1 07 )，當開始這一批 的處理，則從該最後處理PM的下一處理室（例如最後處理 PM爲處理室PM1時，則爲處理室PM2 )開始半導體晶圓W 的搬入。 然後，將半導體晶圓依次搬入（搬出）至兩個處理室 PM1、PM2 (處理船PS1、PS2)而進行處理，當完成被搬入 的一批的所有半導體晶圓W的處理（1 06 )，則記憶這次最 後進行處理的處理室PM (最後處理）（1 07 )，而完成這次 處理。 又，〇R搬運模態未被選擇時（1 04 )，僅將半導體晶圓 W搬入至所指定的處理室PM (處理船PS )而進行處理（ -13- (11) 1270956 1 08 )，當完成被搬入的一批的所有半導體晶圓W的處理（ ]09 )，則這時候也記憶這一次最後進行處理的處理室PM ( 最後處理PM ) (107)，完成這一次的處理。 如上所述，在本實施形態中，控制裝置MC記憶最後進 行處理的處理室PM (最後處理PM )，而下一批爲OR搬運 模態時，則縱下一處理室（例如，最後處理PM爲處理室 PM 1時是處理室PM2 )開始半導體晶圓W的搬入。 因此，可均勻化兩個處理室PM1、PM2 (處理船PS1、 PS2 )的使用頻度，並可抑制在維修週期或零件的消耗度產 生相差的情形。 例如，在OR搬運模態被選擇時，經常從處理室PM 1 ( 處理船PS 1 )開始搬運時，若進行25枚半導體晶圓W的處 理，則成爲在處理室PM 1 (處理船PS 1 )進行1 3枚半導體 晶圓W處理，而在處理室PM2 (處理船PS2)進行12枚的 半導體晶圓W的處理，在一批（晶盒）有一枚使用頻度相 差。因此，若將維修週期作成1 500枚（1 15批）的每一半 導體晶圓W，則在成爲維修週期時，處理室PM 1 (處理船 PS1)與處理室PM2 (處理船PS2)的使用頻度相差在半導 體晶圓W處理枚數成爲1 1 5枚，若平均的一處理時間作成 3.5分鐘，則在累計使用時間上會產生大約6.7小時的相差 〇 對此，依照本實施形態，在上述條件下，可將使用頻度 相差，在半導體晶圓W處理枚數的相差作成一枚以內，而 在累計使用時間的相差作成一處理時間的3.5分鐘以內。由 -14 - (12) 1270956 此，可防止各處理船PS 1、PS2的維修週期或零件的消耗度 上產生相差，而在各處理船PS1、PS2，同時期地，藉由進 行同樣的維修，而在良好狀態下可使用裝置。 又，在第1圖的基板處理裝置中，爲了簡單地說明·，針 對於設置兩個處理船PS 1、PS2的情形加以說明，惟如第3 圖所示地，即使設置三個處理船PS 1、PS2、PS3的情形， 或是設置三個以上數的處理船的情形，也作成與上述情形同 樣而可以適用。又，在第3圖的基板處理裝置中，設有五個 載入端口 LP1〜LP5，惟該載入端口的數量幾個也可以。 此種基板處理裝置的情形，處理順序（—PM 1 — PM2 — PM3— PM1—…的基本上順序）是已被決定之故，因而若記 憶最後處理PM (最後處理室），即可決定下一進行處理的 處理室。例如，最後處理PM (最後處理室）爲處理室PM2 (處理船PS2 )的情形，是從處理室PM3 (處理船PS3 )開 始半導體晶圓W的搬入，而以處理室PM3—處理室PM 1 — 處理室PM2的順序進行半導體晶圓W的搬入。 又，即使未事先決定處理的順序的情形，也記憶剛成爲 空閒狀態之前的（N-1 )枚（N是OR搬運的對象的處理室 數）的半導體晶圓W被處理的處理室，即可決定進行下一 處理的處理室。例如處理室爲三個的情形，剛成爲空閒狀態 之前的兩枚半導體晶圓W被處理的處理室爲PM3— PM1—( 空閒），則下一處理的處理室是成爲PM2。 如上所述地，即使處理船PS爲三個以上的情形，在上 述的條件下，也可將使用頻度的相差，作成在半導體晶圓 -15- (13) 1270956 W處理枚數的相差爲一枚以內，而在累計使用時間的相差 成爲一處理時間爲3.5分鐘以內。 然而，從空間狀態恢復成正常狀態的時間，是藉由其處 理船PS的狀態，每一處理船ps地有不相同的情形。在此 種情形，在上述的次序中，例如成爲從處理室PM2 (處理船 PS2 )開始半導體晶圓W的搬入，且該處理室PM (處理船 PS 2 ) —直成爲接受半導體晶圓w的狀態爲止費時的情形， 則有無法開始半導體晶圓W的搬入，而有降低產量的可能 性。 又，此種情形，處理室PM2 (處理船PS2 ) —直成爲接 受半導體晶圓W的狀態爲止費時，另一方面，在處理室 PM1 (處理船PS1 )或處理室PM3 (處理船PS3 )有成爲已 接受半導體晶圓W的狀態的情形。 所以，開始半導體晶圓W的搬入之際，設置超時，在 設定成該超時的時間內無法搬運至該處理室的情形，則成爲 接受半導體晶圓W的狀態的其他處理室中，從最優先度較 高的處理室能搬運半導體晶圓W就可以。 例如在表示於第2圖的實施例的情形，將下一處理室決 定作爲PM 1，惟在超時設定時間內無法搬運至PM 1的情形 ，則將優先度較高，亦即將PM 1的下一順序的PM2作爲下 一處理室。又，表示於第4、6圖的實施例的情形，也將下 一處理室的優先度次高，亦即將累計處理時間，累計處理枚 數較少的處理室分別作爲下一處理室而開始搬運，就可抑制 降低產量。又，該超時的設定時間，是構成能適當地變更較 -16- (14) 1270956 理想。 然而，上述實施形態的情形，藉由最後處理PM (最後 處理室），來決定開始新穎一批的半導體晶圓W的搬入的 處理室PM，惟例如第4圖所示地，也可構成記憶各處理室 PM的累計處理時間並依次更新該記憶（207 )，而從該累計 處理時間最少的處理室PM (處理船PS )開始搬入（205 ) ，或是如第5圖所示地，也可構成記憶各處理室PM的累計 處理枚數並依次更新該記憶（307 )，而從該累計處理枚數 最少的處理室PM (處理船PS )開始搬入（3 85 )。 又，如上述地，在記憶累計處理時間或累計處理枚數的 情形，若如第3圖所示地具備三個以上的處理船PS 1、PS2 、PS3的情形，則如第4、5圖所示地，也可將整體半導體 晶圓W的搬入順序，作成累計處理時間及累計處理枚數最 少的順序。這時候，例如，處理室PM的累計處理時間爲處 理室PM2<處理室PM1<處理室PM3，則成爲以處理室PM2 — 處理室PM1—處理室PM3的順序搬入半導體晶圓W。 或是’僅由累計處理時間或累計處理枚數來決定在開始 處理時開始搬入的處理室PM (處理船PS )，由下一搬入半 導體晶圓W的處理室PM (處理船PS )，也可作成通常的 順序（依據處理室PM1—處理室PM2—處理室PM3的順序 )。又’在第4、5圖中，其他的次序是與第2圖的情形同 樣。 作成此種構成，即使因混雜OR搬運模態以外而在累計 處理時間或累計處理枚數（使用頻度）產生相差時，也可減 -17 - (15) 1270956 少該累計處理時間或累計處理枚數（使用頻度）的相差。 又，在上述實施形態中，說明了進行一直開放載入端口 閘CG1〜CG3的搬運方法，惟若一直到搬運需費時之情形， 則暫時地關閉載入端口 C G 1〜C G 3也可以。 又’在上述實施形態中，以搬運室TR被大氣開放的狀 態作爲例子加以說明，惟進行搬運室TR的真空吸引也可以 。又，在各真空隔絕室LL1、LL2，針對於晶圓載置台Bl 1 、B12、B21、B22分別設置兩台的情形加以說明，惟晶圓載 置台是各設一台也可以，或是將真空隔絕室臂LR1、LR2兼 用作爲晶圓載置台也可以。 又，裝載機臂LAI、LA2是採用與跟前的半導體晶圓載 置台B 1 1、B2 1可存取的情形爲例子加以說明，惟作成直接 與探部的半導體晶圓載置台B12、B22進行存取也可以。又 ，裝載機臂LA 1、LA2是針對於二段構成的情形加以說明， 惟構成一段也可以。 如上所述地，依照本發明的基板處理裝置及基板處理方 法，可將各處理部的使用頻度成爲均勻化，而可抑制在維 修週期或處理部內的零件的消耗度發生差異。 (產業上的利用可能性） 本發明的基板處理裝置及基板處理方法，是在進行半導 體裝置的製造的半導體製造產業中可使用。因此具有產業上 的利用可能性。 (16) 1270956 [圖式簡單說明】 第1圖是模式地表示本發明的一實施形態的基板處理 裝置的槪略構成的圖式。 第2圖是表示本發明的一實施形態的動作的流程圖。 第3圖是模式地表示本發明的其他實施形態的基板處 理裝置的槪略構成的圖式。 第4圖是表示本發明的其他實施形態的動作的流程圖 〇 第5圖是表示本發明的其他實施形態的動作的流程圖 主要元件對照表 W :半導體晶圓 P S 1、PS2 ：處理船 LM :裝載機模組 LP1〜LP3 :載入端口 〇 R :定位器 LG1〜LG2 :真空隔絕室門 CG1 〜CG3 : _ 入 ^ 口 0 CS1〜CS3 :晶盒 LL1、LL2 :真空隔絕室 LAI、LA2 :裝載機臂 PM1、PM2:處理室 P G 1、P G 2 :處理閘 (17) 12709561270956 (1) Technical Field of the Invention The present invention relates to a substrate processing apparatus and substrate processing for performing a film formation or etching treatment on a substrate to be processed such as a glass substrate for a semiconductor wafer or a liquid crystal display device. method. [Prior Art] A substrate processing apparatus that performs processing such as film formation or etching on a substrate to be processed such as a glass substrate for a semiconductor wafer or a liquid crystal display device includes a plurality of processing units and a processing unit connected thereto. In the transport mechanism, the substrate to be processed is sequentially transported to the plurality of processing units by the transport mechanism, and the same processing or different processing can be applied to each processing unit, and it is known that resources, spaces, and the like can be effectively utilized, and efficiently A substrate processing apparatus that performs processing of a substrate to be processed. In the above-described substrate processing apparatus, for example, the substrate processing apparatus including the first processing unit and the second processing unit performs the same processing, for example, in the first jade and the second processing unit, and is sequentially processed and accommodated. In the case of 25 semiconductor wafers of one crystal cassette, first, the first semiconductor wafer is carried in the i-th processing unit, and the first semiconductor wafer is processed in the first processing unit, and the first semiconductor wafer is While the processing unit performs the processing of the first semiconductor wafer, the second processing unit carries the second semiconductor wafer, and the second processing unit performs the processing of the second semiconductor crystal_ from the first processing. When the first semiconductor wafer is carried out and the third semiconductor wafer is carried in, the processing of 25 semiconductor crystals of -4-(2) 1270956 can be efficiently performed in a short time. However, in the conventional substrate processing apparatus having the above configuration, after a batch of processing is completed, once the processing is suspended, the cassette containing the semiconductor wafer for the next processing is carried, and the semiconductor in the cassette is started. In the case of wafer processing, the semiconductor wafer is transferred from the first processing unit. Therefore, for example, when processing 25 semiconductor wafers in a wafer cassette, 13 semiconductor wafers are processed in the first processing unit, and 12 semiconductor wafers are processed in the second processing unit. deal with. There is a possibility that the frequency of use differs between the first processing unit and the second processing unit, and there is a possibility of a difference in the main sustain period or the consumption of components in the processing. SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate processing apparatus and a substrate processing method capable of reducing the frequency of use of each processing unit and suppressing a difference in the degree of consumption of components in a maintenance cycle or a processing unit. A substrate processing apparatus according to the present invention includes: a plurality of processing units required to perform a predetermined process on a substrate to be processed; a transport mechanism that transports the processed substrate to the plurality of processing units in a predetermined order; and a memory of the plurality of processes In the processing unit that performs the processing of the substrate to be processed, the processing unit that controls the conveyance mechanism to start the conveyance of the substrate to be processed from the processing unit in the next step of the memory processing unit is controlled. Moreover, the substrate processing apparatus of the present invention is characterized in that it includes a plurality of processing units required to perform a predetermined process on the substrate to be processed, and a transport mechanism that transports the substrate to be processed-5-(3) 1270956 to the plurality of processing units. And the control means for controlling the conveyance mechanism to start the conveyance of the substrate to be processed from the minimum processing unit of the accumulated accumulated processing time, when the processing is started, and the processing is started. Further, in the substrate processing apparatus of the present invention, in the substrate processing apparatus, the control means controls the transport means to transport the substrate to be processed in the order of a small number of processing units in accordance with the accumulated accumulated processing time. Its characteristics. Further, the substrate processing apparatus of the present invention includes: a plurality of processing units required to perform a predetermined process on the substrate to be processed; a transport mechanism that transports the processed substrate to the plurality of processing units; and a plurality of the above-described processes When the processing time is started, the processing unit is controlled to control the conveyance of the substrate to be processed from the minimum processing unit of the accumulated accumulated processing time. In the substrate processing apparatus of the present invention, the control means controls the transport means to transport the substrate to be processed in the order of the number of the processing units that are stored in the memory processing. Characterized by it. In the substrate processing apparatus of the present invention, in the above substrate processing apparatus, the control unit is configured to control the substrate to be processed when the processing unit for transporting the substrate to be processed does not receive the substrate to be processed for a predetermined period of time. The processing unit is transported to a processing unit having the highest priority among the processing units that can accept the substrate to be processed, and is characterized by the processing unit. Further, in the substrate processing apparatus of the present invention, in the above substrate processing apparatus-6 (4), the processing unit has a vacuum isolation chamber, and the transport mechanism configured to transport the substrate to be vacuumed. Room, characterized by it. Further, in the substrate processing apparatus of the present invention, in the above substrate processing apparatus, the plurality of processing units are subjected to the same processing and are characterized. The substrate processing method of the present invention pertains to substrate processing using a substrate processing apparatus including a plurality of processing units required for performing a predetermined process on a substrate to be processed, and a transport mechanism for transporting the substrate to be processed to a plurality of processing units in a predetermined order. The method of recording a processing unit that performs the processing of the substrate to be processed last in the processing unit, and then starts the processing, and starts from the processing unit in the next order of the processed processing unit. Handling. Moreover, the substrate processing method of the present invention is a substrate processing method using a substrate processing apparatus including a plurality of processing units required for performing a predetermined process on a substrate to be processed, and a transport mechanism for transporting the substrate to be processed to the plurality of processing units. It is characterized in that the cumulative processing time of the processing unit is calculated in the sum of the billions of the processing units, and the processing of the substrate to be processed is started from the minimum processing unit of the accumulated accumulated processing time. Further, in the substrate processing method of the present invention, in the substrate processing method, the processing of the substrate to be processed is performed in the order of a small number of processing units in which the accumulated processing time is stored. Moreover, the substrate processing method of the present invention is a substrate processing method using a substrate processing apparatus including a plurality of processing units required for performing a predetermined process on a substrate to be processed, and a transport mechanism for transporting the substrate to be processed to the plurality of processing units. It is characterized in that the number of processed -7 - (5) 1270956 processed by the plurality of processing units is memorized, and when the processing is started, the processing of the substrate to be processed is started from the minimum processing unit of the accumulated accumulated processing number. . Further, in the substrate processing method of the present invention, in the substrate processing method, the substrate to be processed is transported in the order of a small number of processed portions of the integrated processed memory. Further, in the substrate processing method of the present invention, in the substrate processing method described above, when the processing unit for transporting the substrate to be processed is not able to receive the substrate to be processed for a predetermined period of time, the substrate to be processed is conveyed to an acceptable state. Among the processing units of the substrate to be processed, the processing unit having the highest priority is a feature. Further, in the substrate processing method of the present invention, in the substrate processing method described above, each of the processing units includes a vacuum isolation chamber, and the transport mechanism constitutes a method of transporting the substrate to be processed to the vacuum isolation chamber. In the substrate processing method of the present invention, in the above substrate processing method, the complex processing unit performs the same processing and is characterized by the same. [Embodiment] Hereinafter, the details of the substrate processing apparatus of the present invention will be described with reference to the drawings. Fig. 1 is a schematic view showing a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention. As shown in Fig. 1, the substrate processing apparatus is a combination processing unit PS1 in which a plurality of predetermined processing units are applied to the semiconductor wafer W (the apparatus of Fig. 1 is two -8-(6) 1270956), PS2 and a loader module LM constituting a transport mechanism for transporting the semiconductor wafer w to such a carrier. The loader module LM is loaded into the ports LP1 to LP3' and the transfer chamber TR for transporting the semiconductor wafer W by a plurality of semiconductor wafers W (three in the apparatus of FIG. 1), and the semiconductor wafer W. The positioned positioner Ο R is composed. In the transfer chamber TR, the positioner OR is connected, and the processing vessels PS1 and PS2 are connected via the vacuum isolation chamber doors LG1 and LG2, and the load ports LP1 to LP3 are connected via the load port gates (CG1 to CG3). The loading ports LP1 to LP3 are provided with a crystal cassette or FOUP CS1 to CS3 for accommodating the unprocessed semiconductor wafer W and the processed semiconductor wafer W (in the case of the crystal cassette described below). Two stages of loading arms LAI, LA2. The loader arms LAI, LA2 are between the loading ports LP1 to LP3 and the processing vessels PS1, PS2 (vacuum isolation chambers LL1, LL2), or between the positioner OR Transportation of the semiconductor wafer W (transport of 126 in Fig. 1). Here, the loader arms LA 1 and LA2 are configured in two stages, and the semiconductor wafer W is performed by one of the loader arms LA 1 and LA2. When the load is carried out, the semiconductor wafer W is carried out by the other loader arms LA2 and LA1, and the semiconductor wafer W can be efficiently replaced. The vacuum isolation chamber LL1 is provided in the processing vessels PS1 and PS2. LL2 and processing chambers PM1, PM2. Vacuum isolation chambers LL1, LL2 and processing PM1, PM2, vacuum isolation chambers LL1, LL2 and processing chambers PM1, PM2 are mutually connected via processing gates PG1, PG2. (7) 1270956 In the vacuum isolation chambers LL1, LL2, wafer mounting tables B11, B12 are respectively provided. B21, B22 and vacuum isolation arms LR1, LR2. On the wafer mounting tables B11 and B21, the semiconductor wafer W carried in from the loader module LM is placed, and the vacuum insulation chambers LL1 and LL2 are placed. The semiconductor wafer W is placed on the wafer mounting tables B12 and B22, and the semiconductor wafer W carried into the processing chambers PM1 and PM2 is placed. Further, the vacuum isolation chamber arms LR1 and LR2 are vacuum chambers LL1 and LL2. The conveyance of the semiconductor wafer W between the processing chambers PM1 and PM2 (the conveyance of 345 in Fig. 1). Here, in order to obtain the efficiency of transportation, the transfer chamber TR is opened to the atmosphere, and the port gate CG1 is loaded. CG3 is maintained in an open state. In order to prevent contamination, the processing chambers PM1 and PM2 are maintained at a predetermined degree of vacuum. Therefore, the vacuum isolation chambers LL1 and LL2 are transported to and from the transfer chamber TR, or Handling between the processing chambers PM 1 and PM2, The line corresponds to the supply and exhaust of each of the vacuum degrees. Hereinafter, the conveyance sequence between the load port LP1 and the processing ship PS 1 will be described. The transfer order will be described. The overall substrate processing apparatus is controlled by the control unit. The MC is collectively controlled, and the transport order is also controlled by the control device MC. First, the loader arms LAI, LA2 take out the semiconductor wafer W from the cassette CS1 mounted on the load port LP1, and carry it into the positioning. The 〇R (1) 〇 positioner OR is a position that enters the semiconductor wafer w when it is carried into the semiconductor wafer W. When the positioning of the semiconductor wafer W is completed, the loader arms LA1 -10- (8) 1270956 and LA2 take out the semiconductor wafer λν from the positioner 〇r. Thereafter, when the atmosphere of the vacuum isolation chamber LL1 is opened, the vacuum isolation chamber door LG 1 of the vacuum isolation chamber LL 1 is opened. When the vacuum chamber door LG is opened, the loader arm LAI 'LA2 carries the semiconductor wafer w into the vacuum chamber LL1 and mounts it on the wafer stage 11 (2). When the semiconductor wafer W is placed on the wafer stage β 1 1 , the vacuum isolation chamber door LG 1 is closed. Thereafter, the evacuation in the vacuum chamber 11 is performed, and the vacuum isolation chamber arm LR1 transports the semiconductor wafer W on the wafer stage BU to the wafer stage B12 (3). When the semiconductor wafer W is transported to the wafer stage Bi2 so that the semiconductor wafer W can be carried into the processing chamber PM1, the processing gate PG1 of the processing chamber pm1 is opened, and the vacuum isolation chamber arm LR1 is crystallized. The semiconductor wafer W on the circular stage B12 is carried into the processing chamber PM1 (4). When the semiconductor wafer W is carried into the processing chamber pm1, the processing gate P G 1 is turned off' so that the semiconductor wafer w is processed in the processing chamber ρ μ . When the processing of the semiconductor wafer W in the processing chamber PM1 is completed, the semiconductor wafer W can be carried out to the vacuum isolation chamber LL1, the processing gate PG1 is opened, and the vacuum isolation arm LR1 is the processing chamber PM. The semiconductor wafer W in 1 is transported to the wafer stage β 1丨(5). Thereafter, the gate PG1 is opened and closed, and the atmosphere in the vacuum chamber LL1 is opened. When the atmosphere in the vacuum isolation chamber LL 1 is completed, the vacuum isolation gate LG 1 is opened as the next semiconductor wafer W is moved in, and the other loader arms LAI, LA2 are placed on the wafer 11 The semiconductor wafer W is carried out to the load port LP1 (6) while the other loader arm -11 - 1270956 Ο LA 1 , LA2 is to carry the next semiconductor wafer w positioned at the positioner 〇R into the vacuum Isolated room LL1 (2). Further, the order (execution order) performed in the processing chambers PM1 and PM2 is not the timing at which the semiconductor wafers W are carried into the processing chambers PM1 and PM2 from the vacuum isolation chambers LL1 and LL2, but in the slave loader mode. When the group LM moves into the vacuum isolation chambers LL1 and LL2, the LM can be read. As a result, the time required for the next semiconductor wafer W (for example, temperature setting, self-diagnosis of the flow rate of the fcS (Flow Control System), etc., can be performed at a time until the semiconductor wafer W enters the processing chambers PM1 and PM2. Even if the processing gates PG1 and PG2 between the processing chambers PM1 and PM2 and the vacuum isolation chambers LL1 and LL2 are opened, there is no problem in processing, and the throughput can be improved. In the substrate processing apparatus of the above configuration, when one of the novel batches (one or a plurality of crystal cassettes containing the semiconductor wafer W of the next processing) is transported to the load ports LP1 to LP3, the design is specified from the crystal cassette. For any of the processing chambers PM1, PM2 (processing vessels PS1, PS2), for example, a mode in which only the semiconductor wafer W is transported to the designated processing chamber PM1 (processing vessel PS1) can be selected, and the semiconductor can be processed. The wafer W is sequentially transported to the two processing chambers PM1, PM2 (processing vessels PS1, PS2), and is a mold that can selectively use the two processing chambers PM1, PM2 (processing vessels PS1, PS2) and can be processed in a short time. State (or (OR) handling mode). That is, in one crystal cassette, 25 semiconductor wafers W are usually accommodated, and in the above-described OR transport mode, two processing chambers PM1, PM2 are sequentially used by the semiconductor wafers W (set to implement the same Processing), can be processed in a short time. -12- (10) 1270956 Hereinafter, the procedure when the substrate processing apparatus in the space state starts processing will be described. Once the processing of a batch of semiconductor wafers is completed, until the next batch is emptied from the previous process, that is, once there is no processing of the semiconductor wafer of the substrate processing apparatus, the substrate processing The device is in the idle mode (1 0 1 ) shown in Fig. 2 in the standby state. In this state, when the control device MC recognizes that the next novel batch (cartridge) is carried into the load ports LP1 to LP3 (102), first, the sequence of starting to restore the entire device from the spatial state to the normal state (1 03) . Then, the control unit MC judges whether or not the next batch is the OR transport mode (104), and if it is the 〇R mode, it moves into the semiconductor wafer W from the next processing chamber pm (processing ship PS). That is, in the control device MC, in the previous batch, the processing chamber PM (final processing PM) (1 07) which is finally processed is memorized, and when the processing of the batch is started, the next processing from the last PM is performed. The processing of the semiconductor wafer W is started in the processing chamber (for example, when the final processing PM is the processing chamber PM1, the processing chamber PM2). Then, the semiconductor wafer is sequentially carried in (lifted out) to the two processing chambers PM1, PM2 (processing vessels PS1, PS2) for processing, and when all of the semiconductor wafers W that have been carried in are processed (1 06), Then, the processing chamber PM (final processing) (1 07) which is the last processing is memorized, and this processing is completed. Further, when the 〇R transport mode is not selected (104), only the semiconductor wafer W is carried into the designated processing chamber PM (processing vessel PS) for processing (-13-(11) 1270956 1 08), When the processing ( ]09) of all the semiconductor wafers W to be carried in is completed, the processing chamber PM (final processing PM) (107) which is finally processed this time is also memorized, and the processing is completed this time. As described above, in the present embodiment, the control device MC memorizes the processing chamber PM (final processing PM) which is finally processed, and when the next batch is the OR transport mode, the processing chamber is vertically processed (for example, the final processing PM) In the processing chamber PM1, the processing chamber PM2) starts the loading of the semiconductor wafer W. Therefore, the frequency of use of the two processing chambers PM1, PM2 (processing vessels PS1, PS2) can be made uniform, and the occurrence of a difference in the maintenance cycle or the consumption of parts can be suppressed. For example, when the OR transport mode is selected, when the processing is performed from the processing chamber PM 1 (processing vessel PS 1 ), if 25 semiconductor wafers W are processed, the processing chamber PM 1 (processing vessel PS 1) 13 semiconductor wafer W processing is performed, and 12 semiconductor wafers W are processed in the processing chamber PM2 (processing ship PS2), and one batch (crystal cassette) has a frequency difference. Therefore, if the maintenance cycle is made into 1,500 (1 15 batches) of each semiconductor wafer W, the processing chamber PM 1 (processing vessel PS1) and the processing chamber PM2 (processing vessel PS2) are used when the maintenance cycle is completed. The frequency difference is 151 pieces in the semiconductor wafer W, and if the average processing time is 3.5 minutes, a difference of about 6.7 hours is generated in the cumulative use time. According to the present embodiment, Under the circumstance, the frequency of use can be made different, and the phase difference between the number of processed semiconductor wafers W can be made within one step, and the phase difference of the accumulated use time can be made within 3.5 minutes of one processing time. By -14 - (12) 1270956, it is possible to prevent the maintenance cycle of the processing vessels PS 1 and PS 2 or the consumption of parts from being different, and the same maintenance is performed on each of the processing vessels PS1 and PS2 at the same time. And the device can be used in good condition. Further, in the substrate processing apparatus of Fig. 1, for the sake of simplicity, the case where two processing vessels PS 1 and PS2 are provided will be described. However, as shown in Fig. 3, even if three processing vessels PS are provided 1. In the case of PS2 and PS3, or the case where three or more processing vessels are installed, the same can be applied as in the above case. Further, in the substrate processing apparatus of Fig. 3, five load ports LP1 to LP5 are provided, but the number of the load ports may be several. In the case of such a substrate processing apparatus, the processing order (the basic order of -PM 1 - PM2 - PM3 - PM1 - ...) has been determined, so if the last processed PM (final processing chamber) is memorized, it can be decided. A processing chamber that performs processing. For example, in the case where the final processing PM (final processing chamber) is the processing chamber PM2 (processing vessel PS2), the loading of the semiconductor wafer W is started from the processing chamber PM3 (processing vessel PS3), and the processing chamber PM3 - processing chamber PM 1 — The processing of the semiconductor wafer W is carried out in the order of the processing chamber PM2. In addition, even if the order of the processing is not determined in advance, the processing chamber in which the semiconductor wafer W of (N-1) (N is the number of processing chambers to be transported by OR) immediately before the idle state is processed is stored, that is, The processing chamber for the next process can be decided. For example, in the case where there are three processing chambers, the processing chambers in which the two semiconductor wafers W immediately before the idle state are processed are PM3 - PM1 - (idle), and the processing chamber of the next processing is PM2. As described above, even if the processing ship PS is three or more, under the above conditions, the phase difference of the frequency of use can be made to be one phase difference between the number of processed semiconductor wafers -15-(13) 1270956 W. Within the range, the difference in the accumulated usage time becomes a processing time of 3.5 minutes or less. However, the time to return from the spatial state to the normal state is by which the state of the ship PS is handled, and each processing ship has a different ps. In this case, in the above-described order, for example, the loading of the semiconductor wafer W is started from the processing chamber PM2 (processing vessel PS2), and the processing chamber PM (processing vessel PS2) becomes the semiconductor wafer w. In the case where the state takes time, there is a possibility that the loading of the semiconductor wafer W cannot be started, and there is a possibility that the yield is lowered. Further, in this case, the processing chamber PM2 (processing vessel PS2) takes time to receive the semiconductor wafer W, and on the other hand, in the processing chamber PM1 (processing vessel PS1) or processing chamber PM3 (processing vessel PS3) It is a case where the state of the semiconductor wafer W has been accepted. Therefore, when the semiconductor wafer W is loaded, a timeout is set, and when it is set to the timeout period, it is not possible to transport it to the processing chamber, and in another processing chamber in which the semiconductor wafer W is received, The processing chamber having the highest priority can transport the semiconductor wafer W. For example, in the case of the embodiment shown in FIG. 2, the next processing chamber is determined as PM 1, but if it cannot be transported to PM 1 within the timeout setting time, the priority is higher, that is, PM 1 The next sequence of PM2 serves as the next processing chamber. Further, in the case of the fourth and sixth embodiments, the priority of the next processing chamber is also the second highest, that is, the processing time is accumulated, and the processing chambers having the smaller number of integrated processing are started as the next processing chamber. By carrying it, it can suppress the reduction of production. In addition, the setting time of the timeout is that the configuration can be appropriately changed compared to -16-(14) 1270956. However, in the case of the above-described embodiment, the processing chamber PM for starting the loading of the novel semiconductor wafer W is determined by the final processing of the PM (final processing chamber). However, for example, as shown in Fig. 4, the memory may be constructed. The accumulated processing time of each processing chamber PM is sequentially updated (207), and the processing chamber PM (processing ship PS) having the smallest accumulated processing time is loaded (205), or as shown in Fig. 5 The accumulated processing number of each processing chamber PM can be stored and the memory (307) can be sequentially updated, and the processing chamber PM (processing ship PS) having the smallest cumulative processing number can be moved in (3 85). In addition, as described above, when three or more processing vessels PS1, PS2, and PS3 are provided as shown in FIG. 3 in the case of the memory integration processing time or the cumulative processing number, as shown in FIGS. 4 and 5 As shown in the figure, the order in which the entire semiconductor wafer W is carried in may be the order in which the cumulative processing time and the number of accumulated processings are the smallest. At this time, for example, the cumulative processing time of the processing chamber PM is the processing chamber PM2 < the processing chamber PM1 < the processing chamber PM3, and the semiconductor wafer W is carried in the processing chamber PM2 - the processing chamber PM1 - the processing chamber PM3. Or, 'the processing chamber PM (processing vessel PS) that is started to be loaded at the start of processing, and the processing chamber PM (processing vessel PS) that is carried into the semiconductor wafer W from the next, is also determined by the cumulative processing time or the cumulative processing number. The order can be made in the usual order (according to the order of the processing chamber PM1 - the processing chamber PM2 - the processing chamber PM3). Further, in the fourth and fifth figures, the other order is the same as in the case of Fig. 2. In such a configuration, even if there is a phase difference between the cumulative processing time and the cumulative processing number (usage frequency) due to the mixed OR transport mode, the -17 - (15) 1270956 can be reduced by the accumulated processing time or the accumulated processing block. The phase difference of the number (usage frequency). Further, in the above-described embodiment, the method of transporting the load port gates CG1 to CG3 is described. However, if it takes time to carry it, the load ports C G 1 to C G 3 may be temporarily closed. Further, in the above embodiment, the state in which the transfer chamber TR is opened by the atmosphere will be described as an example, but vacuum suction of the transfer chamber TR may be performed. Further, in each of the vacuum isolation chambers LL1, LL2, two sets of the wafer mounting tables B1, B12, B21, and B22 are separately provided, but the wafer mounting table may be provided separately or may be vacuum-isolated. The chamber arms LR1, LR2 may also be used as a wafer mounting table. Further, the case where the loader arms LAI and LA2 are accessible to the semiconductor wafer mounts B 1 1 and B2 1 are described as an example, but are directly accessed by the semiconductor wafer mounts B12 and B22 of the probe unit. Also. Further, the loader arms LA 1 and LA2 are described for the case of the two-stage configuration, but it is also possible to constitute one segment. As described above, according to the substrate processing apparatus and the substrate processing method of the present invention, the frequency of use of each processing unit can be made uniform, and the difference in the degree of consumption of components in the maintenance cycle or the processing unit can be suppressed. (Industrial Applicability) The substrate processing apparatus and the substrate processing method of the present invention can be used in a semiconductor manufacturing industry in which a semiconductor device is manufactured. Therefore, it has industrial utilization possibilities. (16) 1270956 [Brief Description of the Drawings] Fig. 1 is a schematic view showing a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention. Fig. 2 is a flow chart showing the operation of an embodiment of the present invention. Fig. 3 is a view schematically showing a schematic configuration of a substrate processing apparatus according to another embodiment of the present invention. Fig. 4 is a flow chart showing the operation of another embodiment of the present invention. Fig. 5 is a flow chart showing the operation of another embodiment of the present invention. Main component comparison table W: semiconductor wafers PS1, PS2: processing ship LM : Loader modules LP1 to LP3 : Load port 〇 R : Positioners LG1 to LG2 : Vacuum isolation chamber doors CG1 to CG3 : _ Input ^ Port 0 CS1 to CS3 : Crystal cassettes LL1, LL2 : Vacuum isolation chambers LAI, LA2 : Loader arm PM1, PM2: Process chamber PG 1, PG 2 : Process gate (17) 1270956
Bll、B12、B21、B22:晶圓載置台 LR1、LR2 :真空隔絕室臂 M C :控制裝置 T R :搬運室 -20-Bll, B12, B21, B22: Wafer mounting table LR1, LR2: Vacuum isolation chamber arm M C : Control device T R : Transfer chamber -20-