WO2002089544A1 - Tableau de connexions et procede de brasage correspondant - Google Patents
Tableau de connexions et procede de brasage correspondant Download PDFInfo
- Publication number
- WO2002089544A1 WO2002089544A1 PCT/JP2002/004293 JP0204293W WO02089544A1 WO 2002089544 A1 WO2002089544 A1 WO 2002089544A1 JP 0204293 W JP0204293 W JP 0204293W WO 02089544 A1 WO02089544 A1 WO 02089544A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- soldering
- land
- wiring board
- solder
- soldering land
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3468—Applying molten solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/046—Means for drawing solder, e.g. for removing excess solder from pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a four-way flat package integrated circuit (Quad FlatPac)
- This is related to a wiring board on which electronic components having a narrow lead pitch, represented by “kag e” (hereinafter referred to as “QFPIC”), are surface-mounted by soldering. More specifically, the present invention relates to a wiring board suitable for soldering an electronic component having a narrow lead pitch by using a jet-type soldering method.
- the surface mount component QFP IC 2 has a substantially square shape, and has a plurality of leads 3 all around its four sides.
- lands 4 are arranged on the wiring board 1 so as to correspond to the leads 3. Since the leads 3 are arranged at a narrow pitch, a solder bridge is likely to occur between the leads when performing the jet-type soldering. In particular, when pins are continuously arranged in a direction perpendicular to the moving direction of the board in the jet-type soldering, the frequency of occurrence of solder bridges increases. For this reason, for example, as shown in FIG.
- the soldering is performed such that the QFP IC is inclined at an angle of about 45 degrees with respect to the moving direction of the board in the jet-type soldering. In this way, improvement measures have been taken to make the solder jet contact the lead and land in order from the top lead, and to promote the flow of solder.
- soldering land a land for preventing solder bridge
- the intermediate soldering land 12 and the lead and land on the rear two sides are located close to the QFPIC 2 between the lead and land group 10 on the front two sides and the lead pin and land group 11 on the rear two sides.
- a tail soldering land 13 close to QFPIC 2 is formed at the tail of group 11.
- FIG. A schematically shows this from the side of the wiring board 1.
- the solder flowing in the lead and land in sequence is drawn into the soldering land 13 using the surface tension to prevent the formation of excess solder pool on the lead and land. ing.
- This principle is the same for both the intermediate soldering land 12 and the last soldering land 13.
- soldering land 13 there is an issue as to how to draw on the side.
- the solder pools for the two rows of rear lead groups are concentrated.
- solder bridges are likely to occur between leads or lands, and know-how such as selecting the optimal land shape of the last soldering land is required.
- FIG. 7B proper soldering is as shown in FIG. 22.
- a solder bridge 23 between leads may be generated due to excess solder.
- solder-free solder that does not contain lead which plays an important role in lowering the melting point and improving flowability and wettability, has poor flowability and wettability, so the frequency of occurrence of solder bridges is further increased. It will be higher.
- An object of the present invention is to solve many of the conventional problems as described above, and to provide a wiring board capable of performing good jet-flow soldering of QFPIC and a method of manufacturing the same. Disclosure of the invention
- a first soldering land is provided at a corner of the QFPIC mounted on the board, and a second soldering land is provided on a side substantially opposite to the QFPIC with respect to the first soldering land.
- the configuration is such that a land is provided.
- the corner provided with the first or second soldering land is the last in the moving direction of the wiring board to the solder jet tank. In this way.
- a wiring board according to the present invention is a wiring board on which at least a QFP IC is mounted on a surface, comprising a first soldering land on at least one corner of the QFP IC, and a first soldering land. On the opposite side of the pull land from the QFP IC, a second solder pull land is provided adjacent to the first solder pull land.
- a first soldering land is provided on two corners of a substrate which are located at opposite corners of a QFP IC, and the first soldering land is provided with respect to the first soldering land.
- a second soldering land is provided adjacent to the first soldering land.
- This configuration increases the degree of freedom during soldering. For example, multiple individual wiring boards are rotated 180 degrees to face each other and In this case, the direction of movement of the QFP is reversed, but the board movement direction for jet-type soldering can be determined without special consideration on the pattern. In addition, even at the time of designing the pattern of the wiring board, the direction of placement of the QFPIC does not matter and the design becomes easy.
- the first soldering land is disposed on two sides of the QFPIC adjacent to the corner with a diagonal line between the corner where the first soldering land of the QFPIC is arranged. It is divided and arranged along the line of the QFP lead.
- the excess solder on the two sides sandwiching the corners where the first and second soldering lands of the QFPIC are arranged is transferred to the final leads of each lead group (the wiring board is moved to the jet tank by the jet-flow soldering method).
- the first soldering land provided in contact with the lead located at the last part in the moving direction when moved is moved by the first soldering land, and the excess soldering force is guided to the second soldering land.
- the first soldering land is not connected to each side. Since each of them is separated from each other, the electrical connection can avoid short circuit, and the connection safety can be further improved.
- first and second soldering lands having the same shape with respect to the center of the QFPIC.
- the second soldering land is equivalent to the first soldering land.
- the area may be larger.
- the first soldering land also has a large soldering allowance of the second soldering land, so that the solder is easily guided to the second soldering land, and the effect of preventing solder bridges is further increased. be able to.
- At least one of the first and second soldering lands can be configured to have a substrate through hole in the copper foil portion of the land.
- gas generated during soldering can be efficiently removed from the soldering land portion, soldering failure due to gas foaming can be suppressed, and soldering quality can be further improved.
- At least the first soldering land has a first position with respect to the arrangement of the QFPIC lead group on two sides adjacent to the first corner of the QFPIC on which the first soldering land is arranged. It can be configured to have a tapered shape in a direction from the second corner and the third corner that are not diagonal to the corner and substantially toward the first corner.
- surplus solder can be easily guided from the first soldering land to the second soldering land, and even if excessive surplus solder is generated, the second soldering land can be effectively formed. Can be transferred to For this reason, the possibility that surplus solder returns from the first soldering land to the final lead or land on the QFPIC side is reduced, and the yield and reliability as a wiring board are improved.
- At least the second soldering land has a tapered shape in a direction substantially opposite to the QFPIC with respect to the first corner of the QFPIC on which the second soldering land is arranged.
- the surplus solder guided to the second soldering land can easily separate unnecessary solder from the movement of the wiring board. For this reason, the possibility that surplus solder is stored on the wiring board or leads to a short circuit with another land can be greatly reduced. And, by using the present invention in soldering using lead-free solder, the flowability of solder containing no lead and the property of poor wettability are covered, and the frequency of occurrence of solder bridges is further reduced. You can do so. In addition, the use of lead-free solder makes it possible to manufacture products that are suitable for environmental protection.
- FIG. 1 shows a wiring board according to Embodiment 1 of the present invention.
- the conventional soldering land as shown in Fig. 6 all surplus solder must be processed by one soldering land.
- Another problem is that the surface tension must be optimized in order to smoothly guide the excess solder to the solder land by the land area and the surface tension of the solder itself. Due to these problems, the solder bridge drawn could not be eliminated because the amount of solder drawn into the last soldering land was not stable.
- the lands are divided so that surplus solder can be drawn in stepwise, and the primary and secondary soldering lands 13a and 13b are arranged.
- the excess solder is first drawn into the primary soldering land 13a at the end of the side of QFPIC in the moving direction of the jet-type soldering.
- the excess solder is drawn into the secondary soldering land 13b.
- the amount of excess solder held on the land 13a can be reduced.
- the lands 13a and 13b have a triangular shape, but the lands 13a and 13b are arranged in order according to the moving direction of the wiring board. Is not limited to a triangle, but may be a round shape or a square shape. However, it is preferable that at least the second land 13b has a tapered shape such as a triangle in a direction opposite to the moving direction of the wiring board during the jet soldering, as shown in FIG. (Embodiment 2)
- FIG. 2 shows a wiring board according to Embodiment 2 of the present invention.
- a triangular second soldering land 13 b opposite to a triangular first soldering land 13 a is arranged, and the second soldering land 13 b has a second area larger than the area of the first land 13 a.
- the area of land 13b was set large. This makes it easier for the solder to move to the second land 13b side, and it is possible to more effectively prevent backflow adhesion due to swing back of the drawn-in solder.
- each land shape is not limited to a triangle.
- first and second lands 13a and 13b are arranged at opposite corners of the QFPIC 2 so as to be substantially symmetric with respect to the center of the QFPIC 2, a plurality of lands can be provided.
- the wire board is simultaneously flowed into the line of the solder jet tank and soldered, even if the board is arranged in the opposite direction, the soldering can be performed well.
- FIG. 3A shows a wiring board according to Embodiment 3 of the present invention.
- the soldering land 30 is disposed on the center axis of the pin array for preventing solder bridging and behind the movement of the wiring board.
- the shape of the land shall be such that the area decreases as the distance from the land targeted for solder bridge prevention increases. This is to prevent the backflow from returning to the target land by gradually releasing the jet solder from the land.
- the solder guide land 31 plays a role of drawing solder into a land that requires solder bonding. They are placed in places where solder flow and wettability are poor, and play a role in improving solderability. This is expected to have an effect opposite to that of the soldering land 30 described above, and it is effective to adopt a land shape whose area increases as it approaches the target land as shown in FIG. 3B.
- the rear side of the order of soldering is arranged on the arrangement axis of the lead group on the rear two sides.
- a first soldering land 13a having a triangle for reducing the area is arranged.
- the first soldering lands 13a are arranged on the two rear sides, and the second soldering lands 13b for integrating these two and guiding the solder are arranged on the rear side.
- This also has a triangular shape whose area decreases in a direction away from the first soldering land 13a. Therefore, a soldering land composed of three triangles is formed.
- the land consisting of these three triangles can be realized by performing resist printing on one rectangular copper foil and dividing it into three parts.In the present invention, as shown in FIG. And realize it.
- the shape of the soldering land is optimized based on the above-described principle, the drawing in of the surplus solder is improved, and the solder bridge between the adjacent final lead and the first soldering land 13a is formed. Even if this occurs at the same time on the two rear sides, it is possible to prevent a short circuit between the final leads. Since electrical connection is ensured, more stable soldering and improved yield can be achieved.
- each of the soldering lands described above is not limited, but is preferably a shape as shown in FIGS. 3A and 3B.
- the direction in which the soldering lands are put into the jet-type soldering tank is not limited. Therefore, when a plurality of individual wiring boards are rotated 180 degrees and face each other, The movement direction of QFP is reversed, but soldering is possible without any problem. Also, at the time of wiring board design, the pattern design becomes easy because the orientation of the QFPIC does not matter.
- a land shape based on a triangle is used.
- such a shape is easy to pattern and beautiful.
- each land shape is not limited to a triangle.
- FIG. 5 shows a wiring board according to a fourth embodiment of the present invention.
- a through-hole 16 penetrating the wiring board is provided in the second soldering land 13b at the end of the third embodiment.
- the through-hole may be provided in the first soldering land 13a.
- each land shape is not limited to a fixed shape.
- Q FP IC has been described as an example of a mounted component.
- the present invention is suitable not only for Q FP IC but also for a wiring board on which a component having a narrow mounting lead pitch is mounted.
- the excess solder guided by the second soldering lands removes unnecessary solder for the movement of the wiring board. It can be easily separated. As a result, excess solder The possibility of being stored on the substrate or leading to a short circuit with another land can be greatly reduced. In this way, stable soldering of QFPIC can be realized even in jet-type soldering.
- soldering using lead-free solder By using the present invention for soldering using lead-free solder, the flowability and poor wettability of lead-free solder are covered, and the frequency of occurrence of solder bridges is further reduced. You can do so. At the same time, it will be possible to construct products suitable for environmental protection.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02722879A EP1383365A4 (en) | 2001-04-27 | 2002-04-26 | WIRING BOARD AND SOLDERING PROCESS THEREFOR |
US10/311,993 US6998861B2 (en) | 2001-04-27 | 2002-04-26 | Wiring board and soldering method therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001131466A JP3633505B2 (ja) | 2001-04-27 | 2001-04-27 | プリント配線基板およびプリント配線基板の半田付け方法 |
JP2001-131466 | 2001-04-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002089544A1 true WO2002089544A1 (fr) | 2002-11-07 |
Family
ID=18979651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/004293 WO2002089544A1 (fr) | 2001-04-27 | 2002-04-26 | Tableau de connexions et procede de brasage correspondant |
Country Status (6)
Country | Link |
---|---|
US (1) | US6998861B2 (ja) |
EP (1) | EP1383365A4 (ja) |
JP (1) | JP3633505B2 (ja) |
KR (1) | KR100506030B1 (ja) |
CN (2) | CN1229003C (ja) |
WO (1) | WO2002089544A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105555024A (zh) * | 2014-10-24 | 2016-05-04 | 富士施乐株式会社 | 基板、基板装置以及基板装置的制造方法 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3988720B2 (ja) * | 2003-12-11 | 2007-10-10 | 三菱電機株式会社 | 4方向リードフラットパッケージic実装プリント配線基板及び4方向リードフラットパッケージicの半田付け方法、4方向リードフラットパッケージic実装プリント配線基板を備えた空気調和機。 |
JP4222260B2 (ja) * | 2004-06-03 | 2009-02-12 | 三菱電機株式会社 | リード形電子部品実装プリント配線基板及び空気調和機 |
JP4692085B2 (ja) * | 2005-06-09 | 2011-06-01 | 株式会社村田製作所 | 電子部品 |
JP4207934B2 (ja) | 2005-08-09 | 2009-01-14 | 三菱電機株式会社 | 4方向リードフラットパッケージic実装プリント配線基板、4方向リードフラットパッケージicの半田付方法、空気調和機。 |
JP4196979B2 (ja) * | 2005-09-07 | 2008-12-17 | 三菱電機株式会社 | リード形電子部品実装プリント配線基板、リード形電子部品の半田付方法、空気調和機。 |
JP2007207826A (ja) * | 2006-01-31 | 2007-08-16 | Orion Denki Kk | プリント基板 |
KR100622299B1 (ko) * | 2006-02-10 | 2006-09-19 | 박경찬 | 케이블관 밀폐용 밀폐구 |
JP2009141106A (ja) * | 2007-12-06 | 2009-06-25 | Mitsubishi Electric Corp | プリント配線基板、空気調和機、プリント配線基板の半田付け方法 |
CN101868123B (zh) * | 2010-07-02 | 2011-12-28 | 深圳和而泰智能控制股份有限公司 | 印刷电路板及设计方法 |
JP5496118B2 (ja) * | 2011-01-14 | 2014-05-21 | 三菱電機株式会社 | プリント配線基板、4方向リードフラットパッケージicの半田付方法および空気調和機 |
JP5924517B2 (ja) * | 2011-07-29 | 2016-05-25 | 株式会社ノーリツ | プリント基板及びプリント基板の製造方法 |
US9307640B2 (en) * | 2012-11-19 | 2016-04-05 | Magna Electronics Inc. | PCB pad for imager of vehicle vision system |
CN104363698B (zh) * | 2014-07-15 | 2018-05-11 | 邯郸美的制冷设备有限公司 | 线路板的列引脚封装结构及封装设计方法和线路板 |
JP7034677B2 (ja) * | 2017-11-17 | 2022-03-14 | ソニー・オリンパスメディカルソリューションズ株式会社 | 医療用回路基板及び医療機器 |
EP3723466A4 (en) * | 2017-12-04 | 2020-11-25 | Fuji Corporation | SYSTEM FOR CHECKING THE MOUNTING ORIENTATION OF AN ELECTRONIC COMPONENT AND METHOD OF CHECKING THE MOUNTING ORIENTATION OF AN ELECTRONIC COMPONENT |
CN108288610A (zh) * | 2018-04-20 | 2018-07-17 | 深圳市锐钜科技有限公司 | 一种新型芯片拖锡焊盘设计及其在红胶工艺中应用 |
WO2020188718A1 (ja) * | 2019-03-18 | 2020-09-24 | 三菱電機株式会社 | プリント配線板及び電子機器 |
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JPH0254598A (ja) * | 1988-08-18 | 1990-02-23 | Matsushita Electric Ind Co Ltd | 集積回路部品の実装済プリント基板の製造方法 |
JPH06164120A (ja) * | 1992-09-22 | 1994-06-10 | Victor Co Of Japan Ltd | プリント配線基板 |
JPH08323495A (ja) * | 1995-03-31 | 1996-12-10 | Hitachi Ltd | 鉛フリーはんだ及びそれを用いた実装品 |
JPH11251725A (ja) * | 1998-03-04 | 1999-09-17 | Mitsuba Corp | プリント配線基板およびそれを使用した半田付け方法 |
JP2000040869A (ja) * | 1998-07-22 | 2000-02-08 | Nippon Seiki Co Ltd | プリント配線板 |
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US4891472A (en) * | 1987-09-10 | 1990-01-02 | Siemens Aktiengesellschaft | Interconnects on a printed circuit board having connecting points for an electronic component with a plurality of terminals |
US5010448A (en) * | 1987-12-18 | 1991-04-23 | Alpine Electronics Inc. | Printed circuit board |
JPH05315733A (ja) * | 1992-05-07 | 1993-11-26 | Sanyo Electric Co Ltd | プリント配線基板 |
JPH08242067A (ja) * | 1995-03-01 | 1996-09-17 | Diamond Electric Mfg Co Ltd | フラットパッケージic用プリント配線基板のパターン形状 |
US5679929A (en) * | 1995-07-28 | 1997-10-21 | Solectron Corporqtion | Anti-bridging pads for printed circuit boards and interconnecting substrates |
JPH09181435A (ja) * | 1995-12-27 | 1997-07-11 | Sharp Corp | プリント配線基板 |
US5877033A (en) * | 1997-03-10 | 1999-03-02 | The Foxboro Company | System for detection of unsoldered components |
-
2001
- 2001-04-27 JP JP2001131466A patent/JP3633505B2/ja not_active Expired - Fee Related
-
2002
- 2002-04-25 CN CNB021183694A patent/CN1229003C/zh not_active Expired - Fee Related
- 2002-04-25 CN CN02231085U patent/CN2547092Y/zh not_active Expired - Lifetime
- 2002-04-26 WO PCT/JP2002/004293 patent/WO2002089544A1/ja active IP Right Grant
- 2002-04-26 US US10/311,993 patent/US6998861B2/en not_active Expired - Lifetime
- 2002-04-26 KR KR10-2002-7017736A patent/KR100506030B1/ko not_active IP Right Cessation
- 2002-04-26 EP EP02722879A patent/EP1383365A4/en not_active Ceased
Patent Citations (5)
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JPH0254598A (ja) * | 1988-08-18 | 1990-02-23 | Matsushita Electric Ind Co Ltd | 集積回路部品の実装済プリント基板の製造方法 |
JPH06164120A (ja) * | 1992-09-22 | 1994-06-10 | Victor Co Of Japan Ltd | プリント配線基板 |
JPH08323495A (ja) * | 1995-03-31 | 1996-12-10 | Hitachi Ltd | 鉛フリーはんだ及びそれを用いた実装品 |
JPH11251725A (ja) * | 1998-03-04 | 1999-09-17 | Mitsuba Corp | プリント配線基板およびそれを使用した半田付け方法 |
JP2000040869A (ja) * | 1998-07-22 | 2000-02-08 | Nippon Seiki Co Ltd | プリント配線板 |
Non-Patent Citations (1)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105555024A (zh) * | 2014-10-24 | 2016-05-04 | 富士施乐株式会社 | 基板、基板装置以及基板装置的制造方法 |
Also Published As
Publication number | Publication date |
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CN1384697A (zh) | 2002-12-11 |
EP1383365A4 (en) | 2005-08-24 |
JP3633505B2 (ja) | 2005-03-30 |
EP1383365A1 (en) | 2004-01-21 |
CN2547092Y (zh) | 2003-04-23 |
US20030156391A1 (en) | 2003-08-21 |
KR20040002404A (ko) | 2004-01-07 |
CN1229003C (zh) | 2005-11-23 |
KR100506030B1 (ko) | 2005-08-04 |
JP2002329955A (ja) | 2002-11-15 |
US6998861B2 (en) | 2006-02-14 |
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