US7964454B2 - Low noise and high performance LSI device, layout and manufacturing method - Google Patents

Low noise and high performance LSI device, layout and manufacturing method Download PDF

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US7964454B2
US7964454B2 US11/981,153 US98115307A US7964454B2 US 7964454 B2 US7964454 B2 US 7964454B2 US 98115307 A US98115307 A US 98115307A US 7964454 B2 US7964454 B2 US 7964454B2
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stress
control layer
devices
forming
stress control
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US20080064157A1 (en
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Shigenobu Maeda
Jeong Hwan Yang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to US12/984,261 priority patent/US8816440B2/en
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Priority to US14/337,532 priority patent/US9093306B2/en
Priority to US14/791,770 priority patent/US9425182B2/en
Priority to US15/211,012 priority patent/US9899386B2/en
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    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Definitions

  • the invention is directed to semiconductor devices and, more particularly, to Large Scale Integration (LSI) semiconductor devices, such as metal-oxide-silicon (MOS) transistors in which mechanical stress engineering is employed to improve device performance.
  • LSI Large Scale Integration
  • MOS metal-oxide-silicon
  • the carrier mobility in a MOS transistor has a significant impact on power consumption and switching performance of the device. Improvement in carrier mobility allows faster switching speed and allows for operation at low voltages, resulting in reduced power consumption.
  • FIG. 1 is a schematic cross-sectional view of a MOS device illustrating an approach to introducing mechanical stress to improve carrier mobility in the device.
  • the device is formed in a substrate 10 and is isolated by isolation regions 12 formed in the substrate 10 .
  • the transistor device includes source/drain regions 22 , 26 formed in the substrate 10 defining a channel region 18 therebetween.
  • a gate structure includes a gate dielectric 14 formed on the substrate 10 , a conductive gate layer 20 over the gate dielectric and a silicide layer 30 formed over the conductive gate layer 20 . Insulating sidewall spacers 24 are formed on the sidewalls of the gate structure.
  • tensile stress is introduced into the channel 18 by a stress control layer 40 formed over the gate structure and the top surface of the source/drain regions 26 and substrate 10 .
  • tensile stress is introduced into the MOS transistor structure as indicated by the arrows in the figure.
  • Another approach to introducing tensile stress into the channel 18 is the silicide layer 30 formed in the source/drain regions 22 , 26 . After silicidation, the silicide regions 30 occupy less volume than the original source/drain material replaced by the silicide. As a result, tensile stress is introduced into the channel 18 .
  • Flicker noise is also commonly referred to as “pink noise” because most of the noise power is concentrated at the lower end of the frequency spectrum. Flicker noise is considered to be caused not only by the trapping and detrapping of carriers, but also by mobility modulation via carrier scattering due to the trapped charges.
  • Flicker noise degradation can be an important factor for both low frequency analog circuits and high performance digital circuits. Although the flicker noise is generated at relatively low frequencies, the noise may be very significant to some RF circuits since it is up-converted to the high frequency spectrum and degrades the coherency of oscillation.
  • FIGS. 2A and 2B are graphs illustrating the relationship between stress engineering in a MOS device and noise.
  • FIG. 2B is a graph of Noise Power Ratio versus maximum transconductance (Gmmax) improvement ratio of a CMOS device. The graph of FIG. 2B illustrates that both tensile and compressive stress on a MOS device degrade performance from the standpoint of flicker noise.
  • Gmmax maximum transconductance
  • the invention is directed to a method of fabricating a circuit.
  • a plurality of devices of a plurality of conductivity types are formed in a plurality of regions of the circuit, the plurality of devices being adapted to perform in a plurality of associated operational modes.
  • a mechanical stress is applied to at least one selected device, the selected device being selected based on its associated operational mode.
  • the operational modes can include an analog mode and a digital mode.
  • the operational modes can also include a noise-sensitive mode and a noise-insensitive mode, a low-speed operation mode and a high-speed operation mode, and a high-voltage operation mode and a low-voltage operation mode.
  • the devices comprise at least one PMOS device and/or one NMOS device.
  • the devices can include at least one CMOS device.
  • mechanical stress is applied to a channel of an NMOS device in the digital mode. In one embodiment, mechanical stress is applied to the channel of a PMOS device in the digital mode.
  • stress is not applied to a device operating in an analog mode to prevent an increase in electrical noise.
  • the electrical noise can be flicker noise.
  • applying a mechanical stress to at least one selected device comprises forming a stress control layer on the circuit in proximity to the devices.
  • the stress control layer can apply a tensile stress and/or a compressive stress.
  • stress is release in the stress control layer in proximity to devices to which stress is not to be applied.
  • Releasing the stress in the stress control layer can include implanting ions into the stress control layer.
  • Releasing the stress in the stress control layer can include selectively removing portions of the stress control layer.
  • the stress control layer can include SiN, SiON or SiO 2 .
  • Forming the stress control layer can include an annealing step. Forming the stress control layer can include performing plasma-enhanced chemical vapor deposition (PECVD) and/or low-pressure chemical vapor deposition (LPCVD).
  • PECVD plasma-enhanced chemical vapor deposition
  • LPCVD low-pressure chemical vapor deposition
  • applying a mechanical stress to at least one selected device comprises performing a silicidation process on the circuit. In one embodiment, applying a mechanical stress to at least one selected device further comprises: forming a capping layer on the circuit; selectively removing the capping layer in proximity to devices to which stress is to be applied; and performing a second silicidation process to apply stress to the devices to which stress is to be applied.
  • applying a mechanical stress to at least one selected device comprises epitaxially growing a source/drain structure in a device to which stress is to be applied.
  • stress is applied to a first device in a first CMOS structure and to a second device in the first CMOS structure; and stress is not applied to a first device in a second CMOS structure and to a second device in the second CMOS structure.
  • the first CMOS structure operates in a digital mode and the second CMOS structure operates in an analog mode.
  • the first device in the first CMOS structure is a PMOS device; the second device in the first CMOS structure is an NMOS device; the PMOS device has a compressive stress applied to its channel; and the NMOS device has a tensile stress applied to its channel.
  • the first device in both the first CMOS structure and the second CMOS structure is a PMOS device.
  • the second device in both the first CMOS structure and the second CMOS structure is an NMOS device.
  • applying the mechanical stress comprises: forming a first stress control layer on the circuit, the stress control layer applying a tensile stress on the devices; selectively removing the first stress control layer in proximity to devices that do not require tensile stress; forming a second stress control layer on the devices, the second stress control layer applying a compressive stress on the devices; forming a stress release layer over the second stress control layer in proximity to a selected portion of the devices; and using the stress release layer, releasing stress in devices that do not require the compressive stress.
  • Releasing stress in devices that do not require the compressive stress can include implanting ions into the stress release layer.
  • applying the mechanical stress comprises: forming a first stress control layer on the circuit, the stress control layer applying a tensile stress on the devices; selectively removing the first stress control layer in proximity to devices that do not require tensile stress; forming a second stress control layer on the devices, the second stress control layer applying a compressive stress on the devices; and selectively removing the second stress control layer in proximity to devices that do not require the compressive stress.
  • the invention is directed to a circuit.
  • the circuit includes a substrate on which are formed a plurality of devices of a plurality of conductivity types in a plurality of regions of the circuit, the plurality of devices being adapted to perform in a plurality of operational modes. At least one selected device among the plurality of devices has a mechanical stress applied thereto, the selected device being selected based on its operational mode.
  • the operational modes can include an analog mode and a digital mode.
  • the operational modes can also include a noise-sensitive mode and a noise-insensitive mode, a low-speed operation mode and a high-speed operation mode, and a high-voltage operation mode and a low-voltage operation mode.
  • the devices comprise at least one PMOS device and/or one NMOS device.
  • the devices can include at least one CMOS device.
  • mechanical stress is applied to a channel of an NMOS device in the digital mode. In one embodiment, stress is applied to a channel of a PMOS device in the digital mode.
  • stress is not applied to a device operating in an analog mode to prevent an increase in electrical noise.
  • the electrical noise can be flicker noise.
  • the mechanical stress is applied to a selected device using a stress control layer on the circuit in proximity to the devices.
  • the stress control layer can apply a tensile and/or a compressive stress.
  • stress is released in the stress control layer in proximity to devices to which stress is not applied. Portions of the stress control layer in which stress is released can include additional implanted ions.
  • the stress control layer is absent in proximity to devices to which stress is not applied.
  • the stress control layer can include SiN, SiON and/or SiO 2 .
  • the stress control layer is annealed.
  • the stress control layer is a layer formed by PECVD or LPCVD.
  • a means by which the mechanical stress is applied comprises silicide.
  • a means by which the mechanical stress is applied comprises an epitaxially grown source/drain structure.
  • stress is applied to a first device in a first CMOS structure and to a second device in the first CMOS structure; and stress is not applied to a first device in a second CMOS structure and to a second device in the second CMOS structure.
  • the first CMOS structure operates in a digital mode and the second CMOS structure operates in an analog mode.
  • the first device in the first CMOS structure is a PMOS device; the second device in the first CMOS structure is an NMOS device; the PMOS device has a compressive stress applied to its channel; and the NMOS device has a tensile stress applied to its channel.
  • the first device in both the first CMOS structure and the second CMOS structure is a PMOS device.
  • the second device in both the first CMOS structure and the second CMOS structure is an NMOS device.
  • a means by which the mechanical stress is applied comprises: a first stress control layer on the circuit, the first stress control layer applying a tensile stress on the devices, the first stress control layer being present only in proximity to devices requiring the tensile stress; a second stress control layer on the devices, the second stress control layer applying a compressive stress on the devices; and a stress release layer over the second stress control layer in proximity to a selected portion of the devices, the stress release layer releasing stress in devices that do not require the compressive stress.
  • the stress release layer comprises additional implanted ions.
  • a means by which the mechanical stress is applied comprises: a first stress control layer on the circuit, the stress control layer applying a tensile stress on the devices, the first stress control layer being present only in proximity to devices requiring the tensile stress; a second stress control layer on the devices, the second stress control layer applying a compressive stress on the devices, the second stress control layer being present only in proximity to devices requiring the compressive stress.
  • the invention is directed to a method of fabricating a circuit.
  • a first MOS device of a first conductivity type is formed in a first area of the circuit.
  • a second MOS device of the first conductivity type is formed in a second area of the circuit.
  • a stress is applied to channels of the first and second MOS devices. The stress applied to the channel of the second MOS device is released.
  • a stress control layer is formed on the circuit in proximity to the first and second MOS devices, the stress control layer applying the stress to the first and second MOS devices.
  • the stress control layer can be formed by low pressure chemical vapor deposition (LPCVD).
  • the stress control layer can also be formed by plasma enhanced chemical vapor deposition (PECVD).
  • the stress control layer can include SiN formed at low temperature.
  • releasing the stress comprises implanting ions into the stress control layer.
  • the stress control layer can comprise SiN.
  • the stress is a compressive stress. In one embodiment, the stress is a tensile stress.
  • the invention is directed to a method of fabricating a circuit.
  • a first MOS device of a first conductivity type is formed in a first area of the circuit.
  • a second MOS device of the first conductivity type is formed in a second area of the circuit.
  • a stress is applied to a channel of the first MOS device.
  • applying a stress to the channel of the first MOS device comprises forming a stress control layer on the circuit in proximity to the first and second MOS devices.
  • the stress control layer can be formed by PECVD.
  • the stress control layer can comprise SiON.
  • the stress control layer can comprise SiO 2 .
  • the method further comprises removing the stress control layer from the second MOS device and leaving a portion of the stress control layer on the first MOS device. In one embodiment, the method further comprises annealing the portion of the stress control layer on the first MOS device.
  • the method further comprises performing a first heat treatment to form a first phase silicide in proximity to the first and second MOS devices.
  • a capping layer can be formed over the first and second MOS devices and the first phase silicide. A portion of the capping layer on the first MOS device and the first phase silicide can be removed.
  • a second heat treatment can be performed to transform the first phase silicide into a second phase silicide.
  • the stress is a compressive stress. In one embodiment, the stress is a tensile stress.
  • the invention is directed to a method of fabricating a circuit.
  • a first CMOS device is formed in a first area of the circuit, the first CMOS device comprising a first MOS device of a first conductivity type and a second MOS device of a second conductivity type.
  • a second CMOS device is formed in a second area of the circuit, the second CMOS device comprising a third MOS device of the first conductivity type and a fourth MOS device of the second conductivity type.
  • a tensile stress is applied to a channel of one of the first and second MOS devices, and a compressive stress is applied to the other of the first and second MOS devices. If stress is applied to channels of the MOS device in the second area, the stress applied to the channels of the MOS devices in the second area is removed.
  • the method further comprises epitaxially growing a semiconductor layer in source/drain regions and on a gate of one of the first and second MOS devices, such that a compressive stress is applied to the one of the first and second MOS devices.
  • a stress control layer is formed over the other of the first and second MOS devices such that a tensile stress is applied to the other of the first and second MOS devices.
  • a first stress control layer is formed over one of the first and second MOS devices, the first stress control layer applying a tensile stress to the one of the first and second MOS devices.
  • the first stress control layer comprises at least one of SiN, SiON and SiO 2 .
  • a second stress control layer can be formed over the other of the first and second MOS devices, the second stress control layer applying a compressive stress to the other of the first and second MOS devices.
  • the second stress control layer comprises at least one of SiN and SiO 2 .
  • the invention is directed to a circuit.
  • the circuit includes a first MOS device of a first conductivity type in a first area of the circuit and a second MOS device of the first conductivity type in a second area of the circuit. A stress is applied to a channel of the first MOS device and a stress is not applied to the channel of the second MOS device.
  • a stress control layer is formed on the first MOS device, the stress control layer applying the stress to the first MOS device.
  • the stress control layer comprises ions implanted into the stress control layer.
  • the stress control layer comprises SiN.
  • the stress control layer comprises SiON.
  • the stress control layer comprises SiO 2 .
  • the stress is a compressive stress.
  • the stress is a tensile stress.
  • the circuit further comprises a second phase silicide in proximity to a source/drain structure of the first MOS device.
  • the invention is directed to a circuit.
  • the circuit comprises a first CMOS device in a first area of the circuit, the first CMOS device comprising a first MOS device of a first conductivity type and a second MOS device of a second conductivity type.
  • a second CMOS device in a second area of the circuit comprises a third MOS device of the first conductivity type and a fourth MOS device of the second conductivity type.
  • a tensile stress is applied to a channel of one of the first and second MOS devices, and a compressive stress is applied to the other of the first and second MOS devices.
  • the circuit further comprises an epitaxially grown semiconductor layer in source/drain regions and on a gate of one of the first and second MOS devices, such that a compressive stress is applied to the one of the first and second MOS devices.
  • the circuit further comprises a stress control layer over the other of the first and second MOS devices such that a tensile stress is applied to the other of the first and second MOS devices.
  • the circuit further comprises a first stress control layer over one of the first and second MOS devices, the first stress control layer applying a tensile stress to the one of the first and second MOS devices.
  • the first stress control layer comprises at least one of SiN, SiON and SiO 2 .
  • the circuit further comprises a second stress control layer over the other of the first and second MOS devices, the second stress control layer applying a compressive stress to the other of the first and second MOS devices.
  • the second stress control layer can include at least one of SiN and SiO 2 .
  • FIG. 1 is a schematic cross-sectional view of a MOS device illustrating an approach to introducing mechanical stress to improve carrier mobility in the device.
  • FIGS. 2A and 2B are graphs illustrating the relationship between stress engineering in a MOS device and noise.
  • FIG. 3 contains a flow chart illustrating one approach to forming a device in accordance with the invention in which stress engineering is selectively applied to one or more selected portions of the device to enhance device performance while reducing the effects of noise on the device.
  • FIG. 4 contains a flow chart illustrating another approach to forming a device in accordance with the invention in which stress engineering is selectively applied to one or more selected portions of the device to enhance device performance while reducing the effects of noise on the device.
  • FIG. 5 contains a flow chart illustrating another approach to forming a device in accordance with the invention in which stress engineering is selectively applied to one or more selected portions of the device to enhance device performance while reducing the effects of noise on the device.
  • FIGS. 6 through 8 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the invention.
  • FIGS. 9 and 10 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • FIGS. 11 through 13 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • FIGS. 14 through 16 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • FIGS. 17 through 20 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • FIGS. 21 through 27 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • FIGS. 28 through 31 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • FIG. 32 contains a schematic cross-sectional view illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • a semiconductor device such as an LSI device having mixed-signal applications, i.e., analog and digital applications, a layout of the semiconductor device and an approach to manufacturing the device, in which tensile and/or compressive stress are selectively applied to different portions of the device, i.e., analog and digital portions, are provided to enhance performance of the device and simultaneously reduce the effects of flicker noise on the performance of the device.
  • FIGS. 3 through 5 contain flow charts which illustrate the three categories, respectively, of the embodiments of the invention. These categories are not to be construed as limiting the invention in any way. They are defined only for the purposes of clarity of the description and ease of understanding of the invention.
  • FIG. 3 contains a flow chart illustrating one approach to forming a device in accordance with the invention in which stress engineering is selectively applied to one or more selected portions of the device to enhance device performance while reducing the effects of noise on the device.
  • FIG. 3 illustrates the first category of embodiments of the invention.
  • a first MOS device of a first conductivity type i.e., n-type or p-type
  • a first area of a device for example a digital area, i.e., an area of the device in which digital circuits are being formed.
  • a second MOS device of the first conductivity type i.e., n-type or p-type
  • Stress engineering is applied to selectively apply a local stress to the channels of the first and second MOS devices in the first and second areas in step 54 .
  • stress is released or relieved in the channel of the second MOS device in the second area.
  • the above approach results in stress being applied only to the channel of the first MOS device.
  • the first MOS device with the stress applied will have the enhanced performance characteristics resulting from the applied stress, but it may also have increased noise.
  • the second MOS device will not have local stress applied, resulting in a circuit with reduced effects due to flicker noise.
  • This approach can be applied in situations such as where the first area contains circuits which are less sensitive to noise than those in the second area.
  • the first area may include digital circuits, circuits for low-voltage operation and/or noise insensitive circuits
  • the second area may include analog circuits, circuits for high-voltage operation and/or noise-sensitive circuits.
  • the local stress can be applied by forming a stress control layer in both the first and second area.
  • ion implantation can be used, or the portion of the stress control layer on the second MOS device can be removed.
  • FIG. 4 contains a flow chart illustrating another approach to forming a device in accordance with the invention in which stress engineering is selectively applied to one or more selected portions of the device to enhance device performance while reducing the effects of noise on the device.
  • FIG. 4 illustrates the second category of embodiments of the invention.
  • a first MOS device of a first conductivity type i.e., n-type or p-type
  • a first area of a device for example a digital area, i.e., an area of the device in which digital circuits are being formed.
  • a second MOS device of the first conductivity type i.e., n-type or p-type
  • Stress engineering is applied to selectively apply a local stress to the channel of the first MOS device in the first area in step 64 .
  • the above approach results in stress being applied only to the channel of the first MOS device.
  • the first MOS device with the stress applied will have the enhanced performance characteristics resulting from the applied stress, but it may also have increased noise.
  • the second MOS device will not have local stress applied, resulting in a circuit with reduced effects due to flicker noise.
  • This approach can be applied in situations such as where the first area contains circuits which are less sensitive to noise than those in the second area.
  • the first area may include digital circuits, circuits for low-voltage operation and/or noise insensitive circuits
  • the second area may include analog circuits, circuits for high-voltage operation and/or noise-sensitive circuits.
  • FIG. 5 contains a flow chart illustrating another approach to forming a device in accordance with the invention in which stress engineering is selectively applied to one or more selected portions of the device to enhance device performance while reducing the effects of noise on the device.
  • FIG. 5 illustrates the third category of embodiments of the invention.
  • a first CMOS device which includes a first MOS device of a first conductivity type, i.e., n-type or p-type, and a second MOS device of a second conductivity type, i.e., p-type or n-type, is formed in a first area of a device, for example a digital area, i.e., an area of the device in which digital circuits are being formed.
  • a second CMOS device which includes a first (third) MOS device of the first conductivity type, i.e., n-type or p-type, and a second (fourth) MOS device of a second conductivity type, i.e., p-type or n-type, is formed in a second area of the device, i.e., an area of the device in which analog circuits are formed.
  • Stress engineering is applied to selectively apply a local tensile stress and a local compressive stress to at least the channels of the first and second MOS devices in the first CMOS device in step 68 .
  • stress is released or relieved in the channels of the MOS devices of the second CMOS device.
  • the above approach results in stress being applied only to the channels of the first and/or second MOS devices of the first CMOS device.
  • the first CMOS device with the stress applied will have the enhanced performance characteristics resulting from the applied stress, but it may also have increased noise.
  • the second CMOS device will not have local stress applied, resulting in a circuit with reduced effects due to flicker noise.
  • This approach can be applied in situations such as where the first area contains circuits which are less sensitive to noise than those in the second area.
  • the first area may include digital circuits, circuits for low-voltage operation and/or noise insensitive circuits
  • the second area may include analog circuits, circuits for high-voltage operation and/or noise-sensitive circuits.
  • FIGS. 6 through 8 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the invention. This embodiment is of the type defined within the first category of embodiments described above.
  • a substrate 100 made of, for example, silicon.
  • the device includes a digital circuit area and an analog circuit area.
  • Each of the digital circuit area and the analog circuit area includes a first NMOS transistor and a first PMOS transistor.
  • a shallow trench isolation (STI) 102 is formed in the substrate 100 to isolate the devices.
  • Each of the transistors includes source/drain regions 128 , each of which includes a lightly-doped source/drain region 122 and a heavily-doped source/drain region 126 .
  • a gate dielectric layer pattern 110 is formed on the substrate for each transistor.
  • a conductive gate pattern 120 is formed on a respective gate dielectric layer pattern 110 for each transistor, and a silicide layer pattern 130 is formed over each of the conductive gate patterns 120 and over exposed portions of the source/drain regions 128 , specifically, over portions of the heavily-doped source/drain regions 126 .
  • the silicide layer patterns can be formed of, for example, cobalt silicide, nickel silicide, titanium silicide, or tungsten silicide.
  • Sidewall spacers 124 are formed on the sides of all of the gate structures, including the gate dielectric layer patterns 110 , the conductive gate patterns 120 and the silicide layer patterns 130 . In one embodiment, it is desirable that, in the analog circuit area, the distance between the transistor gate structure and the STI 102 , i.e., d 1 , d 2 , d 3 , d 4 , be more than 1.5 um.
  • a stress control layer 150 is formed over the structure.
  • the stress control layer 150 applies a compressive stress to the channels 104 a , 104 b , 104 c , 104 d of the transistors, as indicated by the arrows in the figure.
  • the stress control layer 150 can be a layer of silicon nitride (SiN) deposited to a thickness of about 20-150 nm by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • a silicon nitride layer formed under a low temperature condition of 200-400 degrees C., or a silicon oxide layer with a compressive stress can also be used.
  • the compressive stress is selectively released over the NMOS transistor of the digital circuit area and both of the transistors of the analog circuit area.
  • a photoresist mask 160 is formed to cover only the PMOS transistor of the digital circuit area. Ions such as genmanium, silicon, arsenic, indium, antimony, etc., ions are implanted, as indicted by 162 , into the stress control layer 150 , using the photoresist 160 as an ion implantation mask. In one embodiment, it is desirable that the ion implant energy be controlled within the range of 20-100 KeV, with consideration given to the thickness of the stress control layer 150 , such that the implant ions are substantially prevented from being implanted into the silicide layer patterns 130 .
  • the stress control layer 150 is converted into a stress release or relax layer 152 everywhere except over the PMOS transistor in the digital circuit area. Therefore, compressive stress remains applied only to the channel 104 b of the PMOS transistor in the digital circuit area. As a result, performance is improved in the PMOS transistor in the digital circuit area. No stress is remaining on the NMOS transistor in the digital circuit area and on both transistors in the analog circuit area, such that the flicker noise characteristics of those devices is not degraded. That is, in this embodiment, a PECVD silicon nitride stress control layer is used to enhance performance of only a PMOS device in the digital circuit area.
  • FIGS. 9 and 10 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention. This embodiment is of the type defined within the first category of embodiments described above.
  • the formation of the portion of the device including the substrate 100 , STI 102 , source/drain regions 128 , gate dielectric patterns 110 , conductive gate patterns 120 , silicide patterns 130 and sidewall spacers 124 is the same as that of the embodiment of FIGS. 6 through 8 . Accordingly, description thereof will not be repeated.
  • a stress control layer 250 which applies a tensile stress, is formed on the structure.
  • the stress control layer 250 can be a silicon nitride layer formed to a thickness of about 20-150 nm by low pressure chemical vapor deposition (LPCVD).
  • LPCVD low pressure chemical vapor deposition
  • the stress control layer 250 can be formed by forming a silicon nitride layer under a high-temperature condition of 400-800 degrees C.
  • the stress control layer 250 can also be formed by forming a silicon oxynitride (SiON) layer by PECVD followed by an annealing step.
  • the stress control layer 250 can be a silicon oxide layer which applies a tensile stress. The resulting tensile stress is locally imposed on the channels 204 a , 204 b , 204 c , 204 d of the transistors, as indicated in FIG. 9 by the arrows.
  • the tensile stress is selectively released over the PMOS transistor of the digital circuit area and both of the transistors of the analog circuit area.
  • a photoresist mask 260 is formed to cover only the NMOS transistor of the digital circuit area. Ions such as germanium, silicon, arsenic, indium, antimony, etc., ions are implanted, as indicted by 262 , into the stress control layer 150 , using the photoresist 260 as an ion implantation mask.
  • the ion implant energy be controlled within the range of 20-100 KeV, with consideration given to the thickness of the stress control layer 250 , such that the implant ions are substantially prevented from being implanted into the silicide layer patterns 130 .
  • the stress control layer 250 is converted into a stress release or relax layer 252 everywhere except over the NMOS transistor in the digital circuit area. Therefore, tensile stress remains applied only to the channel 204 a of the NMOS transistor in the digital circuit area. As a result, performance is improved in the NMOS transistor in the digital circuit area. No stress is remaining on the PMOS transistor in the digital circuit area and on both transistors in the analog circuit area, such that the flicker noise characteristics of those devices is not degraded. That is, in one embodiment, a LPCVD silicon nitride stress control layer is used to enhance performance of only an NMOS device in the digital circuit area.
  • FIGS. 11 through 13 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention. This embodiment is of the type defined within the second category of embodiments described above.
  • the formation of the portion of the device including the substrate 100 , STI 102 , source/drain regions 128 , gate dielectric patterns 110 , conductive gate patterns 120 , silicide patterns 130 and sidewall spacers 124 is the same as that of the embodiment of FIGS. 6 through 8 . Accordingly, description thereof will not be repeated.
  • a stress control layer 350 which applies no initial net stress, is formed on the structure.
  • the stress control layer 350 can be a silicon oxynitride layer formed to a thickness of about 20-150 nm by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • a photoresist pattern 360 is formed and patterned such that it remains only over the NMOS transistor in the digital circuit area.
  • the stress control layer 350 is removed everywhere except over the NMOS transistor in the digital circuit area.
  • the photoresist pattern 360 is removed, and the remaining portion of the stress control layer is annealed.
  • the stress control layer 350 is converted into a tensile stress layer 352 , which applies a tensile stress to the channel 304 a of the NMOS transistor in the digital circuit area as shown by the arrows in the figure.
  • the remaining transistor channels 304 b , 304 c , 304 d have no stress applied, due to the absence of the tensile stress layer 352 in their respective transistor regions.
  • tensile stress is locally imposed on the channel 304 a of the NMOS transistor in the digital circuit area.
  • performance is improved in the NMOS transistor in the digital circuit area.
  • No stress is applied to the PMOS transistor in the digital circuit area or on both transistors in the analog circuit area, such that the flicker noise characteristics of those devices is not degraded.
  • an annealed PECVD silicon oxynitride layer which has a tensile stress, is used to enhance performance of only an NMOS device in the digital circuit area.
  • FIGS. 14 through 16 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention. This embodiment is of the type defined within the second category of embodiments described above.
  • the formation of the portion of the device including the substrate 100 , STI 102 , source/drain regions 128 , gate dielectric patterns 110 , conductive gate patterns 120 and sidewall spacers 124 is the same as that of the embodiment of FIGS. 6 through 8 . Accordingly, description thereof will not be repeated.
  • an annealed PECVD layer of silicon dioxide SiO 2 which has a tensile stress, is formed to enhance NMOS performance.
  • a SiO 2 layer 450 is formed on the structure.
  • the SiO 2 layer 450 can be formed to a thickness of about 20-100 nm by plasma enhanced chemical vapor deposition (PECVD) at a temperature below about 600 degrees C.
  • PECVD plasma enhanced chemical vapor deposition
  • the portion of the SiO 2 layer on the NMOS transistor of the analog circuit area is removed.
  • the SiO 2 layer is annealed at a temperature of 900-1150 degrees C. to introduce a tensile stress in the SiO 2 layer and, therefore in the NMOS transistor of the digital circuit area. It is noted that the SiO 2 layer is removed from the NMOS transistor in the analog circuit area because it is desired to prevent stress from being applied to that transistor.
  • the portion of the SiO 2 layer over the PMOS transistors need not be removed because the annealing of the SiO 2 layer will not affect the PMOS transistors.
  • the remaining portion of the SiO 2 layer can be removed to permit subsequent process steps, such as silicidation of the source/drain regions of the device. It should be noted that the remaining portion of the SiO 2 layer need not be removed.
  • the compressive stress in the gate 120 and the tensile stress in the channel 404 a will be maintained, whether the SiO 2 layer is completely removed or it remains on the NMOS transistor in the digital circuit area.
  • tensile stress is locally imposed on the channel 404 a of the NMOS transistor in the digital circuit area and compressive stress is applied to its gate.
  • performance is improved in the NMOS transistor in the digital circuit area.
  • No stress is applied to the PMOS transistor in the digital circuit area or on both transistors in the analog circuit area, such that the flicker noise characteristics of those devices is not degraded.
  • the heat budget for source/drain activation can be used to induce tensile stress without introducing an additional high-temperature anneal process.
  • FIGS. 17 through 20 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • This embodiment is of the type defined within the second category of embodiments described above.
  • a silicidation process is used to enhance performance of an NMOS transistor.
  • the formation of the portion of the device including the substrate 100 , STI 102 , source/drain regions 128 , gate dielectric patterns 110 , conductive gate patterns 120 and sidewall spacers 124 is the same as that of the embodiment of FIGS. 6 through 8 . Accordingly, description thereof will not be repeated.
  • silicide patterns 830 are shown instead of the silicide patterns 130 . In this embodiment, it is these silicide patterns 830 , as described below, that enhance the NMOS performance.
  • the silicide patterns 830 are formed by depositing a metal layer pattern on the structure where the silicide patterns 830 are to be formed, i.e., on the silicon of the source/drain regions 128 and conductive gate 120 .
  • the metal can be, for example, cobalt.
  • a first rapid thermal annealing (RTA) process is carried out at approximately 450 degrees C. to form patterns of cobalt monosiliside CoSi 830 . That is, a first phase metal silicide is formed by a first heat treatment. After the first RTA is performed, the remaining cobalt is removed.
  • a capping layer 840 is formed over the structure after the first RTA is performed.
  • the capping layer 840 can be a layer of titanium nitride TiN formed to a thickness of about 5-20 nm.
  • a photoresist pattern 860 is formed over the structure such that only the portion of the capping layer 840 that is formed over the NMOS transistor in the digital circuit area is exposed. Then, that exposed portion of the capping layer 840 is removed. Next, a second RTA process is carried out at a temperature of about 700-1100 degrees C. As a result of the second RTA process, the silicidation patterns 830 transition to a second phase metal silicide, for example, the CoSi transitions to cobalt disilicide CoSi 2 . This results in formation of new silicide patterns 830 a on the gates and source/drain regions.
  • a tensile stress is imposed on the channel 804 a of the NMOS transistor in the digital circuit area. Relatively little or no tensile stress is applied to the other channels 804 b , 804 c , 804 d because the capping layer 840 over their respective transistors acts to attenuate stress.
  • tensile stress is locally imposed on the channel 804 a of the NMOS transistor in the digital circuit area, but the channels 804 b , 804 c , 804 d of the remaining transistors are not affected by the annealing because there is present on the transistors a capping layer 840 for stress attenuation.
  • the remainder of the capping layer 840 is removed.
  • the result is a device with silicide layers 830 a which apply a tensile stress to the channel 804 a of the NMOS transistor in the digital circuit area and which do not apply a stress to the remaining transistors.
  • FIGS. 21 through 27 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • This embodiment is of the type defined within the third category of embodiments described above.
  • an epitaxially grown source/drain structure is used to induce compressive stress on a PMOS transistor to enhance performance of the PMOS transistor.
  • CMOS structures each including an NMOS transistor and a PMOS transistor, are formed in both a digital circuit area and an analog circuit area of a device.
  • the device includes a digital circuit area and an analog circuit area.
  • Each of the digital circuit area and the analog circuit area includes a first NMOS transistor and a first PMOS transistor.
  • a substrate 100 made of, for example, silicon, is provided.
  • a shallow trench isolation (STI) 102 is formed in the substrate 100 to isolate the devices.
  • Each of the transistors includes source/drain regions 128 , each of which includes a lightly-doped source/drain region 122 and a heavily-doped source/drain region 126 .
  • a gate dielectric layer pattern 110 is formed on the substrate for each transistor.
  • a conductive gate pattern 120 is formed on a respective gate dielectric layer pattern 110 for each transistor, and sidewall spacers 124 are formed on the sides of all of the gate structures, including the gate dielectric layer patterns 110 and the conductive gate patterns 120 .
  • a mask layer 510 is formed over the structure of FIG. 21 .
  • the mask layer can be made of, for example, silicon dioxide, silicon nitride, or other similar material.
  • the portion of the mask layer 510 that is over the PMOS transistor in the digital circuit area is at least partially removed, leaving a small portion of the mask layer 510 on the sidewall spacer 124 . Then, a portion of the source/drain region 128 of the exposed PMOS transistor is removed beside its gate structure by a self-aligned, vertical, anisotropic etching. As a result, a groove 520 is formed to have a depth of about 10-100 nm.
  • a semiconductor layer 522 is selectively and epitaxially grown on the groove 520 and the top of the conductive gate 120 .
  • the epitaxial layer 522 can be SiGe, SiC, or other such material.
  • the layer 522 imposes compressive stress on the channel 504 b of the PMOS transistor in the digital circuit area, as indicated by the arrows in the figure. This compressive stress is due to the larger lattice constant of the epitaxially grown semiconductor layer 522 .
  • the material with the larger lattice constant exerts pressure on the material of the channel 504 b , resulting in the compressive stress in the channel 504 b . That is, the epitaxially grown semiconductor layer 522 and the substrate 100 have different crystal lattice structures and/or different thermal expansion coefficients, which produces a mechanical stress in the channel of the transistor, thereby affecting the mobility of carriers in the channel.
  • metal silicide layers 530 which can be nickel silicide, cobalt silicide, or other similar material, are formed on the gate conductive patterns 120 and exposed source/drain regions 128 , and on top of the epitaxially grown semiconductor layer 522 in the PMOS transistor in the digital circuit area.
  • a stress control layer 550 having a tensile stress, is formed on the structure.
  • the stress control layer 550 can be a silicon nitride layer formed to a thickness of about 20-150 nm by LPCVD.
  • the stress control layer 550 can be a silicon nitride layer formed under a high-temperature condition of 400-800 degrees C.
  • the stress control layer 550 can be an annealed SiON layer formed by PECVD, or a tensile stress silicon oxide layer. As a result, tensile stress is locally imposed on the channels 504 a , 504 b , 504 c , 504 d.
  • the tensile stress is selectively released in the PMOS transistor in the digital circuit area and both of the transistors of the analog circuit area.
  • a photoresist mask pattern 560 is formed over the NMOS transistor in the digital circuit area.
  • ions such as germanium, silicon, arsenic, indium, antimony, or other similar ions are implanted into the structure everywhere except in the NMOS transistor in the digital circuit area.
  • the tensile stress is released in the PMOS transistor in the digital circuit area and in both transistors in the analog circuit area.
  • FIGS. 28 through 31 contain schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention.
  • This embodiment is of the type defined within the third category of embodiments described above.
  • a tensile and a compressive layer are separately formed to induce stress in both the NMOS and PMOS transistors in the digital circuit area.
  • the formation of the portion of the device including the substrate 100 , STI 102 , source/drain regions 128 , gate dielectric patterns 110 , conductive gate patterns 120 , silicide patterns 130 and sidewall spacers 124 is the same as that of the embodiment of FIGS. 6 through 8 . Accordingly, description thereof will not be repeated.
  • a first stress control layer 650 which has a tensile stress, is formed over the structure.
  • the first stress control layer 650 can be a silicon nitride layer formed to a thickness of about 20-150 nm by LPCVD.
  • the layer 650 can be a silicon nitride layer formed under a high-temperature condition of 400-800 degrees C.
  • the layer 650 can be an annealed SiON layer formed by PECVD, or a silicon oxide layer with tensile stress.
  • tensile stress is locally imposed on the channels 604 a , 604 b , 604 c , 604 d of the transistors in both the digital circuit area and the analog circuit area, as indicated by the arrows in the figure.
  • the portion of the first stress control layer 650 over the PMOS transistor in the digital circuit area and over both transistors in the analog circuit area is removed.
  • a photoresist pattern 654 is formed to cover only the NMOS transistor in the digital circuit area, and the exposed portion of the first stress control layer 650 is removed.
  • a PECVD SiON layer is used as the first stress control layer 650 , then it is desirable that the annealing process be carried out after selectively removing the first stress control layer 650 from the PMOS transistor in the digital circuit area and the transistors in the analog circuit area.
  • a tensile stress remains applied to only the channel 604 a of the NMOS transistor in the digital circuit area, as shown by the arrows in the figure.
  • a second stress control layer 660 which has a compressive stress, is formed over the structure.
  • the second stress control layer 660 can be, for example, a layer of silicon nitride formed to a thickness of about 20-150 nm by PECVD.
  • the second stress control layer 660 can be a silicon nitride layer formed under a low-temperature condition of 200-400 degrees C.
  • the second stress control layer 660 can alternatively be a silicon oxide layer with a compressive stress.
  • a compressive stress is applied to all of the channels 604 a , 604 b , 604 c , 604 d , and the channel 604 a has both a compressive stress and a tensile stress applied, as shown by the arrows in the figure.
  • the second stress control layer 660 is selectively converted to a stress release or relax layer 662 over all of the transistors except the PMOS transistor in the digital circuit area.
  • a photoresist mask pattern 670 is formed over only the PMOS transistor in the digital circuit area.
  • Ions such as germanium, silicon, arsenic, indium, antimony, or other similar ions, are implanted, indicated by 672 , into the second stress control layer 660 , except in the portion of the second stress control layer 660 that covers the PMOS transistor in the digital circuit area.
  • the ion implantation releases the compressive stress in the exposed portion of the second stress control layer 660 , such that the exposed portion of the second stress control layer becomes the stress release or relax layer 662 .
  • FIG. 32 contains a schematic cross-sectional views illustrating a method of forming a semiconductor device in accordance with another embodiment of the invention. This embodiment is of the type defined within the third category of embodiments described above.
  • the embodiment of FIG. 32 is a variation of that of FIGS. 28 through 31 .
  • the steps shown in FIGS. 28 through 30 are also used in the embodiment of FIG. 32 . Accordingly, description of those steps will not be repeated.
  • the second stress control layer 660 having a compressive stress is formed, the second stress control layer 660 is removed everywhere except over the PMOS transistor in the digital circuit area.
  • tensile stress is locally imposed on the channel 704 a of the NMOS transistor in the digital circuit area, and compressive stress is locally imposed on the channel 704 b of the PMOS transistor in the digital circuit area, as indicated by the arrows in the figure.
  • stress engineering is selectively applied to particular devices depending on their required operational configurations. That is, the appropriate stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc.
  • the present invention is applicable to circuits which include digital, analog and mixed-mode functions.
  • the invention is applicable to memory LSI, such as DRAM and embedded DRAM.
  • the approach of the invention is applicable to the DRAM cell and/or the DRAM sense amplifier, which is considered to be a noise-sensitive analog circuit.
  • the invention is applicable to other circuits such as the sense amplifier circuit of memory circuits in discrete memory chip or embedded memory chip configurations of, for example, SRAM, flash memory, MRAM, PRAM, and other such devices.
  • the invention is particularly applicable to these circuits because the sense amplifiers in these circuits are required to sense very small differences in currents, and, therefore, noise such as flicker noise can substantially degrade their performance.

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US14/337,532 US9093306B2 (en) 2004-03-30 2014-07-22 Low noise and high performance LSI device
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