US5604696A - Stacked capacitor type semiconductor memory device with good flatness characteristics - Google Patents

Stacked capacitor type semiconductor memory device with good flatness characteristics Download PDF

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US5604696A
US5604696A US08/506,979 US50697995A US5604696A US 5604696 A US5604696 A US 5604696A US 50697995 A US50697995 A US 50697995A US 5604696 A US5604696 A US 5604696A
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capacitor
insulating layer
electrode layer
semiconductor substrate
layer formed
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Yoshihiro Takaishi
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NEC Electronics Corp
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NEC Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor

Definitions

  • the present invention relates to a stacked capacitor used in a memory cell of a dynamic random access memory (DRAM) device.
  • DRAM dynamic random access memory
  • each memory cell is constructed by a MOS transistor and a capacitor.
  • a stacked capacitor which has lower and upper electrodes and an insulating layer therebetween, has been used as such a capacitor. Since the stacked capacitor is three-dimensional, the capacitance thereof can be increased, to thereby enhance the integration of the DRAM device.
  • an insulating layer is formed on a semiconductor substrate.
  • a capacitor electrode layer is formed on the insulating layer and is electrically connected via a contact hole of the insulating layer to an impurity doped region of the semiconductor substrate.
  • a capacitor insulating layer is formed on the capacitor lower electrode layer, and a capacitor upper electrode layer is formed on the capacitor insulating layer. This will be explained later in detail.
  • a step between a memory cell array area and a peripheral circuit area is so large that it is difficult to arrange wiring patterns around an interface between the memory cell array area and the peripheral circuit area.
  • the depth of focus of an exposure system used in a lithography process is reduced, so that a fine pattern cannot be formed on such a step.
  • Another object is to provide a highly integrated stacked capacitor type semiconductor device.
  • first and second insulating layers are formed on a memory cell array area and a peripheral circuit area of a semiconductor substrate.
  • a plurality of openings are formed in the second insulating layer on the memory cell array area.
  • Stacked capacitors are buried in the openings, and are electrically connected via contact holes of the first insulating layer to impurity doped regions of the semiconductor substrate.
  • first and second insulating layers are formed on a memory cell array area and a peripheral circuit area of a semiconductor substrate.
  • a groove is formed in the second insulating layer, so that the second insulating layer in the memory cell array area is divided into a plurality of islands.
  • Stacked capacitors are formed on the islands, and are electrically connected via contact holes of the second insulating layer and contact holes of the first insulating layer to impurity doped regions of the semiconductor substrate.
  • FIG. 1 is a cross-sectional view illustrating a prior art DRAM deice
  • FIG. 2 is a cross-sectional view illustrating a first embodiment of the DRAM device according to the present invention
  • FIG. 3 is a traverse cross-sectional view of the capacitor lower electrode layer and the capacitor upper electrode layer of FIG. 2;
  • FIG. 4A through 4I are cross-sectional views for explaining the manufacturing steps of the device of FIG. 2;
  • FIG. 5 is a cross-sectional view illustrating a second embodiment of the DRAM device according to the present invention.
  • FIG. 6 is a traverse cross-sectional view of the capacitor lower electrode layer and the capacitor upper electrode layer of FIG. 5;
  • FIGS. 7A through 7M are cross-sectional views for explaining the manufacturing steps of the device of FIG. 5;
  • FIG. 8 is a cross-sectional view illustrating a modification of the device of FIG. 5;
  • FIG. 9 is a cross-sectional view illustrating a third embodiment of the DRAM device according to the present invention.
  • FIG. 10 is a traverse cross-sectional view of the capacitor lower electrode layer and the capacitor upper electrode layer of FIG. 9;
  • FIGS. 11A through 11I are cross-sectional views for explaining the manufacturing steps of the device of FIG. 9;
  • FIG. 12 is a cross-sectional view illustrating a modification of the device of FIG. 9;
  • FIG. 13 is a cross-sectional view illustrating a fourth embodiment of the DRAM device according to the present invention.
  • FIGS. 14A through 14K are cross-sectional views for explaining the manufacturing steps of the device of FIG. 13.
  • FIG. 15 is a cross-sectional view illustrating a modification of the device of FIG. 13.
  • X designates a memory cell array area
  • Y designates a peripheral circuit area for address buffers, address decoders sense amplifiers and the like.
  • a thick field silicon oxide layer 2 is formed for isolating elements from eack other.
  • gate thin silicon oxide layers 3 and gate electrode layers 4 are formed thereon.
  • N + -type impurity doped regions 5-1 through 5--5 are formed within the silicon substrate 1.
  • the region 5-1 is a drain region of a MOS transistor or so-called cell transistor for connection of a bit line
  • the region 5-2 is for a source region of the cell transistor
  • the regions 5-3 and 5-4 are for source and drain regions of a transistor of the peripheral circuit area Y.
  • a silicon oxide layer 6 is formed on the gate electrode layers 3, and is flattened by using a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • a contact hole CONT1 is perforated in the silicon oxide layer 6, and a conductive layer 7 is deposited by a chemical vapor deposition (CVD) process thereon.
  • CVD chemical vapor deposition
  • the conductive layer 7 is also buried in the contact hole CONT1, and the conductive layer 7 is patterned to form one bit line.
  • the conductive layer 7 is made of phosphorus or arsenic including polycrystalline silicon or high melting temperature metal such as Ti and W.
  • an insulating layer 8 is formed thereon.
  • the insulating layers 6 and 8 are patterned to form contact holes CONT2 therein.
  • capacitor lower electrode layers 9 are formed thereon, and are connected via the contact holes CONT2 to the impurity doped regions 5-2.
  • a capacitor insulating layer 10 and a capacitor upper electrode layer 11 which is called a cell plate made of laminated titanium nitride (TiN) and W are formed commonly for the memory cells.
  • first wiring layers 13 made of aluminum are formed by using a sputtering process.
  • second wiring layers are formed.
  • the height of the capacitor lower electrode layers 9 has to be increased, i.e., the aspect ratio of the capacitor lower electrode layers 9 has to be increased.
  • an area per one memory cell is about 0.5 to 0.6 ⁇ m 2 and the capacitance thereof should be more than 30 fF in accordance with the memory cell reduction rule. Therefore, if the capacitor insulating layer 10 is equivalent to a 4 nm thick silicon oxide layer, the height of the capacitor lower eletrode layers 9 should be approximately 1 ⁇ m.
  • a step S between the memory cell array area X and the peripheral circuit area Y is so large, for example, 1 ⁇ m, that it is impossible to form the first wiring layers 13 and the second wiring layers around the interface between the memory cell array area X and the peripheral circuit area Y due to the reduced depth of focus of an exposure system used in a lithograply process.
  • FIG. 2 which illustrates a first embodiment of the present invention
  • an about 500 to 1000 nm thick insulating layer 21 made of silicon oxide is formed on the insulating layer 8.
  • a plurality of openings are perforated in the insulating layer 21, and stacked capacitors are buried in the openings, that is, a capacitor lower electrode layer 22 is formed within each of the openings.
  • the capacitor lower electrode layer 22 is made of phosphorus or arsenic doped polycrystalline silicon or high melting temperature metal such as TiN.
  • the capacitor lower electrode layer 22 is electrically connected via the contact hole CONT2 to the impurity doped region 5-2.
  • a capacitor insulating layer 23 and a capacitor upper electrode layer 24 made of laminated TiN and W are formed commonly for the memory cells.
  • first wiring layers 26 made of aluminum are formed by using a sputtering process.
  • second wiring layers are formed.
  • a step S between the memory cell array area X and the peripheral circuit area Y is remarkably reduced.
  • the step S depends mainly upon the thickness of the capacitor upper electrode layer 24 which is less than 200 nm thick.
  • FIG. 3 which is a traverse cross-sectional view of the capacitor lower electrode layer 22 and the capacitor upper electrode layer 24 taken along the line at the middle of the openings of the insulating layer 21 of FIG. 2, a stacked capacitor is formed by the capacitor lower electrode layer 22, the capacitor upper electrode layer 24, and the capacitor insulating layer 23 therebetween, which are located within the opening of the insulating layer 21.
  • a thick field silicon oxide layer 2 is formed by using a local oxidation of silicon (LOCOS) process in a P - -type monocrystalline silicon substrate 1.
  • LOC local oxidation of silicon
  • a gate thin silicon oxide layer 3 is formed by thermally oxidizing the silicon substrate 1, and a gate electrode layer 4 is formed by a CVD process thereon.
  • N + -type impurity doped regions 5-1 through 5-4 are formed by indroducing N-type impurity ions into the silicon substrate 1 with a mask of the field silicon oxide layer 2 and the gate electrode layer 4.
  • a silicon oxide layer 6 is formed by a CVD process and is flattened by a CMP process.
  • a contact hole CONT1 is perforated in the silicon oxide layer 6.
  • a conductive layer 7 made of phosphorus or arsenic doped polycrystalline silicon or high melting temperature metal such as Ti and W is formed by a CVD process, to form one bit line.
  • the conductive layer 7 is electrically connected via the contact hole CONT1 to the impurity doped region 5-1.
  • an insulating layer 8 is formed thereon by a CVD process.
  • the insulating layer 8 is made of silicon oxide including an excess of 2 to 12 at % silicon, which is called a silicon rich oxide (SRO) layer.
  • contact holes CONT2 are perforated in the insulating layer 8 and the silicon oxide layer 7.
  • a phosphorus doped polycrystalline silicon layer 22' is formed thereon by a CVD process.
  • the polycrystalline silicon layer 22' is flattened by a CMP process, so that the polycrystalline silicon layer 22' is buried in the contact holes CONT2, as shown in FIG. 4C.
  • an about 500 to 1000 nm thick insulating layer 21 made of silicon oxide is formed by a CVD process.
  • openings 21a are perforated in the insulating layer 21 by a reactive ion etching (RIE) process using a mixture gas of C 4 H 8 and CO.
  • RIE reactive ion etching
  • the etching rate of the insulating layer (SiO 2 ) 21 is remarkably larger than that of the insulating layer (SRO) 8, so that the insulating layer 8 is hardly etched.
  • the polycrystalline silicon layer 22' is hardly etched.
  • the excess silicon of the insulating layer (SRO) 8 is larger than 12 at %, the insulating characteristics are remarkable reduced, in other words, the resistance value is reduced by less than 1/100 as compared with silicon oxide. Therefore, the excess silicon of the insulting layer 8 is preferably about 2 to 12 at %.
  • a capacitor lower electrode layer 22 made of phosphorus doped polycrystalline silicon or high melting temperature metal such as TiN, Pt or W is formed by a CVD process or a sputtering process.
  • a core insulating layer 27 made of boron including phospho-silicated glass (BPSG) is formed by a CVD process.
  • the core insulating layer 27 is etched by fluoric hydrogen gas under a low pressure less than 100 Torr at a chamber temperature of about 200° C.
  • the etching rate of the core insulating layer (BPSG) 27 is remarkably larger than that of the insulating layer 21 by about 1000 times, so that the insulating layer 21 is hardly etched.
  • the capacitor lower electrode layer 22 is electrically connected via the contact hole CONT2 to the impurity doped region 5-2.
  • a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, strontium titanate (STO), barium strontium titanate (BST) or lead titanium zirconate (PZT) is formed.
  • a capacitor upper electrode layer 24 made of laminated TiN and W is formed by a sputtering process
  • the capacitor upper electrode layer 24 and the capacitor insulating layer 23 are patterned.
  • an insulating layer 25 and a first aluminum wiring layers 26 are formed to complete the device of FIG. 2.
  • FIG. 5 which illustrates a second embodiment of the present invention
  • another capacitor upper electrode layer 24a is formed on sidewalls of the openings of the insulating layer 21 of FIG. 2, and another capacitor insulating layer 23a is formed between the capacitor lower electrode layer 22 and the capacitor upper electrode layer 24a.
  • the capacitor upper electrode layer 24a is electrically connected via a contact hole CONT3 to the capacitor upper electrode layer 24.
  • FIG. 6 which is a traverse cross-sectional view of the capacitor lower electrode layer 22 and the capacitor upper electrode layer 24 (24a) taken along the line at the middle of the openings of the insulating layer 21 of FIG. 5, a stacked capacitor is formed not only by the capacitor lower electrode layer 22, the capacitor upper electrode layer 24, and the capacitor insulating layer 23 therebetween, but also by the capacitor lower electrode layer 22, the capacitor upper electrode layer 24a, and the capacitor insulating layer 23a therebetween. Also, the elements of the stacked capacitor are located within the opening of the insulting layer 21. Thus, the capacitance of the stacked capacitor is increased as compared with that in the first embodiment.
  • FIGS. 7A, 7B and 7C the same processes as shown in FIGS. 4A, 4B and 4C are carried out.
  • an about 500 to 1000 nm thick insulating layer 21 made of silicon oxide is formed by a CVD process. Then, an about 100 to 200 mn thick titanium nitride layer 31 is formed thereon, and thereafter, an about 100 nm thick silicon oxide layer 32 for a back-etching process is formed.
  • the silicon oxide layer 32 and the titanium nitride layer 31 are etched by an RIE process with a resist mask (not shown), Subsequently, openings 21a are perforated in the insulating layer 21 by this RIE process.
  • this RIE process uses a mixture gas of C 4 H 8 and CO. According to this RIE process, the etching rate of the insulating layer (SiO 2 ) 21 is remarkably larger than that of the insulating layer (SRO) 8, so that the insulating layer 8 is hardly etched. Also, the polycrystalline silicon layer 22' is hardly etched.
  • a titanium mitride layer 33 is again formed. Note that the thickness of the titanium nitride layer 33 is smaller than that of the titanium nitride layer 31.
  • the titanium nitride layer 33 is anisotropically etched back by an RIE process using a mixture gas of HBr and Cl 2 . As a result, as shown in FIG. 7G, the titanium nitride layer 33 is left on only the sidewalls of the openings 21a of the insulating layer 21.
  • the silicon oxide layer 32 is etched by using the same RIE process as shown in FIG. 7E.
  • the capacitor upper electrode layer 24a is formed by the layers 31 and 33.
  • a capacitor insulating layer 23a made of silicon nitride, or ferroelectrics such as tantalum oxide, STO, BST or RZT is formed by a CVD process.
  • a capacitor lower electrode layer 22 made of phosphorus doped polycrystalline silicon or high melting temperature metal such as TiN, Pt or W is formed by a CVD process or a sputtering process.
  • a core insulating layer 27 made of BPSG is formed by a CVD process.
  • the core insulating layer 27 is etched by fluoric hydrogen gas under a low pressure less than 100 Torr at a chamber temperature of about 200° C.
  • the etching rate of the core insulating layer (BPSG) 27 is remarkably larger than that of the insulating layer 21 by about 1000 times, so that the insulating layer 21 is hardly etched.
  • the capacitor lower electrode layer 22 is electrically connected via the contact hole CONT2 to the impurity doped region 5-2.
  • a contact holes CONT3 is perforated in the capacitor insulating layer 23a.
  • a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, STO, BST or PZT is formed.
  • a capacitor upper electrode layer 24 made of laminated TiN and W is formed by a sputtering process
  • an insulating layer 25 and a first aluminum wiring layers 26 are formed to complete the device of FIG. 5.
  • the capacitor upper electrode layer 22a is provided on only the sidewalls of the openings of the insulating layer 21. That is, the capacitor upper electrode layer 22a is not provided on the insulating layer 21. In this case, the capacitor upper electrode layer 22a is directly connected to the capacitor electrode layer 22.
  • a step S between the memory cell array area X and the peripheral circuit area Y is reduced as compared with the second embodiment as illustrated in FIG. 5.
  • the capacitance of the stacked capacitor is a little reduced as compared with the second embodiment as illustrated in FIG. 5.
  • the manufacture of the device of FIG. 8 is the same as that of the device of FIG. 5 except that the titanium nitride layer 31 and the silicon oxide layer 32 as shown in FIG. 7D are not formed.
  • FIG. 9 which illustrates a third embodiment of the present invention
  • an about 500 to 1000 nm thick insulating layer 21 made of silicon oxide is formed on the insulating layer 8.
  • a plurality of grooves such as rectangular grooves are perforated in the insulating layer 21, so that a plurality of insulating islands 21' are formed in the memory cell array area X.
  • Stacked capacitors are formed on the insulating islands 21'. That is, a capacitor lower electrode layer 22 is formed on each of the insulating islands 21'.
  • the capacitor lower electrode layer 22 is made of phosphorus or arsenic doped polycrystalline silicon or high melting temperature metal such as TiN.
  • the capacitor lower electrode layer 22 is electrically connected via a contact hole CONT4 of the respective insulating island 21' and the contact hole CONT2 to the impurity doped region 5-2.
  • a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, STO, BST or PZT is formed on the capacitor lower electrode layer 22.
  • a capacitor upper electrode layer 24 made of laminated TiN and W are formed commonly for the memory cells.
  • an insulating layer 25 is formed thereon, and first wiring layers 26 made of aluminum are formed by using a sputtering process. Finally, another insulating layer and second wiring layers (not shown) are formed.
  • FIG. 10 which is a traverse cross-sectional view of the capacitor lower electrode layer 22 and the capacitor upper electrode layer 24 taken along the line at the middle of the insulating islands 21' of the insulating layer 21 of FIG. 9, a stacked capacitor is formed by the capacitor lower electrode layer 22, the capacitor upper electrode layer 24, and the capacitor insulating layer 23 therebetween.
  • FIGS. 11A, 11B and 11C the same processes as shown in FIGS. 4A, 4B and 4C are carried out.
  • an about 500 to 1000 nm thick insulating layer 21 made of silicon oxide is formed by a CVD process.
  • contact holes CONT4 are perforated in the insulating layer 21.
  • a phosphorus doped polycrystalline silicon layer 22" is buried in the contact holes CONT4 in the same way as the phosphorus doped polycrystalline silicon layer 22' buried in the contact holes CONT2.
  • an about 100 to 200 nm thick titanium nitride layer 41 is formed thereon, and thereafter, an about 100 nm thick silicon oxide layer 32 for a back-etching process is formed.
  • the silicon oxide layer 42 and the titanium nitride layer 41 are etched by an RIE process with a resist mask (not shown). Subsequently, grooves 2lb are perforated in the insulating layer 21 by this RIE process. As a result, insulating islands 21' are formed in the memory cell array X. Note that this RIE uses a mixture gas of C 4 H 8 and CO in the same way as in FIG. 4D. Therefore, the etching rate of the insulating layer (SiO 2 ) 21 is remarkably larger than that of the insulating layer (SRO) 8, so that the insulating layer 8 is hardly etched.
  • a titanium nitride layer 43 is again formed. Note that the thickness of the titanium nitride layer 43 is smaller than that of the titanium nitride layer 41.
  • the titanium nitride layer 43 is anisotropically etched back by an RIE process using a mixture gas of HBr and Cl 2 . As a result, as shown in FIG. 11G, the titanium nitride layer 43 is left on only the sidewalls of the insulating islands 21' of the insulating layer 21.
  • a capacitor lower electrode layer 22 is constructed by the layers 41 and 42.
  • a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, STO, BST or PZT is formed by a CVD process. Also, a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, STO or BST or PZT. Then, a capacitor upper electrode layer 24 made of laminated TiN and W is formed by a sputtering process.
  • the capacitor upper electrode layer 24 and the capacitor insulating layer 23 are patterned.
  • an insulating layer 25 and first aluminum wiring layers 26 are formed to complete the device of FIG. 9.
  • FIG. 12 which is a modification of the device of FIG. 9, the capacitor lower electrode layer 22 on the insulating layer 21 on the peripheral circuit area Y is not provided.
  • a step S between the memory cell array area X and the peripheral circuit area Y is reduced as compared with the third embodiment illustrated in FIG. 9.
  • the manufacture of the device of FIG. 12 is the same as that of FIG. 9 except that an RIE process using a resist pattern is added to remove the capacitor lower electrode 22 on the insulating layer 21 in FIG. 11G.
  • FIG. 13 which illustrates a fourth embodiment of the present invention
  • another capacitor upper electrode layer 24b is formed on insulating layer 8 of FIG. 9, and another capacitor insulating layer 23b is formed between another capacitor lower electrode layer 22b and the capacitor upper electrode layer 24b.
  • the capacitor upper electrode layer 24b is electrically connected to the capacitor upper electrode layer 24.
  • a step S between the memory cell array area X and the peripheral circuit area Y is remarkably reduced. Further, the capacitance of the stacked capacitor is increased as compared with that in the third embodiment.
  • the insulating layer 8 is made of silicon oxide and etching stopper material thereon.
  • a capactior upper 25 electrode layer 24b made of phosphorus doped polycrystalline silicon is formed by a CVD process.
  • a capacitor insulating layer 23b made of about 100 nm thick silicon nitride is formed by a CVD process, and thereafter, a capacitor lower electrode layer 22b made of about 100 nm thick titanium nitride is formed by a CVD process.
  • the capacitor lower electrode layer 22b, the capacitor insulating layer 23b and the capacitor upper electrode layer 24b are patterned.
  • an about 500 to 1000 nm thick insulating layer 21 made of silicon oxide is formed by a CVD process.
  • contact holes CONT4 are perforated in the insulating layer 21.
  • a phosphorus doped polycrystalline silicon layer 22" is buried in the contact holes CONT4 in the same way as the phosphorus doped polycrystalline silicon layer 22' buried in the contact holes CONT2.
  • an about 100 to 200 nm thick titanium nitride layer 41 is formed thereon, and thereafter, an about 100 nm thick silicon oxide layer 32 for a back-etching process is formed.
  • the silicon oxide layer 42 and the titanium nitride layer 41 are etched by an RIE process with a resist mask (not shown). Subsequently, grooves 21b are perforated in the insulating layer 21 by this RIE process. As a result, insulating islands 21' are formed in the memory cell array X.
  • a titanium nitride layer 43 is again formed. Note that the thickness of the titanium nitride layer 43 is smaller than that of the titanium nitride layer 41.
  • the titanium nitride layer 43 is anisotropically etched back by an RIE process using a mixture gas of HBr and Cl 2 . As a result, as shown in FIG. 14I, the titanium nitride layer 43 is left on only the sidewalls of the insulating islands 21' of the insulating layer 21.
  • a capacitor lower electrode layer 22 is constructed by the layers 41 and 43 and is coupled to the capacitor lower electrode layer 22b on the bottom of the grooves of the insulating layer 21. Also, in this case, the capacitor insulating layer 23b is etched with a mask of the capacitor lower electrode layer 22.
  • a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, STO, BST or PZT is formed by a CVD process. Also, a capacitor insulating layer 23 made of silicon nitride, or ferroelectrics such as tantalum oxide, STO or BST or PZT is formed. Then, a capacitor upper electrode layer 24 made of laninated TiN and W is formed by a sputtering process.
  • the capacitor upper electrode layer 24 and the capacitor insulating layer 23 are patterned. Note that the capacitor upper electrode layer 24b is electrically connected to the capacitor upper electrode layer 24.
  • an insulating layer 25 and first aluminum wiring layers 26 are formed to complete the device of FIG. 13.
  • FIG. 15 which is a modification of the device of FIG. 13, the capacitor lower electrode layer 22 on the insulating layer 21 on the peripheral circuit area Y is not provided. As a result, a step S between the memory cell array area X and the peripheral circuit area Y is reduced as compared with the fourth embodiment illustrated in FIG. 13.
  • the manufacture of the device of FIG. 15 is the same as that of FIG. 13 except that an RIE process using a resist pattern is added to remove the capacitor lower electrode 22 on the insulating layer 21 in FIG. 14I.
  • step S between the memory cell array area and the peripheral circuit area in a prior art 256 Mbit DRAM device is 0.8 to 1.0 ⁇ m
  • this step S in a 256 Mbit DRAM device according to the present invention is less than 0.3 ⁇ m.
  • a step between the memory cell array area and the peripheral circuit area can be reduced, a fine wiring pattern can be arranged around an interface therebetween, to enhance the integration of the device. Also, a highly integrated stacked capacitor can be obtained.

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Cited By (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2752484A1 (fr) * 1996-08-16 1998-02-20 United Microelectronics Corp Procede de fabrication d'une structure d'electrode de condensateur de stockage pour une cellule de memoire a semiconducteurs
US5808855A (en) * 1995-12-04 1998-09-15 Chartered Semiconductor Manufacturing Pte Ltd Stacked container capacitor using chemical mechanical polishing
US5838041A (en) * 1995-10-02 1998-11-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having memory cell transistor provided with offset region acting as a charge carrier injecting region
US5869382A (en) * 1996-07-02 1999-02-09 Sony Corporation Structure of capacitor for dynamic random access memory and method of manufacturing thereof
US5903493A (en) * 1997-09-17 1999-05-11 Lucent Technologies Inc. Metal to metal capacitor apparatus and method for making
US5939746A (en) * 1995-12-14 1999-08-17 Nec Corporation Semiconductor memory device and manufacturing method of the same
US5998256A (en) * 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6072210A (en) * 1998-12-24 2000-06-06 Lucent Technologies Inc. Integrate DRAM cell having a DRAM capacitor and a transistor
US6078093A (en) * 1996-04-12 2000-06-20 Lg Semicon Co., Ltd. Capacitor structure of semiconductor device for high dielectric constant
US6104055A (en) * 1997-03-27 2000-08-15 Nec Corporation Semiconductor device with memory cell having a storage capacitor with a plurality of concentric storage electrodes formed in an insulating layer and fabrication method thereof
EP1040518A1 (en) * 1997-11-20 2000-10-04 Advanced Technology Materials, Inc. CHEMICAL MECHANICAL POLISHING OF FeRAM CAPACITORS
US6150690A (en) * 1997-02-28 2000-11-21 Kabushiki Kaisha Toshiba Structure of a capacitor section of a dynamic random-access memory
KR20010004894A (ko) * 1999-06-30 2001-01-15 김영환 반도체 소자의 전하저장전극 형성방법
US20010017402A1 (en) * 2000-02-10 2001-08-30 Tatsuya Usami Semiconductor device and method of manufacturing the same
US20010025974A1 (en) * 1999-04-06 2001-10-04 Gealy F. Daniel Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same
US6300652B1 (en) * 1995-11-22 2001-10-09 Infineon Technologies Ag Memory cell configuration and method for its production
US6307228B1 (en) * 1997-08-06 2001-10-23 Fujitsu Limited Semiconductor device with perovskite capacitor and its manufacture method
US6352902B1 (en) * 1998-05-28 2002-03-05 International Business Machines Corporation Process of forming a capacitor on a substrate
US6421223B2 (en) * 1999-03-01 2002-07-16 Micron Technology, Inc. Thin film structure that may be used with an adhesion layer
KR100359246B1 (ko) * 1999-09-29 2002-11-04 동부전자 주식회사 적층형 캐패시터를 갖는 반도체 장치 제조 방법
US20020197793A1 (en) * 2000-01-06 2002-12-26 Dornfest Charles N Low thermal budget metal oxide deposition for capacitor structures
US6559495B1 (en) * 1999-10-01 2003-05-06 Nec Electronics Corporation Semiconductor memory cell device
US20030089925A1 (en) * 2001-11-15 2003-05-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6583463B1 (en) * 1997-10-14 2003-06-24 Hitachi, Ltd. Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator
US6586816B2 (en) * 1997-08-13 2003-07-01 Micron Technology, Inc. Semiconductor structures formed using redeposition of an etchable layer
US6590250B2 (en) 1997-11-25 2003-07-08 Micron Technology, Inc. DRAM capacitor array and integrated device array of substantially identically shaped devices
US6667502B1 (en) * 1999-08-31 2003-12-23 Micron Technology, Inc. Structurally-stabilized capacitors and method of making of same
US6710389B2 (en) 2001-02-09 2004-03-23 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
US6765255B2 (en) * 2002-03-26 2004-07-20 Samsung Electronics Co., Ltd. Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof
US20040180497A1 (en) * 1997-12-24 2004-09-16 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US20050054159A1 (en) * 2003-09-04 2005-03-10 Manning H. Montgomery Semiconductor constructions, and methods of forming capacitor devices
US20050051822A1 (en) * 2003-09-04 2005-03-10 Manning Homer M. Support for vertically oriented capacitors during the formation of a semiconductor device
US20050179076A1 (en) * 2003-03-17 2005-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming DRAM capactiors with protected outside crown surface for more robust structures
US20050248014A1 (en) * 1997-01-22 2005-11-10 Renesas Technology Corp. Resin-encapsulated semiconductor apparatus and process for its fabrication
US20050263814A1 (en) * 2003-01-06 2005-12-01 Samsung Electronics Co., Ltd. Bottom electrode of capacitor of semiconductor device and method of forming the same
US20060014344A1 (en) * 2004-07-19 2006-01-19 Manning H M Methods of forming semiconductor structures and capacitor devices
US20060051918A1 (en) * 2004-08-27 2006-03-09 Busch Brett W Methods of forming a plurality of capacitors
US20060121672A1 (en) * 2004-12-06 2006-06-08 Cem Basceri Methods of forming pluralities of capacitors, and integrated circuitry
US20060148190A1 (en) * 2004-08-30 2006-07-06 Busch Brett W Methods of forming a plurality of capacitors
US20060211211A1 (en) * 2005-03-18 2006-09-21 Sandhu Gurtej S Methods of forming pluralities of capacitors
US20060234464A1 (en) * 2005-04-19 2006-10-19 Stmicroelectronics S.A. Method for fabricating an integrated circuit comprising a three-dimensional capacitor
US20060246678A1 (en) * 2004-08-27 2006-11-02 Manning H M Methods of forming a plurality of capacitors
US20060255427A1 (en) * 2005-05-04 2006-11-16 Stmicroelectronics S.A. Integrated circuit comprising at least one capacitor and process for forming the capacitor
US20060258111A1 (en) * 2005-04-19 2006-11-16 Stmicroelectronics S.A. Process for producing an integrated circuit comprising a capacitor
US20060256597A1 (en) * 2005-05-13 2006-11-16 Stmicroelectronics S.R.L Method and relative circuit for generating a control voltage of a synchronous rectifier
US20060263968A1 (en) * 2005-05-18 2006-11-23 Micron Technology, Inc. Methods of forming pluralities of capacitors
US20060261440A1 (en) * 2005-05-18 2006-11-23 Micron Technology, Inc. Methods of forming a plurality of capacitors, and integrated circuitry comprising a pair of capacitors
US20070032014A1 (en) * 2005-08-02 2007-02-08 Micron Technology, Inc. Methods of forming pluralities of capacitors
US20070238259A1 (en) * 2006-04-10 2007-10-11 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20080090416A1 (en) * 2006-10-11 2008-04-17 Micro Technology, Inc. Methods of etching polysilicon and methods of forming pluralities of capacitors
US20080206950A1 (en) * 2007-02-26 2008-08-28 Micron Technology, Inc. Methods of forming a plurality of capacitors
DE102007016631A1 (de) * 2007-04-05 2008-10-30 Qimonda Ag Speicherkondensator, Speichervorrichtung und Verfahren zur Herstellung eines Speicherkondensators und einer Speichervorrichtung
US20090176011A1 (en) * 2008-01-08 2009-07-09 Mark Kiehlbauch Capacitor Forming Methods
US7563687B2 (en) 2004-12-16 2009-07-21 Stmicroelectronics S.A. Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit
US20090251845A1 (en) * 2008-04-08 2009-10-08 Micron Technology, Inc. High aspect ratio openings
US20100009512A1 (en) * 2008-07-09 2010-01-14 Fred Fishburn Methods of forming a plurality of capacitors
US7682924B2 (en) 2007-08-13 2010-03-23 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20100173490A1 (en) * 1997-04-02 2010-07-08 Chih-Chien Liu High density plasma chemical vapor deposition process
US20130076335A1 (en) * 2011-09-23 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8652926B1 (en) 2012-07-26 2014-02-18 Micron Technology, Inc. Methods of forming capacitors
US20140252545A1 (en) * 2013-03-06 2014-09-11 Nanya Technology Corp. Contact structure and semiconductor memory device using the same
US8946043B2 (en) 2011-12-21 2015-02-03 Micron Technology, Inc. Methods of forming capacitors
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9305996B2 (en) 2007-02-21 2016-04-05 Fujitsu Semiconductor Limited Semiconductor device
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0184064B1 (ko) * 1995-12-22 1999-03-20 문정환 반도체 소자의 캐패시터 제조방법
US6083831A (en) * 1996-03-26 2000-07-04 Micron Technology, Inc. Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor
JP2809183B2 (ja) * 1996-03-27 1998-10-08 日本電気株式会社 半導体記憶装置の製造方法
GB2321774A (en) * 1996-08-16 1998-08-05 United Microelectronics Corp Stacked capacitor
JP2977077B2 (ja) * 1996-08-16 1999-11-10 ユナイテッド マイクロエレクトロニクス コープ ツリー型コンデンサを備えた半導体メモリ素子
JP3210262B2 (ja) * 1996-08-16 2001-09-17 ユナイテッド マイクロエレクトロニクス コープ ツリー型コンデンサを備えた半導体メモリ素子の製造方法
DE19640273C1 (de) * 1996-09-30 1998-03-12 Siemens Ag Verfahren zur Herstellung barrierenfreier Halbleiterspeicheranordnungen
KR100506101B1 (ko) * 1996-11-14 2006-04-21 텍사스 인스트루먼츠 인코포레이티드 메모리 셀 어레이 제조방법 및 메모리 셀 어레이
WO1998028795A1 (fr) * 1996-12-20 1998-07-02 Hitachi, Ltd. Dispositif memoire a semi-conducteur et procede de fabrication associe
KR100464540B1 (ko) * 1996-12-31 2005-06-23 주식회사 하이닉스반도체 반도체소자의캐패시터제조방법
JP3466851B2 (ja) 1997-01-20 2003-11-17 株式会社東芝 半導体装置及びその製造方法
JP3137051B2 (ja) * 1997-10-08 2001-02-19 日本電気株式会社 半導体装置およびその製造方法
JPH11145410A (ja) * 1997-11-13 1999-05-28 Toshiba Corp 半導体装置およびその製造方法
WO1999062116A1 (fr) * 1998-05-25 1999-12-02 Hitachi, Ltd. Dispositif a semi-conducteurs et procede de fabrication
KR100300059B1 (ko) * 1998-12-08 2001-09-22 김영환 커패시터 제조방법
US6249016B1 (en) * 1999-01-13 2001-06-19 Agere Systems Guardian Corp. Integrated circuit capacitor including tapered plug
US6294807B1 (en) 1999-02-26 2001-09-25 Agere Systems Guardian Corp. Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers
KR100287187B1 (ko) * 1999-03-30 2001-04-16 윤종용 반도체소자의 커패시터 및 그 제조방법
JP2001085617A (ja) * 1999-09-09 2001-03-30 Nec Corp 半導体装置及びその製造方法
DE19950364A1 (de) * 1999-10-19 2001-04-26 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mindestens einem Kondensator und Verfahren zu deren Herstellung
JP2001339071A (ja) * 2000-03-22 2001-12-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2001291844A (ja) * 2000-04-06 2001-10-19 Fujitsu Ltd 半導体装置及びその製造方法
US6274899B1 (en) * 2000-05-19 2001-08-14 Motorola, Inc. Capacitor electrode having conductive regions adjacent a dielectric post
TW460954B (en) * 2000-11-09 2001-10-21 United Microelectronics Corp Manufacturing method of bottom electrode of semiconductor device
KR100416601B1 (ko) * 2001-06-30 2004-02-05 삼성전자주식회사 실린더형 커패시터를 포함하는 반도체 소자 및 그 제조 방법
US7317208B2 (en) * 2002-03-07 2008-01-08 Samsung Electronics Co., Ltd. Semiconductor device with contact structure and manufacturing method thereof
US20050280060A1 (en) * 2004-06-22 2005-12-22 Werner Juengling Concentric or nested container capacitor structure for integrated cicuits
JP2007141904A (ja) * 2005-11-15 2007-06-07 Elpida Memory Inc キャパシタおよびその製造方法
US8014125B2 (en) * 2007-11-26 2011-09-06 Ati Technologies Ulc Chip capacitor
US8753933B2 (en) 2008-11-19 2014-06-17 Micron Technology, Inc. Methods for forming a conductive material, methods for selectively forming a conductive material, methods for forming platinum, and methods for forming conductive structures
JP2011082543A (ja) * 2010-11-22 2011-04-21 Fujitsu Ltd 半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162881A (en) * 1989-08-24 1992-11-10 Nec Corporation Dynamic random access memory device having rampart structure outside memory cell array
US5247196A (en) * 1990-03-30 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including capacitor having stacked structure and manufacturing method thereof
US5274258A (en) * 1991-01-30 1993-12-28 Samsung Electronics Co., Ltd. High density semiconductor memory device (MBC cell)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441262A (en) * 1987-08-07 1989-02-13 Hitachi Ltd Memory cell
JPH01302851A (ja) * 1988-05-31 1989-12-06 Fujitsu Ltd 半導体メモリのメモリセル構造
JPH0221652A (ja) * 1988-07-08 1990-01-24 Mitsubishi Electric Corp 半導体記憶装置
JP2932540B2 (ja) * 1989-11-28 1999-08-09 ソニー株式会社 半導体メモリ装置
US5217914A (en) * 1990-04-10 1993-06-08 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor integration circuit with stacked capacitor cells
US5162248A (en) * 1992-03-13 1992-11-10 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
JP3222188B2 (ja) * 1992-04-14 2001-10-22 株式会社日立製作所 半導体装置及びその製造方法
KR960005251B1 (ko) * 1992-10-29 1996-04-23 삼성전자주식회사 반도체 메모리장치의 제조방법
US5401681A (en) * 1993-02-12 1995-03-28 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells
KR960015122B1 (ko) * 1993-04-08 1996-10-28 삼성전자 주식회사 고집적 반도체 메모리장치의 제조방법
JP2555965B2 (ja) * 1993-12-13 1996-11-20 日本電気株式会社 半導体装置の製造方法
US5418180A (en) * 1994-06-14 1995-05-23 Micron Semiconductor, Inc. Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162881A (en) * 1989-08-24 1992-11-10 Nec Corporation Dynamic random access memory device having rampart structure outside memory cell array
US5247196A (en) * 1990-03-30 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including capacitor having stacked structure and manufacturing method thereof
US5274258A (en) * 1991-01-30 1993-12-28 Samsung Electronics Co., Ltd. High density semiconductor memory device (MBC cell)

Cited By (196)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838041A (en) * 1995-10-02 1998-11-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having memory cell transistor provided with offset region acting as a charge carrier injecting region
US6300652B1 (en) * 1995-11-22 2001-10-09 Infineon Technologies Ag Memory cell configuration and method for its production
US5808855A (en) * 1995-12-04 1998-09-15 Chartered Semiconductor Manufacturing Pte Ltd Stacked container capacitor using chemical mechanical polishing
US5939746A (en) * 1995-12-14 1999-08-17 Nec Corporation Semiconductor memory device and manufacturing method of the same
US6078093A (en) * 1996-04-12 2000-06-20 Lg Semicon Co., Ltd. Capacitor structure of semiconductor device for high dielectric constant
US5869382A (en) * 1996-07-02 1999-02-09 Sony Corporation Structure of capacitor for dynamic random access memory and method of manufacturing thereof
FR2752484A1 (fr) * 1996-08-16 1998-02-20 United Microelectronics Corp Procede de fabrication d'une structure d'electrode de condensateur de stockage pour une cellule de memoire a semiconducteurs
US6300214B1 (en) 1996-11-01 2001-10-09 Micron Technology, Inc. Semiconductor processing methods of forming capacitor arrays on a substrate
US6316327B1 (en) 1996-11-01 2001-11-13 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6121653A (en) * 1996-11-01 2000-09-19 Micron Technology, Inc. Dram capacitor arrays with 3-capacitor and 6-capacitor geometries
US5998256A (en) * 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6753220B2 (en) 1996-11-01 2004-06-22 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6331461B1 (en) 1996-11-01 2001-12-18 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6482731B1 (en) 1996-11-01 2002-11-19 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US20050248014A1 (en) * 1997-01-22 2005-11-10 Renesas Technology Corp. Resin-encapsulated semiconductor apparatus and process for its fabrication
US7521744B2 (en) * 1997-01-22 2009-04-21 Renesas Technology Corp. Resin-encapsulated semiconductor apparatus and process for its fabrication
US6150690A (en) * 1997-02-28 2000-11-21 Kabushiki Kaisha Toshiba Structure of a capacitor section of a dynamic random-access memory
US6635933B2 (en) * 1997-02-28 2003-10-21 Kabushiki Kaisha Toshiba Structure of a capacitor section of a dynamic random-access memory
US6303429B1 (en) 1997-02-28 2001-10-16 Kabushiki Kaisha Toshiba Structure of a capacitor section of a dynamic random-access memory
US6104055A (en) * 1997-03-27 2000-08-15 Nec Corporation Semiconductor device with memory cell having a storage capacitor with a plurality of concentric storage electrodes formed in an insulating layer and fabrication method thereof
US8062536B2 (en) * 1997-04-02 2011-11-22 United Microelectronics Corp. High density plasma chemical vapor deposition process
US20100173490A1 (en) * 1997-04-02 2010-07-08 Chih-Chien Liu High density plasma chemical vapor deposition process
US6307228B1 (en) * 1997-08-06 2001-10-23 Fujitsu Limited Semiconductor device with perovskite capacitor and its manufacture method
US6586816B2 (en) * 1997-08-13 2003-07-01 Micron Technology, Inc. Semiconductor structures formed using redeposition of an etchable layer
US5903493A (en) * 1997-09-17 1999-05-11 Lucent Technologies Inc. Metal to metal capacitor apparatus and method for making
US6583463B1 (en) * 1997-10-14 2003-06-24 Hitachi, Ltd. Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator
US6627497B2 (en) 1997-10-14 2003-09-30 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
EP1040518A4 (en) * 1997-11-20 2001-03-21 Advanced Tech Materials MECHANICAL CHEMICAL POLISHING OF FERAM CAPACITORS
EP1040518A1 (en) * 1997-11-20 2000-10-04 Advanced Technology Materials, Inc. CHEMICAL MECHANICAL POLISHING OF FeRAM CAPACITORS
US6590250B2 (en) 1997-11-25 2003-07-08 Micron Technology, Inc. DRAM capacitor array and integrated device array of substantially identically shaped devices
US8471321B2 (en) 1997-12-24 2013-06-25 Renesas Electronics Corporation Semiconductor device comprising capacitor and method of fabricating the same
US7795648B2 (en) 1997-12-24 2010-09-14 Renesas Technology Corporation Semiconductor device comprising capacitor and method of fabricating the same
US20090148989A1 (en) * 1997-12-24 2009-06-11 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US20040180497A1 (en) * 1997-12-24 2004-09-16 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US7439132B2 (en) 1997-12-24 2008-10-21 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US7368776B2 (en) 1997-12-24 2008-05-06 Renesas Technology Corp. Semiconductor device comprising a highly-reliable, constant capacitance capacitor
US7816204B2 (en) 1997-12-24 2010-10-19 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US6940116B2 (en) 1997-12-24 2005-09-06 Renesas Technology Corp. Semiconductor device comprising a highly-reliable, constant capacitance capacitor
US7754562B2 (en) 1997-12-24 2010-07-13 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US20090184354A1 (en) * 1997-12-24 2009-07-23 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US8759891B2 (en) 1997-12-24 2014-06-24 Renesas Electronics Corporation Semiconductor device comprising capacitor and method of fabricating the same
CN100385670C (zh) * 1997-12-24 2008-04-30 三菱电机株式会社 具备电容器的半导体装置及其制造方法
US20060128095A1 (en) * 1997-12-24 2006-06-15 Renesas Technology Corp. Semiconductor device comprising a highly-reliable, constant capacitance capacitor
US20060113579A1 (en) * 1997-12-24 2006-06-01 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US7045420B2 (en) 1997-12-24 2006-05-16 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US20110001177A1 (en) * 1997-12-24 2011-01-06 Renesas Technology Corp. Semiconductor device comprising capacitor and method of fabricating the same
US6352902B1 (en) * 1998-05-28 2002-03-05 International Business Machines Corporation Process of forming a capacitor on a substrate
US6376302B1 (en) * 1998-12-24 2002-04-23 Agere Systems Guardian Corp. Method for forming a DRAM capacitor having a high dielectric constant dielectric and capacitor made thereby
US6072210A (en) * 1998-12-24 2000-06-06 Lucent Technologies Inc. Integrate DRAM cell having a DRAM capacitor and a transistor
US6757153B2 (en) 1999-03-01 2004-06-29 Micron Technology, Inc. Thin film structure that may be used with an adhesion layer
US6569689B2 (en) 1999-03-01 2003-05-27 Micron Technology, Inc. Method of forming a capacitor
US20070263340A1 (en) * 1999-03-01 2007-11-15 Micron Technology, Inc. Thin film structure that may be used with an adhesion layer
US8593784B2 (en) 1999-03-01 2013-11-26 Round Rock Research, Llc Thin film structure that may be used with an adhesion layer
US20040212090A1 (en) * 1999-03-01 2004-10-28 Marsh Eugene P. Method of forming a conductive structure
US7214602B2 (en) 1999-03-01 2007-05-08 Micron Technology, Inc. Method of forming a conductive structure
US6421223B2 (en) * 1999-03-01 2002-07-16 Micron Technology, Inc. Thin film structure that may be used with an adhesion layer
US20060097348A1 (en) * 1999-04-06 2006-05-11 Micron Technology, Inc. Structures having an electrode formed from a transition metal or a conductive metal-oxide
US6696718B1 (en) 1999-04-06 2004-02-24 Micron Technology, Inc. Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same
US20030057472A1 (en) * 1999-04-06 2003-03-27 Gealy F. Daniel Method of forming a capacitor
US20030100163A1 (en) * 1999-04-06 2003-05-29 Gealy F. Daniel Method of forming a device
US20060120019A1 (en) * 1999-04-06 2006-06-08 Micron Technology, Inc. Method of forming a capacitor
US6960513B2 (en) 1999-04-06 2005-11-01 Micron Technology, Inc. Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same
US20010025974A1 (en) * 1999-04-06 2001-10-04 Gealy F. Daniel Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same
US20030080369A1 (en) * 1999-04-06 2003-05-01 Gealy F. Daniel Method of forming a capacitor
US6689657B2 (en) * 1999-04-06 2004-02-10 Micron Technology, Inc. Method of forming a capacitor
US6919257B2 (en) 1999-04-06 2005-07-19 Micron Technology, Inc. Method of forming a capacitor
US7091101B2 (en) 1999-04-06 2006-08-15 Micron Technology, Inc. Method of forming a device
US7041570B2 (en) 1999-04-06 2006-05-09 Micron Technology, Inc. Method of forming a capacitor
US20020173112A1 (en) * 1999-04-06 2002-11-21 Gealy F. Daniel Method of forming a capacitor
US7026222B2 (en) 1999-04-06 2006-04-11 Micron Technology, Inc. Method of forming a capacitor
KR20010004894A (ko) * 1999-06-30 2001-01-15 김영환 반도체 소자의 전하저장전극 형성방법
US7282756B2 (en) 1999-08-31 2007-10-16 Micron Technology Inc. Structurally-stabilized capacitors and method of making of same
US6667502B1 (en) * 1999-08-31 2003-12-23 Micron Technology, Inc. Structurally-stabilized capacitors and method of making of same
US7488665B2 (en) 1999-08-31 2009-02-10 Micron Technology, Inc. Structurally-stabilized capacitors and method of making of same
US20040056295A1 (en) * 1999-08-31 2004-03-25 Agarwal Vishnu K. Structurally-stabilized capacitors and method of making of same
US20050093052A1 (en) * 1999-08-31 2005-05-05 Agarwal Vishnu K. Structurally-stabilized capacitors and method of making of same
KR100359246B1 (ko) * 1999-09-29 2002-11-04 동부전자 주식회사 적층형 캐패시터를 갖는 반도체 장치 제조 방법
US6559495B1 (en) * 1999-10-01 2003-05-06 Nec Electronics Corporation Semiconductor memory cell device
US20020197793A1 (en) * 2000-01-06 2002-12-26 Dornfest Charles N Low thermal budget metal oxide deposition for capacitor structures
US20010017402A1 (en) * 2000-02-10 2001-08-30 Tatsuya Usami Semiconductor device and method of manufacturing the same
US6670709B2 (en) * 2000-02-10 2003-12-30 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US7189616B2 (en) 2001-02-09 2007-03-13 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
US20040159871A1 (en) * 2001-02-09 2004-08-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
US7285462B2 (en) 2001-02-09 2007-10-23 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
US20070114588A1 (en) * 2001-02-09 2007-05-24 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
US6710389B2 (en) 2001-02-09 2004-03-23 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
US20030089925A1 (en) * 2001-11-15 2003-05-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6713805B2 (en) 2001-11-15 2004-03-30 Renesas Technology Corp. Semiconductor memory device with increased capacitance
US6765255B2 (en) * 2002-03-26 2004-07-20 Samsung Electronics Co., Ltd. Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof
DE10314307B4 (de) * 2002-03-26 2014-08-28 Samsung Electronics Co., Ltd. Verfahren zur Herstellung eines Halbleiterbauelements mit Kondensator
US20050263814A1 (en) * 2003-01-06 2005-12-01 Samsung Electronics Co., Ltd. Bottom electrode of capacitor of semiconductor device and method of forming the same
DE10362148B4 (de) * 2003-01-06 2010-01-14 Samsung Electronics Co., Ltd., Suwon Verfahren zur Herstellung der Bodenelektrode eines Kondensators einer Halbleitervorrichtung
US20050179076A1 (en) * 2003-03-17 2005-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming DRAM capactiors with protected outside crown surface for more robust structures
US7161204B2 (en) * 2003-03-17 2007-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area
US20050158949A1 (en) * 2003-09-04 2005-07-21 Manning Homer M. Semiconductor devices
US20050287780A1 (en) * 2003-09-04 2005-12-29 Micron Technology, Inc. Semiconductor constructions
US20100117196A1 (en) * 2003-09-04 2010-05-13 Manning Homer M Support For Vertically-Oriented Capacitors During The Formation of a Semiconductor Device
US8786001B2 (en) 2003-09-04 2014-07-22 Round Rock Research, Llc Semiconductor devices
US7067385B2 (en) 2003-09-04 2006-06-27 Micron Technology, Inc. Support for vertically oriented capacitors during the formation of a semiconductor device
US7655968B2 (en) 2003-09-04 2010-02-02 Micron Technology, Inc. Semiconductor devices
US7420238B2 (en) 2003-09-04 2008-09-02 Micron Technology, Inc. Semiconductor constructions
US7449391B2 (en) 2003-09-04 2008-11-11 Micron Technology, Inc. Methods of forming plurality of capacitor devices
US20050051822A1 (en) * 2003-09-04 2005-03-10 Manning Homer M. Support for vertically oriented capacitors during the formation of a semiconductor device
US7271051B2 (en) 2003-09-04 2007-09-18 Micron Technology, Inc. Methods of forming a plurality of capacitor devices
US20050054159A1 (en) * 2003-09-04 2005-03-10 Manning H. Montgomery Semiconductor constructions, and methods of forming capacitor devices
US20060063345A1 (en) * 2003-09-04 2006-03-23 Manning H M Methods of forming plurality of capacitor devices
US20060063344A1 (en) * 2003-09-04 2006-03-23 Manning H M Methods of forming a plurality of capacitor devices
US7125781B2 (en) 2003-09-04 2006-10-24 Micron Technology, Inc. Methods of forming capacitor devices
US7915136B2 (en) 2004-07-19 2011-03-29 Round Rock Research, Llc Methods of forming integrated circuit devices
US8164132B2 (en) 2004-07-19 2012-04-24 Round Rock Research, Llc Methods of forming integrated circuit devices
US20060014344A1 (en) * 2004-07-19 2006-01-19 Manning H M Methods of forming semiconductor structures and capacitor devices
US20090286377A1 (en) * 2004-07-19 2009-11-19 Micron Technology, Inc Methods of Forming Integrated Circuit Devices
US7387939B2 (en) 2004-07-19 2008-06-17 Micron Technology, Inc. Methods of forming semiconductor structures and capacitor devices
US20110186964A1 (en) * 2004-07-19 2011-08-04 Round Rock Research, Llc Methods of forming integrated circuit devices
US7585741B2 (en) 2004-07-19 2009-09-08 Micron Technology, Inc. Methods of forming capacitors
US7413952B2 (en) 2004-08-27 2008-08-19 Micron Technology, Inc. Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate
US7202127B2 (en) 2004-08-27 2007-04-10 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20070173030A1 (en) * 2004-08-27 2007-07-26 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20070161202A1 (en) * 2004-08-27 2007-07-12 Manning H M Methods of forming a plurality of capacitors
US7393743B2 (en) 2004-08-27 2008-07-01 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7445991B2 (en) 2004-08-27 2008-11-04 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20060051918A1 (en) * 2004-08-27 2006-03-09 Busch Brett W Methods of forming a plurality of capacitors
US20060246678A1 (en) * 2004-08-27 2006-11-02 Manning H M Methods of forming a plurality of capacitors
US7534694B2 (en) 2004-08-27 2009-05-19 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20060148190A1 (en) * 2004-08-30 2006-07-06 Busch Brett W Methods of forming a plurality of capacitors
US7445990B2 (en) 2004-08-30 2008-11-04 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20070093022A1 (en) * 2004-12-06 2007-04-26 Cem Basceri Integrated circuitry
US7320911B2 (en) 2004-12-06 2008-01-22 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7268034B2 (en) 2004-12-06 2007-09-11 Micron Technology, Inc. Methods of forming pluralities of capacitors, and integrated circuitry
US8207563B2 (en) 2004-12-06 2012-06-26 Round Rock Research, Llc Integrated circuitry
US20060252224A1 (en) * 2004-12-06 2006-11-09 Cem Basceri Methods of forming pluralities of capacitors, and integrated circuitry
US20060121672A1 (en) * 2004-12-06 2006-06-08 Cem Basceri Methods of forming pluralities of capacitors, and integrated circuitry
US7563687B2 (en) 2004-12-16 2009-07-21 Stmicroelectronics S.A. Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit
US20090209080A1 (en) * 2005-03-18 2009-08-20 Sandhu Gurtej S Methods of Forming Pluralities of Capacitors
US20060211211A1 (en) * 2005-03-18 2006-09-21 Sandhu Gurtej S Methods of forming pluralities of capacitors
US7557015B2 (en) 2005-03-18 2009-07-07 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7919386B2 (en) 2005-03-18 2011-04-05 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7479424B2 (en) 2005-04-19 2009-01-20 Stmicroelectronics S.A. Method for fabricating an integrated circuit comprising a three-dimensional capacitor
US20060234464A1 (en) * 2005-04-19 2006-10-19 Stmicroelectronics S.A. Method for fabricating an integrated circuit comprising a three-dimensional capacitor
US20060258111A1 (en) * 2005-04-19 2006-11-16 Stmicroelectronics S.A. Process for producing an integrated circuit comprising a capacitor
US7534692B2 (en) * 2005-04-19 2009-05-19 Stmicroelectronics Process for producing an integrated circuit comprising a capacitor
US20060255427A1 (en) * 2005-05-04 2006-11-16 Stmicroelectronics S.A. Integrated circuit comprising at least one capacitor and process for forming the capacitor
US7667292B2 (en) * 2005-05-04 2010-02-23 Stmicroelectronics S.A. Integrated circuit comprising at least one capacitor and process for forming the capacitor
US20060256597A1 (en) * 2005-05-13 2006-11-16 Stmicroelectronics S.R.L Method and relative circuit for generating a control voltage of a synchronous rectifier
US20100261331A1 (en) * 2005-05-18 2010-10-14 Manning H Montgomery Methods Of Forming A Plurality Of Capacitors
US7858486B2 (en) 2005-05-18 2010-12-28 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20060263968A1 (en) * 2005-05-18 2006-11-23 Micron Technology, Inc. Methods of forming pluralities of capacitors
US20060261440A1 (en) * 2005-05-18 2006-11-23 Micron Technology, Inc. Methods of forming a plurality of capacitors, and integrated circuitry comprising a pair of capacitors
US20070196978A1 (en) * 2005-05-18 2007-08-23 Manning H M Integrated circuitry comprising a pair of adjacent capacitors
US7825451B2 (en) 2005-05-18 2010-11-02 Micron Technology, Inc. Array of capacitors with electrically insulative rings
US7517753B2 (en) 2005-05-18 2009-04-14 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7544563B2 (en) 2005-05-18 2009-06-09 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7199005B2 (en) 2005-08-02 2007-04-03 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7393741B2 (en) 2005-08-02 2008-07-01 Micron Technology, Inc. Methods of forming pluralities of capacitors
US20070134872A1 (en) * 2005-08-02 2007-06-14 Sandhu Gurtej S Methods of forming pluralities of capacitors
US20070032014A1 (en) * 2005-08-02 2007-02-08 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7557013B2 (en) 2006-04-10 2009-07-07 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20070238259A1 (en) * 2006-04-10 2007-10-11 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7902081B2 (en) 2006-10-11 2011-03-08 Micron Technology, Inc. Methods of etching polysilicon and methods of forming pluralities of capacitors
US20080090416A1 (en) * 2006-10-11 2008-04-17 Micro Technology, Inc. Methods of etching polysilicon and methods of forming pluralities of capacitors
US9305996B2 (en) 2007-02-21 2016-04-05 Fujitsu Semiconductor Limited Semiconductor device
US20100311219A1 (en) * 2007-02-26 2010-12-09 Micron Technology, Inc. Methods of Forming a Plurality of Capacitors
US8129240B2 (en) 2007-02-26 2012-03-06 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8263457B2 (en) 2007-02-26 2012-09-11 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20080206950A1 (en) * 2007-02-26 2008-08-28 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7785962B2 (en) 2007-02-26 2010-08-31 Micron Technology, Inc. Methods of forming a plurality of capacitors
DE102007016631A1 (de) * 2007-04-05 2008-10-30 Qimonda Ag Speicherkondensator, Speichervorrichtung und Verfahren zur Herstellung eines Speicherkondensators und einer Speichervorrichtung
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8450164B2 (en) 2007-08-13 2013-05-28 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7682924B2 (en) 2007-08-13 2010-03-23 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20100151653A1 (en) * 2007-08-13 2010-06-17 Micron Technology, Inc. Methods Of Forming A Plurality Of Capacitors
US20090176011A1 (en) * 2008-01-08 2009-07-09 Mark Kiehlbauch Capacitor Forming Methods
US8388851B2 (en) 2008-01-08 2013-03-05 Micron Technology, Inc. Capacitor forming methods
US8734656B2 (en) 2008-01-08 2014-05-27 Micron Technology, Inc. Capacitor forming methods
US8274777B2 (en) 2008-04-08 2012-09-25 Micron Technology, Inc. High aspect ratio openings
US8760841B2 (en) 2008-04-08 2014-06-24 Micron Technology, Inc. High aspect ratio openings
US9595387B2 (en) 2008-04-08 2017-03-14 Micron Technology, Inc. High aspect ratio openings
US20090251845A1 (en) * 2008-04-08 2009-10-08 Micron Technology, Inc. High aspect ratio openings
US7759193B2 (en) 2008-07-09 2010-07-20 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20100009512A1 (en) * 2008-07-09 2010-01-14 Fred Fishburn Methods of forming a plurality of capacitors
US20100266962A1 (en) * 2008-07-09 2010-10-21 Micron Technology, Inc. Methods Of Forming A Plurality Of Capacitors
US8163613B2 (en) 2008-07-09 2012-04-24 Micron Technology, Inc. Methods of forming a plurality of capacitors
US9076757B2 (en) 2010-08-11 2015-07-07 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20140307510A1 (en) * 2011-09-23 2014-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
US9042171B2 (en) * 2011-09-23 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
US20130076335A1 (en) * 2011-09-23 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
US20150228644A1 (en) * 2011-09-23 2015-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor array having capacitor cell structures
US9385118B2 (en) * 2011-09-23 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor array having capacitor cell structures
US8780628B2 (en) * 2011-09-23 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US8946043B2 (en) 2011-12-21 2015-02-03 Micron Technology, Inc. Methods of forming capacitors
US9196673B2 (en) 2012-07-26 2015-11-24 Micron Technology, Inc. Methods of forming capacitors
US8652926B1 (en) 2012-07-26 2014-02-18 Micron Technology, Inc. Methods of forming capacitors
US9041154B2 (en) * 2013-03-06 2015-05-26 Nanya Technology Corp. Contact structure and semiconductor memory device using the same
US20140252545A1 (en) * 2013-03-06 2014-09-11 Nanya Technology Corp. Contact structure and semiconductor memory device using the same

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KR100242757B1 (ko) 2000-02-01

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