US20130009256A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20130009256A1
US20130009256A1 US13/635,312 US201113635312A US2013009256A1 US 20130009256 A1 US20130009256 A1 US 20130009256A1 US 201113635312 A US201113635312 A US 201113635312A US 2013009256 A1 US2013009256 A1 US 2013009256A1
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Prior art keywords
semiconductor device
body regions
region
field relaxation
regions
Prior art date
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Abandoned
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US13/635,312
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English (en)
Inventor
Keiji Okumura
Mineo Miura
Yuki Nakano
Noriaki Kawamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Assigned to ROHM CO., LTD. reassignment ROHM CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ABE, HIDETOSHI, KAWAMOTO, NORIAKI, MIURA, MINEO, NAKANO, YUKI, OKUMURA, KEIJI
Publication of US20130009256A1 publication Critical patent/US20130009256A1/en
Abandoned legal-status Critical Current

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    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present invention relates to a semiconductor device, and more detailedly, it relates to a power device employed in the field of power electronics.
  • a high withstand voltage semiconductor device (a power device) to which high voltage is applied is employed in the field of power electronics.
  • a vertical structure capable of easily feeding high current and capable of easily ensuring high withstand voltage and low on-resistance is known as the structure of the power device (for example, Patent Document 1).
  • a power device of the vertical structure includes an n + -type substrate, an n ⁇ -type epitaxial layer stacked on the substrate, p-type body regions plurally formed on a surface layer portion of the epitaxial layer at an interval, and an n + -type source region formed on a surface layer portion of each body region, for example.
  • a gate insulating film is formed to extend between adjacent body regions, and a gate electrode is formed on the gate insulating film. The gate electrode is opposed to each body region through the gate insulating film.
  • a source electrode is electrically connected to the source region.
  • a drain electrode is formed on the back surface of the substrate.
  • Voltage of not less than a threshold is applied to the gate electrode in a state applying voltage between the source electrode and the drain electrode (between a source and a drain), whereby channels are formed in the vicinity of interfaces between the body regions and the gate insulating film due to an electric field from the gate electrode.
  • current flows between the source electrode and the drain electrode, and the power device enters an ON-state.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2003-347548
  • An object of the present invention is to provide a semiconductor device excellent in withstand voltage characteristics and manufacturable with a high yield.
  • a semiconductor device for attaining the aforementioned object includes a semiconductor layer of a first conductivity type, body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval, a source region of the first conductivity type formed on a surface layer portion of each body region, a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other, a gate electrode provided on the gate insulating film and opposed to the body regions, and a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film.
  • the HTRB test is a test for confirming withstand voltage of a device by continuously applying voltage approximate to the withstand voltage of the device between a source and a drain under a high temperature in a state where the device is off.
  • the field relaxation portion relaxing the electric field generated in the gate insulating film is provided between the adjacent body regions in such a vertical structure that the source region and a region of the semiconductor layer functionable as the drain are arranged in the vertical direction through the body regions. Even if voltage approximate to the withstand voltage is continuously applied between the source and the drain, therefore, dielectric breakdown of the gate insulating film can be suppressed. According to the inventive structure, therefore, a semiconductor device excellent in withstand voltage can be manufactured with a high yield.
  • the inventors have further investigated a spot where dielectric breakdown is particularly easily caused in a gate insulating film every array pattern (cell layout) of body regions in a semiconductor device, to find the following common feature as to a specific array pattern:
  • the field relaxation portion preferably includes a dotlike field relaxation portion provided on the intersection point between two straight lines included in the straight lines.
  • the field relaxation portion (the dotlike field relaxation portion) is provided on the intersection point between two straight lines included in the plurality of straight lines extending between the respective ones of the adjacent body regions, dielectric breakdown of the gate insulating film around the intersection point can be effectively suppressed.
  • the field relaxation portion may include a linear field relaxation portion provided on a portion along the straight lines extending between the respective ones of the three body regions arranged on the positions of the respective apexes of a triangle.
  • the dotlike field relaxation portion may have a sectional area greater than the sectional area of the linear field relaxation portion in an orthogonal direction orthogonal to the straight lines extending between the respective ones of the adjacent body regions, and the dotlike field relaxation portion may overlap with the body regions in plan view. Further, the dotlike field relaxation portion may be in the form of a square in plan view.
  • the linear field relaxation portion may be formed integrally with the dotlike field relaxation portion, or may be formed to separate from the dotlike field relaxation portion.
  • the dotlike field relaxation portion is preferably provided on a position overlapping with a region where a line region extending between the respective ones of the body regions in the form of the matrix in a row direction and a line region extending between the respective ones in a column direction intersect with each other in plan view.
  • dielectric breakdown of the gate insulating film is particularly easily caused around the region (an intersectional region) where the line regions extending between the respective ones of the body regions in the row direction and in the column direction respectively intersect with each other.
  • the field relaxation portion is preferably provided on a position overlapping with a longitudinal end portion of a line region extending between the adjacent body regions along the longitudinal direction in plan view.
  • dielectric breakdown of the gate insulating film is particularly easily caused around the longitudinal end portion of the line region extending between the adjacent body regions along the longitudinal direction.
  • the field relaxation portion is provided on the position overlapping with the longitudinal end portion of the line region extending between the adjacent body regions along the longitudinal direction in plan view, therefore, dielectric breakdown of the gate insulating film around the end portion can be effectively suppressed.
  • the field relaxation portion is preferably further provided also on a portion along the line region extending between the adjacent body regions along the longitudinal direction.
  • the plane area of the field relaxation portion may be smaller than the plane area of the body regions.
  • a field relaxation portion may include an implantation region formed by implanting a second conductivity type impurity between the body regions adjacent to each other on the semiconductor layer.
  • a depletion layer resulting from junction (p-n junction) between the implantation region and the semiconductor layer can be formed between the adjacent body regions on the semiconductor layer by forming the implantation region of the second conductivity type different from the conductivity type of the semiconductor layer.
  • Equipotential surfaces of high potential with reference to the gate electrode can be separated from the gate insulating film, due to the presence of the depletion layer. Consequently, the electric field applied to the gate insulating film can be reduced, whereby dielectric breakdown can be suppressed.
  • the implantation region may be formed by implanting Al or B as the second conductivity type impurity.
  • the implantation region may be increased in resistance due to the implantation of the second conductivity type impurity into the semiconductor layer, and in this case, the same may be increased in resistance due to implantation of Al, B, Ar or V.
  • the field relaxation layer may include the thick-film portion as the field relaxation portion.
  • the portion opposed to the portion of the semiconductor layer located between the body regions is so increased in thickness that dielectric breakdown withstand voltage of the portion (the thick-film portion) can be rendered greater than that of the remaining portion. Even if the electric field is applied to the thick-film portion, therefore, the thick-film portion does not dielectrically break down, but can relax the applied electric field therein.
  • the portion opposed to the body regions is the thin-film portion in the gate insulating film, whereby an electric field generated by applying voltage to the gate electrode for forming channels in the body regions can be inhibited from weakening in the gate insulating film. Therefore, the withstand voltage can be improved while suppressing reduction of a transistor function of the semiconductor device.
  • the field relaxation layer may include the embedded portion of the interlayer dielectric film as the field relaxation portion.
  • the portion of the gate insulating film opposed to the portion of the semiconductor layer located between the body regions is interposed between the semiconductor layer and the insulating embedded portion. Even if an electric field results from the potential difference between the gate electrode and the semiconductor layer, therefore, the electric field can be rendered hardly applicable to the portion of the gate insulating film opposed to the portion located between the adjacent body regions. Consequently, a total electric field applied to the portion of the gate insulating film can be relaxed.
  • the field relaxation layer may include the high dielectric constant portion as the field relaxation portion.
  • the portion of the gate insulating film opposed to the portion of the semiconductor layer located between the body regions is so brought into the high dielectric constant portion that dielectric breakdown withstand voltage of the portion (the high dielectric constant portion) can be rendered greater than that of the remaining portion. Even if an electric field is applied to the high dielectric constant portion, therefore, the high dielectric constant portion does not dielectrically break down, but can relax the applied electric field therein.
  • the portion of the gate insulating film opposed to the body regions is the low dielectric constant portion, whereby an electric field generated by applying voltage to the gate electrode for forming channels in the body regions can be inhibited from weakening in the gate insulating film. Therefore, the withstand voltage can be improved while suppressing reduction of the transistor function of the semiconductor device.
  • the field relaxation layer may include the protrusion as the field relaxation portion.
  • the protrusion is so provided between the adjacent body regions that the distance from the back surface of the semiconductor layer up to the gate insulating film lengthens by the quantity of projection of the protrusion between the body regions.
  • the semiconductor layer can sufficiently drop voltage applied to the gate insulation film. Therefore, voltage of equipotential surfaces distributed immediately under the gate insulating film between the body regions can be reduced. Consequently, the electric field applied to the gate insulating film can be relaxed.
  • the impurity of the second conductivity type is preferably implanted into the protrusion.
  • a depletion layer resulting from junction (p-n junction) between the protrusion and the remaining portion of the semiconductor layer can be formed between the body regions.
  • Equipotential surfaces of high potential with reference to the gate electrode can be separated from the gate insulating film, due to the presence of the depletion layer. Consequently, the electric field applied to the gate insulating film can be further reduced.
  • the protrusion is preferably covered with the high dielectric constant portion, and in this case, the field relaxation portion includes both of the protrusion and the high dielectric constant portion.
  • dielectric breakdown withstand voltage of the high dielectric constant portion can be rendered greater than that of the remaining portion of the gate insulating film. Therefore, an effect of field relaxation by the high dielectric constant portion can also be relished, in addition to an effect of field relaxation by the protrusion.
  • the high dielectric constant portion may be formed to cover the protrusion and to be opposed to the body regions.
  • the low dielectric constant portion may be interposed between the body regions and a portion of the high dielectric constant portion opposed to the body regions.
  • the high dielectric constant portion may be interposed between the protrusion and a portion of the low dielectric constant portion covering the protrusion.
  • the field relaxation portion may be constituted of the implantation region and the thick-film portion.
  • the field relaxation portion may be constituted of the implantation region and the embedded portion.
  • the field relaxation portion may be constituted of the implantation region and the high dielectric constant portion.
  • the semiconductor layer preferably has a dielectric breakdown electric field of not less than 1 MV/cm, and is preferably made of SiC, for example.
  • An electric field easily concentrates on the gate insulating film on the SiC semiconductor layer due to step punching on an SiC single-crystalline growth surface, and hence an effect at a time of applying the present invention is remarkable.
  • As a semiconductor layer having a dielectric breakdown electric field of not less than 1 MV/cm, 3C—SiC (3.0 MV/cm), 6H—SiC (3.0 MV/cm), 4H—SiC (3.5 MV/cm), GaN (2.6 MV/cm), diamond (5.6 MV/cm) or the like can be listed, for example.
  • the body regions may be in the form of regular polygons in plan view, and may be in the form of squares in plan view, for example.
  • the body regions are in the form of regular hexagons in plan view
  • the body regions are preferably arrayed in the form of a honeycomb. Further, the body regions may be in the form of circles in plan view.
  • FIGS. 1( a ) and 1 ( b ) are schematic plan views of a semiconductor device according to a first embodiment of the present invention, while FIG. 1( a ) shows a general diagram and FIG. 1( b ) shows an enlarged internal diagram respectively.
  • FIGS. 2( a ) and 2 ( b ) are schematic sectional views of the semiconductor device according to the first embodiment of the present invention, while FIG. 2( a ) shows a cutting plane along a cutting plane line IIa-IIa in FIG. 1( a ) and FIG. 2( b ) shows a cutting plane along a cutting plane line IIb-IIb in FIG. 1( b ) respectively.
  • FIG. 3A is a schematic sectional view for illustrating a method of manufacturing the semiconductor device shown in FIG. 2( b ).
  • FIG. 3B is a diagram showing a step subsequent to FIG. 3A .
  • FIG. 3C is a diagram showing a step subsequent to FIG. 3B .
  • FIG. 3D is a diagram showing a step subsequent to FIG. 3C .
  • FIG. 3E is a diagram showing a step subsequent to FIG. 3D .
  • FIG. 3F is a diagram showing a step subsequent to FIG. 3E .
  • FIG. 3G is a diagram showing a step subsequent to FIG. 3F .
  • FIG. 3H is a diagram showing a step subsequent to FIG. 3G .
  • FIG. 3I is a diagram showing a step subsequent to FIG. 3H .
  • FIG. 3J is a diagram showing a step subsequent to FIG. 3I .
  • FIG. 3K is a diagram showing a step subsequent to FIG. 3J .
  • FIGS. 4( a ) and 4 ( b ) are diagrams for illustrating a first modification of the semiconductor device according to the first embodiment, while FIG. 4( a ) shows a schematic plan view and FIG. 4( b ) shows a cutting plane along a cutting plane line IVb-IVb in FIG. 4( a ) respectively.
  • FIGS. 5( a ) and 5 ( b ) are diagrams for illustrating a second modification of the semiconductor device according to the first embodiment, while FIG. 5( a ) shows a schematic plan view and FIG. 5( b ) shows a cutting plane along a cutting plane line Vb-Vb in FIG. 5( a ) respectively.
  • FIG. 6 is a schematic plan view for illustrating a third modification of the semiconductor device according to the first embodiment.
  • FIG. 7 is a schematic plan view for illustrating a fourth modification of the semiconductor device according to the first embodiment.
  • FIGS. 8( a ) and 8 ( b ) are schematic plan views for illustrating a fifth modification of the semiconductor device according to the first embodiment, while FIG. 8 ( a ) shows a schematic plan view and FIG. 8( b ) shows a cutting plane along a cutting plane line VIIIb-VIIIb in FIG. 8( a ) respectively.
  • FIG. 9 is a schematic plan view for illustrating a sixth modification of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic plan view for illustrating a seventh modification of the semiconductor device according to the first embodiment.
  • FIGS. 11( a ) and 11 ( b ) are schematic plan views of a semiconductor device according to a second embodiment of the present invention, while FIG. 11( a ) shows a general diagram and FIG. 11( b ) shows an enlarged internal diagram respectively.
  • FIGS. 12( a ) and 12 ( b ) are schematic sectional views of the semiconductor device according to the second embodiment of the present invention, while FIG. 12( a ) shows a cutting plane along a cutting plane line XIIa-XIIa in FIG. 11( b ) and FIG. 12( b ) shows a cutting plane along a cutting plane line XIIb-XIIb in FIG. 11( b ) respectively.
  • FIG. 13A is a schematic sectional view for illustrating a method of manufacturing the semiconductor device shown in FIG. 12( b ).
  • FIG. 13B is a diagram showing a step subsequent to FIG. 13A .
  • FIG. 13C is a diagram showing a step subsequent to FIG. 13B .
  • FIG. 13D is a diagram showing a step subsequent to FIG. 13C .
  • FIG. 13E is a diagram showing a step subsequent to FIG. 13D .
  • FIG. 13F is a diagram showing a step subsequent to FIG. 13E .
  • FIG. 13G is a diagram showing a step subsequent to FIG. 13F .
  • FIG. 13H is a diagram showing a step subsequent to FIG. 13G .
  • FIG. 13I is a diagram showing a step subsequent to FIG. 13H .
  • FIG. 13J is a diagram showing a step subsequent to FIG. 13I .
  • FIG. 13K is a diagram showing a step subsequent to FIG. 13J .
  • FIGS. 14( a ) and 14 ( b ) are schematic plan views of a semiconductor device according to a third embodiment of the present invention, while FIG. 14( a ) shows a general diagram and FIG. 14( b ) shows an enlarged internal diagram respectively.
  • FIGS. 15( a ) and 15 ( b ) are schematic sectional views of the semiconductor device according to the third embodiment of the present invention, while FIG. 15( a ) shows a cutting plane line along a cutting plane line XVa-XVa in FIG. 14( b ) and FIG. 15( b ) shows a cutting plane along a cutting plane line XVb-XVb in FIG. 14( b ) respectively.
  • FIG. 16A is a schematic sectional view for illustrating a method of manufacturing the semiconductor device shown in FIG. 15( b ).
  • FIG. 16B is a diagram showing a step subsequent to FIG. 16A .
  • FIG. 16C is a diagram showing a step subsequent to FIG. 16B .
  • FIG. 16D is a diagram showing a step subsequent to FIG. 16C .
  • FIG. 16E is a diagram showing a step subsequent to FIG. 16D .
  • FIG. 16F is a diagram showing a step subsequent to FIG. 16E .
  • FIG. 16G is a diagram showing a step subsequent to FIG. 16F .
  • FIG. 16H is a diagram showing a step subsequent to FIG. 16G .
  • FIG. 16I is a diagram showing a step subsequent to FIG. 16H .
  • FIG. 16J is a diagram showing a step subsequent to FIG. 16I .
  • FIG. 16K is a diagram showing a step subsequent to FIG. 16J .
  • FIG. 17 is a schematic plan view for illustrating a first modification of the semiconductor device according to the third embodiment.
  • FIG. 18 is a schematic plan view for illustrating a second modification of the semiconductor device according to the third embodiment.
  • FIG. 19 is an enlarged sectional view of a principal portion of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 20 is a sectional view for illustrating a first modification of the semiconductor device according to the fourth embodiment.
  • FIG. 21 is a sectional view for illustrating a second modification of the semiconductor device according to the fourth embodiment.
  • FIG. 22 is an enlarged sectional view of a principal portion of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 23 is a sectional view for illustrating a first modification of the semiconductor device according to the fifth embodiment.
  • FIG. 24 is a sectional view for illustrating a second modification of the semiconductor device according to the fifth embodiment.
  • FIG. 25 is a sectional view for illustrating a third modification of the semiconductor device according to the fifth embodiment.
  • FIG. 26 is a sectional view for illustrating a fourth modification of the semiconductor device according to the fifth embodiment.
  • FIG. 27 is a schematic plan view for illustrating an eighth modification of the semiconductor device according to the first embodiment.
  • FIGS. 28( a ) and 28 ( b ) are schematic sectional views of a semiconductor device according to a sixth embodiment of the present invention.
  • FIGS. 29( a ) and 29 ( b ) are schematic sectional views of a semiconductor device according to a seventh embodiment of the present invention.
  • FIGS. 30( a ) and 30 ( b ) are schematic sectional views of a semiconductor device according to an eighth embodiment of the present invention.
  • FIGS. 1( a ) and 1 ( b ) are schematic plan views of a semiconductor device according to a first embodiment of the present invention, while FIG. 1( a ) shows a general diagram and FIG. 1( b ) shows an enlarged internal diagram respectively.
  • FIGS. 2( a ) and 2 ( b ) are schematic sectional views of the semiconductor device according to the first embodiment of the present invention, while FIG. 2( a ) shows a cutting plane along a cutting plane line IIa-IIa in FIG. 1( a ) and FIG. 2( b ) shows a cutting plane along a cutting plane line IIb-IIb in FIG. 1( b ) respectively.
  • This semiconductor device 1 is a planar gate VDMOSFET employing SiC, and in the form of a chip square in plan view, as shown in FIG. 1( a ), for example.
  • the lengths in the vertical and horizontal directions in the plane of FIG. 1( a ) are about several mm respectively.
  • a source pad 2 is formed on the surface of the semiconductor device 1 .
  • the source pad 2 is generally in the form of a square in plan view whose four corners are bent outward, and formed to cover generally the whole region of the surface of the semiconductor device 1 .
  • a removed region 3 generally square in plan view is formed around the center of one side thereof. The removed region 3 is a region where the source pad 2 is not formed.
  • a gate pad 4 is arranged on the removed region 3 .
  • An interval is provided between the gate pad 4 and the source pad 2 , which are insulated from each other.
  • the semiconductor device 1 includes an SiC substrate 5 of an n + -type (whose concentration is 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 , for example). According to the embodiment, the SiC substrate 5 functions as a drain of the semiconductor device 1 , while a surface 6 (upper surface) thereof is an Si plane, and a back surface 7 (lower surface) thereof is a C plane.
  • An epitaxial layer 8 made of SiC of an n ⁇ -type (whose concentration is 1 ⁇ 10 15 to 1 ⁇ 10 17 cm ⁇ 3 , for example) in a lower concentration than the SiC substrate 5 is stacked on the SiC substrate 5 .
  • the epitaxial layer 8 as a semiconductor layer is formed on the SiC substrate 5 by the so-called epitaxial growth.
  • the epitaxial layer 8 formed on the surface 6 which is the Si plane is grown with a major growth surface of an Si plane. Therefore, a surface 9 of the epitaxial layer 8 formed by the epitaxial growth is an Si plane, similarly to the surface 6 of the SiC substrate 5 .
  • An active region 10 arranged on a central portion of the epitaxial layer 8 in plan view to function as a field-effect transistor is formed on the semiconductor device 1 , as shown in FIG. 1( a ).
  • a plurality of (in this embodiment, two) guard rings 11 are formed on the epitaxial layer 8 at an interval from the active region 10 , to surround the active region 10 .
  • the interval between the active region 10 and the guard rings 11 is generally constant universally over the whole periphery.
  • the guard rings 11 are low-concentration regions of a p ⁇ -type (whose concentration is 1 ⁇ 10 13 to 1 ⁇ 10 18 cm ⁇ 3 , for example) formed by implanting a p-type impurity into the epitaxial layer 8 .
  • p-type body regions 12 are formed in a large number to be arrayed in the form of a matrix at a constant pitch in a row direction and a column direction.
  • Each body region 12 is in the form of a square in plan view, and the lengths in the vertical and horizontal directions in the plane of FIG. 1( b ) are about 7.2 ⁇ m respectively, for example.
  • the depth of the body region 12 is about 0.65 ⁇ m, for example.
  • the concentration in the body region 12 is about 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 , for example.
  • a region of the epitaxial layer 8 closer to the SiC substrate 5 (closer to the C plane) than the body regions 12 is an n ⁇ -type drift region 13 where the state after the epitaxial growth is maintained.
  • a body contact region 14 is formed on a central portion thereof, and a source region 15 is formed to surround the body contact region 14 .
  • the body contact region 14 is in the form of a square in plan view, and the lengths in the vertical and horizontal directions in the plane of FIG. 1( b ) are about 1.6 ⁇ m respectively, for example.
  • the depth of the body contact region 14 is 0.35 ⁇ m, for example.
  • the source region 15 is in the form of a square ring in plan view, and the lengths in the vertical and horizontal directions in the plane of FIG. 1( b ) are about 5.7 ⁇ m respectively, for example.
  • the depth of the source region 15 is about 0.25 ⁇ m, for example.
  • regions (interbody regions 16 held between side surfaces of adjacent body regions 12 ) between the respective ones of the body regions 12 arrayed in the form of the matrix at the constant pitch are in the form of a lattice having a constant (2.8 ⁇ m, for example) width.
  • the interbody regions 16 include line regions 17 linearly extending in the respective ones of the row direction and the column direction along four side surfaces of each body region 12 and intersectional regions 18 where the line regions 17 extending in the row direction and the line regions 17 extending in the column direction intersect with one another.
  • the intersectional region 18 is a square-shaped region surrounded by inner corners of the arrayed four body regions 12 and partitioned by extensions of four sides of the body regions 12 (a region surrounded by square broken lines in FIG. 1( b )).
  • a latticed gate insulating film 19 is formed along the interbody regions 16 .
  • the gate insulating film 19 extends over adjacent body regions 12 , and covers portions (peripheral edge portions of the body regions 12 ) of the body regions 12 surrounding the source regions 15 and outer peripheral edges of the source regions 15 .
  • the gate insulating film 19 is made of SiO 2 (silicon oxide), and the thickness thereof is about 400 ⁇ and generally uniform.
  • the gate insulating film 19 may be formed by an oxide film containing nitrogen, such as a silicon oxynitride film prepared by thermal oxidation employing gas containing nitrogen and oxygen, for example.
  • a gate electrode 20 is formed on the gate insulating film 19 .
  • the gate electrode 20 is formed in a latticed manner along the latticed gate insulating film 19 , and opposed to the peripheral edge portion of each body region 12 through the gate insulating film 19 .
  • the gate electrode 20 is made of polysilicon, and a p-type impurity is introduced thereinto in a high concentration, for example.
  • the thickness of the gate electrode 20 is about 6000 ⁇ , for example.
  • boundaries between unit cells are set at width-directional centers of the interbody regions 16 .
  • the lengths in the vertical and horizontal directions in the plane of FIG. 1( b ) are about 10 ⁇ m respectively, for example.
  • the depth direction of the body regions 12 is a gate length direction
  • the circumferential direction of the body regions 12 orthogonal to the gate length direction is a gate width direction.
  • drain current flowing toward the side of the surface 9 of the epitaxial layer 8 along four side surfaces of each body region 12 in the drift region 13 can be fed to the source region 15 by controlling voltage applied to the gate electrode 20 thereby forming annular channels in the peripheral edge portions of the body regions 12 of each unit cell.
  • a p ⁇ -type implantation region 21 as a field relaxation layer formed by implanting a p-type impurity into the epitaxial layer 8 is formed on the interbody regions 16 of the epitaxial layer 8 .
  • the depth of the implantation region 21 is about 0.65 ⁇ m (shallower than the body regions 12 ), for example.
  • the concentration in the implantation region 21 is lower than the concentration in the body regions 12 , and 1 ⁇ 10 13 to 1 ⁇ 10 18 cm ⁇ 3 , for example.
  • the implantation region 21 may be an i-type (intrinsic semiconductor) region whose impurity concentration is not more than 1 ⁇ 10 16 cm ⁇ 3 , of a region increased in resistance, for example.
  • the concentration in the implantation region 21 may be higher than the concentration in the body regions 12 .
  • the implantation region 21 is in the form of a lattice formed over the whole areas of the interbody regions 16 , and integrally includes intersectional portions 22 formed on the intersectional regions 18 and linear portions 23 as linear field relaxation portions formed on the line regions 17 .
  • Each intersectional portion 22 is in the form of a square slightly larger than each intersectional region 18 in plan view, and the respective corners thereof enter corners of four body regions 12 facing the intersectional region 18 respectively.
  • body regions 12 a to 12 c in FIG. 1( b ) for example
  • the intersectional region 22 is provided on the intersection point therebetween.
  • the linear portions 23 are in the form of straight lines of a constant width linking centers of respective sides of intersectional portions 22 adjacent to one another in plan view, and at intervals from side surfaces of the body regions 12 .
  • the intervals are so provided between the linear portions 23 and the body regions 12 that a path of drain current flowing along four side surfaces of each body region 12 in an ON-state of the semiconductor device 1 can be ensured.
  • increase in on-resistance can be suppressed, and an excellent transistor operation can be performed.
  • An interlayer dielectric film 25 made of SiO 2 is formed on the epitaxial layer 8 , to cover the gate electrode 20 .
  • Contact holes 26 are formed in the interlayer dielectric film 25 . Central portions of the source regions 15 and the whole of the body contact regions 14 are exposed in the contact holes 26 .
  • a source electrode 27 is formed on the interlayer dielectric film 25 .
  • the source electrode 27 is collectively in contact with the body contact regions 14 and the source regions 15 of all unit cells through the respective contact holes 26 .
  • the source electrode 27 serves as a wire common to all unit cells.
  • An interlayer dielectric film (not shown) is formed on the source electrode 27 , and the source electrode 27 is electrically connected to the source pad 2 (see FIG. 1( a )) through the interlayer dielectric film (not shown).
  • the gate pad 4 (see FIG. 1( a )) is electrically connected to the gate electrode 20 through a gate wire (not shown) drawn onto the interlayer dielectric film (not shown).
  • the source electrode 27 has such a structure that a Ti/TiN layer 28 and an Al layer 29 are stacked successively from the side in contact with the epitaxial layer 8 .
  • a drain electrode 30 is formed on the back surface 7 of the SiC substrate 5 , to cover the whole area thereof.
  • the drain electrode 30 serves as an electrode common to all unit cells.
  • Such a multilayer structure (Ti/Ni/Au/Ag) that Ti, Ni, Au and Ag are stacked successively from the side of the SiC substrate 5 can be applied as the drain electrode 30 , for example.
  • FIGS. 3A to 3K are schematic sectional views for illustrating a method of manufacturing the semiconductor device shown in FIG. 2( b ).
  • an SiC crystal is first grown on the surface 6 (the Si plane) of the Si substrate 5 by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy), for example, while introducing an n-type impurity (n (nitrogen) in this embodiment), as shown in FIG. 3A .
  • epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy), for example, while introducing an n-type impurity (n (nitrogen) in this embodiment), as shown in FIG. 3A .
  • n-type impurity n (nitrogen) in this embodiment
  • a p-type impurity (Al (aluminum) in this embodiment) is implanted from the surface 9 of the epitaxial layer 8 into the epitaxial layer 8 by employing an SiO 2 mask 31 having openings in portions for forming the body regions 12 , as shown in FIG. 3B .
  • the implantation conditions at this time vary with the type of the p-type impurity, the dose is about 6 ⁇ 10 13 cm ⁇ 2 and acceleration energy is about 380 keV, for example.
  • the body regions 12 are formed on the surface layer portion of the epitaxial layer 8 .
  • the drift region 13 maintaining the state after the epitaxial growth is formed on a base layer portion of the epitaxial layer 8 .
  • an n-type impurity (P (phosphorus) in this embodiment) is implanted from the surface 9 of the epitaxial layer 8 into the epitaxial layer 8 by employing an SiO 2 mask 32 having openings in regions for forming the source regions 15 , as shown in FIG. 3C . While the implantation conditions at this time vary with the type of the n-type impurity, the dose is about 2.5 ⁇ 10 15 cm ⁇ 2 and acceleration energy is in four stages in the range of 30 keV to 160 keV, for example. Thus, the source regions 15 are formed on the surface layer portions of the body regions 12 .
  • a p-type impurity (Al in this embodiment) is implanted from the surface 9 of the epitaxial layer 8 into the epitaxial layer 8 by employing an SiO 2 mask 33 having openings in regions for forming the implantation region 21 and the guard rings 11 , as shown in FIG. 3D .
  • the implantation conditions at this time vary with the type of the p-type impurity, the dose is about 2.7 ⁇ 10 13 cm ⁇ 2 and acceleration energy is about 380 keV, for example.
  • the implantation region 21 and the guard rings 11 are simultaneously formed, and the active region 10 is partitioned.
  • Al, B, Ar or V may be implanted in conditions such as a dose of about 1 ⁇ 10 13 cm ⁇ 2 to 1 ⁇ 10 15 cm ⁇ 2 and acceleration energy of about 30 keV to 100 keV, for example.
  • a p-type impurity (Al in this embodiment) is implanted from the surface 9 of the epitaxial layer 8 into the epitaxial layer 8 by employing an SiO 2 mask 34 having openings in regions for forming the body contact regions 14 , as shown in FIG. 3E . While the implantation conditions at this time vary with the type of the p-type impurity, the dose is about 3.7 ⁇ 10 15 cm ⁇ 2 and acceleration energy is in four stages in the range of 30 keV to 180 keV, for example. Thus, the body contact regions 14 are formed.
  • the epitaxial layer 8 is annealed at 1400° C. to 2000° C. for 2 to 10 minutes, for example, as shown in FIG. 3F .
  • ions of the individual n-type impurities and p-type impurities implanted into the surface layer portion of the epitaxial layer 8 are activated.
  • the annealing of the epitaxial layer 8 can be performed by controlling a resistance heating furnace or a high-frequency induction heating furnace at a proper temperature, for example.
  • the surface 9 of the epitaxial layer 8 is so thermally oxidized that the gate insulating film 19 covering the whole area of the surface 9 is formed, as shown in FIG. 3G .
  • a polysilicon material 35 is deposited on the epitaxial layer 8 by CVD while introducing a p-type impurity (B (boron) in this embodiment), as shown in FIG. 3H .
  • portions other than the gate electrode 20 are removed by dry etching, as shown in FIG. 3I .
  • the gate electrode 20 is formed.
  • the interlayer dielectric film 25 made of SiO 2 is stacked on the epitaxial layer 8 by CVD, as shown in FIG. 3J .
  • the interlayer dielectric film 25 and the gate insulating 19 are so continuously patterned that the contact holes 26 are formed, as shown in FIG. 3K .
  • Ti, TiN and Al are successively sputtered on the interlayer dielectric film 25 to form the source electrode 27 , for example. Further, Ti, Ni, Au and Ag are successively sputtered on the back surface 7 of the SiC substrate 5 , so that the drain electrode 30 is formed.
  • the interlayer insulating film (not shown), the source pad 2 , the gate pad 4 and the like are formed, whereby the semiconductor device 1 shown in FIG. 2( b ) is obtained.
  • annular channels are formed in the peripheral edge portions of the body regions 12 of each unit cell by applying drain voltage between the source pad 2 (the source electrode 27 ) and the drain electrode 30 (between the source and the drain) and applying prescribed voltage (voltage of not more than gate threshold voltage) to the gate pad 4 (the gate electrode 20 ) in a state grounding the source pad 2 (i.e., the source electrode 27 is at 0 V).
  • drain voltage between the source pad 2 (the source electrode 27 ) and the drain electrode 30 (between the source and the drain) and applying prescribed voltage (voltage of not more than gate threshold voltage) to the gate pad 4 (the gate electrode 20 ) in a state grounding the source pad 2 (i.e., the source electrode 27 is at 0 V).
  • the drain voltage is 900 V
  • equipotential surfaces of 900 V are distributed around the back surface 7 of the SiC substrate 5 in contact with the drain electrode 30 and a voltage drop is caused from the back surface 7 of the Si substrate 5 toward the surface 9 of the epitaxial layer 8
  • equipotential surfaces of about several 10 V are distributed in the interbody regions 16 . Therefore, an extremely large electric field directed toward the gate electrode 20 is generated in the interbody regions 16 .
  • the implantation region 21 of the reverse conductivity type (the p ⁇ -type) to the drift region 13 is formed over the whole areas of the interbody regions 16 . Therefore, depletion layers resulting from junction (p-n junction) between the implantation region 21 and the drift region 13 can be generated on the whole areas of the interbody regions 16 .
  • the equipotential surfaces of high potential with reference to the gate electrode 20 can be lowered toward the side of SiC substrate 5 and separated from the gate insulating film 19 , due to the presence of the depletion layers. Consequently, the electric field applied to the gate insulating film 19 can be reduced.
  • dielectric breakdown of the gate insulating film 19 can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between the source and the drain, and further in practical use. Therefore, the semiconductor device 1 excellent in withstand voltage can be manufactured with a high yield.
  • the body regions 12 are in the form of the matrix and the interbody regions 16 are formed in the latticed manner, a particularly strong electric field is easily generated in the intersectional region 18 surrounded by the respective corners of the four body regions 12 arrayed in two rows and two columns.
  • the implantation region 21 (the intersectional portion 22 ) larger than the intersectional region 18 is formed on the intersectional region 18 , and the intersectional portion 22 enters the respective corners of the body regions 12 . Therefore, dielectric breakdown of portions of the gate insulating film 19 opposed to the intersectional regions 18 can be effectively suppressed.
  • the implantation region 21 (the linear portions 23 ) is formed not only on the intersectional regions 18 but also on the line regions 17 , whereby dielectric breakdown of portions of the gate insulating film 19 opposed to the line regions 17 can also be effectively suppressed. As a result of these, the electric field applied to the gate insulating film 19 can be uniformly relaxed.
  • the implantation region 21 may be formed only on the line regions 17 .
  • the implantation region 21 formed on the line regions 17 may not necessarily be linear, but may be in the form of a polygon such as a square or a triangle, for example.
  • the linear portions 23 of the implantation region 21 may not be integral with the intersectional portions 22 , but linear portions 38 of an implantation region 36 may be so formed that both longitudinal ends thereof separate from respective sides of intersectional portions 37 , as shown in FIG. 4( a ), for example.
  • the plane shape of the body regions 12 may not be square, but may be in the form of a regular hexagon, as in body regions 39 shown in FIG. 5( a ), for example.
  • An array pattern of the body regions 39 in this case is such a honeycomb pattern that the body regions 39 are so arrayed that single sides of adjacent body regions 39 are parallel to one another, for example.
  • Regions (interbody regions 40 ) between the respective ones of the body regions 39 arrayed in the honeycomb pattern are in the form of a honeycomb having a constant width.
  • the interbody regions 40 include line regions 41 linearly extending between the respective ones of the adjacent body regions 39 along six side surfaces of each body region 39 and intersectional regions 42 where three line regions 41 radially intersect with one another.
  • An implantation region 43 is in the form of a honeycomb formed over the whole area of the honeycomb region, for example, and integrally includes intersectional portions 44 (portions formed on the intersectional regions 42 ) and linear portions 45 (portions formed on the line regions 41 ).
  • the plane shape of the body regions 12 arrayed in the form of the matrix may be circular, as in body regions 46 shown in FIG. 6 , for example.
  • the array pattern of the body regions 12 may not necessarily be the matrix pattern, but may be a zigzag array pattern, as shown in FIG. 7 , for example. More specifically, body regions 12 square-shaped in plan view form a plurality of columns, and are arranged at a constant pitch in a column direction Y in each column. In two columns adjacent to each other in a row direction X orthogonal to the column direction Y, body regions 12 forming one of the columns and body regions 12 forming the other column have positional relation deviating from one another by half the pitch (half the pitch at which the body regions 12 are arranged in the column direction).
  • a region (an interbody region 47 ) between each pair of body regions 12 in the zigzag array pattern integrally includes a first line region 48 linearly extending between two adjacent columns of body regions 12 along the column direction Y, a second line region 49 linearly extending between the respective ones of the body regions 12 of each column along the row direction X, and an intersectional region 50 where the first line region 48 and the second line region 49 intersect with each other in a T-shaped manner.
  • An implantation region 51 is formed over the whole area of the interbody region 47 , for example, and integrally includes an intersectional portion 52 (a portion formed on the intersectional region 50 ) and a linear portion 53 (a portion formed on the first line region 48 and the second line region 49 ).
  • intersectional portion 52 is provided on the intersection point (i.e., a point on the intersection point of a T-shaped path) between the two straight lines 54 a and 54 b.
  • the plane shape of the body regions 12 may be an elongational shape.
  • the plane shape may be oblong, as in body regions 55 shown in FIGS. 8( a ) and 8 ( b ).
  • the oblong body regions 55 are arrayed at a constant pitch so that the long sides of body regions 55 adjacent to each other are parallel to each other, for example.
  • a body contact region 56 is formed on a central portion thereof, and a source region 57 is formed to surround the body contact region 56 .
  • the body contact region 56 has an oblong shape similar to that of the body region 55 in plan view.
  • the source region 57 is in the form of a rectangular ring in plan view.
  • Regions (interbody regions 58 ) between the respective ones of the body regions 55 arrayed in this manner are in the form of lines linearly extending between the respective ones along the longitudinal direction of the body regions 55 .
  • One implantation region 59 is provided every linear interbody region 58 , and in the form of a straight line along the longitudinal direction.
  • Each implantation region 59 includes a pair of end portions 60 formed on both longitudinal end portions thereof and a linear portion 61 linking the pair of end portion regions with each other.
  • Each end portion 60 of the implantation region 59 is in the form of a rectangle in plan view, and two corners thereof closer to the body region 55 enter corners of the body region 55 respectively.
  • the linear portion 61 is formed with a constant width at an interval from a side surface of the body region 55 .
  • the plane shape of the elongational body regions 12 may be a shape partitioned by meandering lines each formed by coupling a plurality of arcuate portions 63 with one another, as in body regions 62 shown in FIG. 9 , for example.
  • two body contact regions 56 may be formed on each body region 62 at an interval from each other in the longitudinal direction of the body regions 62 .
  • the plane shape of the elongational body regions 12 may be a shape partitioned by meandering lines each formed by coupling a plurality of bent portions 65 with one another, as in body regions 64 shown in FIG. 10 , for example.
  • Each bent portion 65 has a shape bent toward one side in the width direction at an interior angle of 120 degrees with respect to a portion extending in the longitudinal direction of the body regions 64 , extending in the longitudinal direction, and bent toward another side in the width direction at an interior angle of 120 degrees with respect to the portion extending in the longitudinal direction.
  • two body contact regions 14 may be formed on each body region 64 at an interval from each other in the longitudinal direction of the body region 64 .
  • FIGS. 11( a ) and 11 ( b ) are schematic plan views of a semiconductor device according to a second embodiment of the present invention, while FIG. 11( a ) shows a general diagram and FIG. 11( b ) shows an enlarged internal diagram respectively.
  • FIGS. 12( a ) and 12 ( b ) are schematic sectional views of the semiconductor device according to the second embodiment of the present invention, while FIG. 12( a ) shows a cutting plane along a cutting plane line XIIa-XIIa in FIG. 11( b ) and FIG. 12( b ) shows a cutting plane along a cutting plane line XIIb-XIIb in FIG. 11( b ) respectively.
  • FIGS. 11( a ) and 11 ( b ) and FIGS. 12( a ) and 12 ( b ) portions corresponding to the respective portions shown in the aforementioned FIG. 1 and the like are denoted by the same reference signs.
  • the thickness of a gate insulating film is not uniform, but the gate insulating film 67 integrally includes a relatively thick thick-film portion 68 as a field relaxation portion opposed to latticed interbody regions 16 and a relatively thin thin-film portion 69 opposed to body regions 12 surrounded by sides of the lattice of the interbody regions 16 .
  • the thick-film portion 68 is in the form of a lattice surrounding the body regions 12 in plan view along the interbody regions 16 , and integrally includes intersectional portions 70 opposed to intersectional regions 18 and linear portions 71 as linear field relaxation portions opposed to line regions 17 .
  • the thickness of the thick-film portion 68 is 1000 ⁇ to 3000 ⁇ , for example.
  • intersectional portion 70 is in the form of a square slightly smaller than the intersectional region 18 in plan view, and respective corners thereof are opposed to corners of four body regions 12 facing the intersectional region 18 at intervals respectively.
  • the intersectional region 70 may overlap with the body region 12 in plan view.
  • Each linear portion 71 is in the form of a straight line linking centers of respective sides of intersectional portions 70 adjacent to each other in plan view, and at an interval not to overlap with a peripheral edge portion of the body region 12 .
  • the thin-film portion 69 extends from the latticed thick-film portion 68 surrounding the body regions 12 in plan view toward the side of the body regions 12 with a constant width, and covers the peripheral edge portions of the body regions 12 and outer peripheral edges of source regions.
  • the thickness of the thin-film portion 69 is 350 ⁇ to 1000 ⁇ , for example.
  • the remaining structure is similar to the case of the aforementioned first embodiment.
  • FIGS. 13A to 13K are schematic sectional views for illustrating a method of manufacturing the semiconductor device shown in FIG. 12( b ).
  • steps similar to the steps shown in FIGS. 3A to 3F are carried out so that the body regions 12 , source regions 15 and body contact regions 14 are formed on an epitaxial layer 8 as shown in FIGS. 13A to 13E , for example, and impurities implanted into these regions are activated by heat treatment.
  • a mask (not shown) having openings in regions (regions opposed to the interbody regions 16 ) for forming the thick-film portion 68 is formed on a surface 9 of the epitaxial layer 8 .
  • oxide films 72 are formed only on the regions for forming the thick-film portion 68 , as shown in FIG. 13F .
  • the surface 9 of the epitaxial layer 8 is thermally oxidized in the state where the oxide films 72 are formed, whereby the portions where the oxide films 72 are formed are so relatively thickened that the thick-film portion 68 is formed while the thin-film portion 69 is so formed on the remaining portions that the gate insulating film 67 is formed, as shown in FIG. 13G .
  • steps similar to the steps shown in FIGS. 3H to 3K are carried out as shown in FIGS. 13H to 13K , so that a gate electrode 20 and an interlayer dielectric film 25 are formed on the gate insulating film 67 .
  • a source electrode 27 , a drain electrode 30 , a source pad 2 and a gate pad 4 etc. are formed, whereby the semiconductor device 66 shown in FIG. 12( b ) is obtained.
  • annular channels are formed in the peripheral edge portions of the body regions 12 of each unit cell by applying drain voltage between the source pad 2 (the source electrode 27 ) and the drain electrode 30 (between a source and a drain) and applying prescribed voltage (voltage of not less than gate threshold voltage) to the gate pad 4 (the gate electrode 20 ) in a state grounding the source pad 2 (i.e., the source electrode 27 is at 0 V).
  • drain voltage between the source pad 2 (the source electrode 27 ) and the drain electrode 30 (between a source and a drain) and applying prescribed voltage (voltage of not less than gate threshold voltage) to the gate pad 4 (the gate electrode 20 ) in a state grounding the source pad 2 (i.e., the source electrode 27 is at 0 V).
  • the drain voltage is 900 V
  • equipotential surfaces of 900 V are distributed around a back surface 7 of an SiC substrate 5 in contact with the drain electrode 30 and a voltage drop is caused from the back surface 7 of the Si substrate 5 toward the surface 9 of the epitaxial layer 8
  • equipotential surfaces of about several 10 V are distributed in the interbody regions 16 . Therefore, a large electric field directed toward the gate electrode 20 is generated in the interbody regions 16 .
  • the portion opposed to the interbody regions 16 is increased in thickness as the thick-film portion 68 in the gate insulating film 67 .
  • dielectric breakdown voltage of the portion (the thick-film portion 68 ) can be rendered greater than that of the remaining portion (the thin-film portion 69 ).
  • the thick-film portion 68 does not dielectrically break down, but can relax the applied electric field therein. Therefore, dielectric breakdown of the gate insulating film 19 can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between the source and the drain and further in practical use. Therefore, the semiconductor device 66 excellent in withstand voltage can be manufactured with a high yield.
  • the thick-film portion 68 (the intersectional portions 70 ) is formed on the portion opposed to the intersectional regions 18 where a particularly strong electric field is easily generated. Therefore, dielectric breakdown of the portion of the gate insulating film 67 opposed to the intersectional regions 18 can be effectively suppressed.
  • the thick-film portion 68 (the linear portions 71 ) is formed not only on the portion opposed to the intersectional regions 18 but also on a portion opposed to the line regions 17 , whereby dielectric breakdown of the portion of the gate insulating film 67 opposed to the line regions 17 can also be effectively suppressed. Consequently, the electric field applied to the gate insulating film 67 can be uniformly relaxed.
  • a portion of the gate insulating film 67 opposed to the peripheral edge portions of the body regions 12 is the thin-film portion 69 , whereby the electric field generated by applying the voltage to the gate electrode 20 in order to form the channels in the peripheral edge portions of the body regions 12 can be inhibited from weakening in the gate insulating film 67 . Therefore, reduction of a transistor function of the semiconductor device 66 can be suppressed.
  • the plane shape of the body regions 12 and the array pattern of the body regions 12 can be properly changed. While illustration is omitted, the plane shape of the body regions 12 may be in the form of a regular hexagon, a circle or an oblong, for example. Further, the array pattern of the body regions 12 may be a honeycomb pattern, a zigzag array pattern or the like.
  • the thick-film portion 68 has been formed by CVD by depositing an insulating material only on the interbody regions 16 after thermally oxidizing the surface 9 of the epitaxial layer 8 in the above description
  • the thick-film portion 68 can also be formed by forming an insulating film on the whole area of the surface 9 of the epitaxial layer 8 by thermal oxidation so that the film thickness is greater than a normal one and thereafter etching only the portion (the region for forming the thin-film portion 69 ) other than the region for forming the thick-film portion 68 , for example.
  • the thick-film portion 68 can also be formed by rendering the impurity concentration in the interbody regions 16 of the epitaxial layer 8 greater than the concentration in the remaining portion and increasing only the rate of oxidation in the interbody regions 16 .
  • only the insulating film on the interbody regions 16 can be rapidly grown to be increased in thickness while the remaining portion can be slowly grown to be reduced in thickness, whereby the thick-film portion 68 and the thin-film portion 69 can be formed through only one thermal oxidation step.
  • FIGS. 14( a ) and 14 ( b ) are schematic plan views of a semiconductor device according to a third embodiment of the present invention, while FIG. 14( a ) shows a general diagram and FIG. 14( b ) shows an enlarged internal diagram respectively.
  • FIGS. 15( a ) and 15 ( b ) are schematic sectional views of the semiconductor device according to the third embodiment of the present invention, while FIG. 15( a ) shows a cutting plane line along a cutting plane line XVa-XVa in FIG. 14( b ) and FIG. 15( b ) shows a cutting plane along a cutting plane line XVb-XVb in FIG. 14( b ) respectively.
  • FIGS. 14( a ) and 14 ( b ) and FIGS. 15( a ) and 15 ( b ) portions corresponding to the respective portions shown in the aforementioned FIG. 1 and the like are denoted by the same reference signs.
  • a large number of through-holes 74 are formed in a gate electrode 20 by removing portions of the gate electrode 20 opposed to respective intersectional regions 18 of interbody regions 16 .
  • each through-hole 74 is in the form of a square having sides smaller than the width of the gate electrode 20 on each intersectional portion of the latticed gate electrode 20 having a constant width in plan view.
  • the lattice of the gate electrode 20 can be rendered continuous without cutting the same around the through-hole 74 by reducing each side of the through-hole 74 below the width of the gate electrode 20 .
  • the through-hole 74 is provided on the intersection point between the two straight lines 24 a and 24 b (may be the intersection point between 24 a and 24 c or the intersection point between 24 b and 24 c ) among these straight lines.
  • An interlayer dielectric film 25 covering the gate electrode 20 enters each through-hole 74 as an embedded portion 75 . It follows that the embedded portion 75 is opposed to an intersectional region 18 of an interbody region 16 through a gate insulating film 19 .
  • the remaining structure is similar to the case of the aforementioned first embodiment.
  • FIGS. 16A to 16K are schematic sectional views for illustrating a method of manufacturing the semiconductor device shown in FIG. 15( b ).
  • steps similar to the steps shown in FIGS. 3A to 3G are carried out so that the body regions 12 , source regions 15 and body contact regions 14 are formed on an epitaxial layer 8 as shown in FIGS. 16A to 16F , for example, and impurities implanted into these regions are activated by heat treatment so that the gate insulating film 19 is formed.
  • a resist pattern 76 having openings in regions for forming the gate electrode 20 is formed, as shown in FIG. 16G .
  • regions for forming the through-holes 74 are covered with the resist pattern 76 .
  • a polysilicon material 77 is deposited from above the epitaxial layer 8 by CVD while introducing a p-type impurity (B (boron) in this embodiment), as shown in FIG. 16H .
  • the resist pattern 76 is so removed that unnecessary portions (portions other than the gate electrode 20 ) of the polysilicon material 77 are lifted off along with the resist pattern 76 , as shown in FIG. 16I .
  • the gate electrode 20 having the through-holes 74 is formed.
  • an interlayer dielectric film 25 made of SiO 2 is formed on the epitaxial layer 8 by CVD, as shown in FIG. 16J .
  • the interlayer dielectric film 25 is partially embedded in the through-holes 74 of the gate electrode 20 .
  • the interlayer dielectric film 25 and the gate insulating film 19 are so continuously patterned that contact holes 26 are formed, as shown in FIG. 16K .
  • Ti, TiN and Al are successively sputtered on the interlayer dielectric film 25 so that a source electrode 27 is formed, for example. Further, Ti, Ni, Au and Ag are successively sputtered on a back surface 7 of an SiC substrate 5 , so that a drain electrode 30 is formed.
  • annular channels are formed in peripheral edge portions of the body regions 12 of each unit cell by applying drain voltage between the source pad 2 (the source electrode 27 ) and the drain electrode 30 (between a source and a drain) and applying prescribed voltage (voltage of not less than gate threshold voltage) to the gate pad 4 (the gate electrode 20 ) in a state grounding the source pad 2 (i.e., the source electrode 27 is at 0 V), similarly to the first embodiment.
  • drain voltage between the source pad 2 (the source electrode 27 ) and the drain electrode 30 (between a source and a drain) and applying prescribed voltage (voltage of not less than gate threshold voltage) to the gate pad 4 (the gate electrode 20 ) in a state grounding the source pad 2 (i.e., the source electrode 27 is at 0 V), similarly to the first embodiment.
  • the drain voltage is 900 V
  • equipotential surfaces of 900 V are distributed around a back surface 7 of an SiC substrate 5 in contact with the drain electrode 30 and a voltage drop is caused from the back surface 7 of the Si substrate 5 toward the surface 9 of the epitaxial layer 8
  • equipotential surfaces of about several 10 V are distributed in the interbody regions 16 . Therefore, a large electric field directed toward the gate electrode 20 is generated in the interbody regions 16 .
  • the through-holes 74 are formed in portions of the gate electrode 20 opposed to the respective intersectional regions 18 where a particularly strong electric field is easily generated, and part (embedded portion 75 ) of the interlayer dielectric film 25 enters each through-hole 74 . Therefore, it follows that portions of the gate insulating film 19 opposed to the interbody regions 16 are interposed between the epitaxial layer 8 and the insulating embedded portions 75 . Even if an electric field results from the potential difference between the gate electrode 20 and the epitaxial layer 8 , therefore, the electric field can be rendered hardly applicable to the portions of the gate insulating film 19 opposed to the interbody regions 16 .
  • the through-holes 74 may be formed in portions opposed to line regions. Further, the through-holes 74 may not necessarily be square-shaped, but may be triangular, circular or the like.
  • the plane shape of the body regions 12 may not be square, but may be in the form of a regular hexagon, as in body regions 78 shown in FIG. 17 , for example.
  • the array pattern of the body regions 78 in this case is such a honeycomb pattern that the body regions 78 are so arrayed that single sides of adjacent body regions 78 are parallel to one another, for example.
  • Regions (interbody regions 79 ) between the respective ones of the body regions 78 arrayed in the honeycomb pattern are in the form of a honeycomb having a constant width.
  • Each interbody region 79 includes a line region 80 linearly extending between the respective ones of the adjacent body regions 78 along six side surfaces of each body region 78 and an intersectional region 81 where three line regions 80 radially intersect with one another.
  • through-holes 74 can be formed in portions of a gate electrode 20 opposed to the intersectional regions 81 of the honeycomb interbody regions 79 , for example.
  • the plane shape of body regions 82 may be in the form of an elongational oblong, as in the body regions 82 shown in FIG. 18 , for example.
  • the oblong body regions 82 are arrayed at a constant pitch so that the long sides of body regions 82 adjacent to one another are parallel to one another, for example.
  • a body contact region 83 is formed on a central portion thereof, and a source region 84 is formed to surround the body contact region 83 .
  • the body contact region 83 is in the form of an oblong similar to the body region 82 in plan view.
  • the source region 84 is in the form of a rectangular ring in plan view.
  • Regions (interbody regions 85 ) between the respective ones of the body regions 82 arrayed in this manner are in the form of lines linearly extending between the respective ones along the longitudinal direction of the body regions 82 .
  • through-holes 74 are formed in the form of grooves (through-grooves 86 ) linearly extending along the interbody regions 85 , by removing portions of a gate electrode 20 opposed to the interbody regions 85 , for example.
  • FIG. 19 is an enlarged sectional view of a principal portion of a semiconductor device according to a fourth embodiment of the present invention, and shows a section corresponding to FIG. 2( a ).
  • portions corresponding to the respective portions shown in the aforementioned FIG. 1 and the like are denoted by the same reference signs.
  • a High-k (high dielectric constant) material is employed for a portion of a gate insulating film 88 opposed to an interbody region 16 .
  • the High-k material is an insulating material whose dielectric constant is higher than that of SiO 2 , and HfO 2 (hafnium oxide), ZrO 2 (zirconium oxide), HfSiO (hafnium silicate), SiON, SiN, Al 2 O 3 or AlON can be listed, for example.
  • the gate insulating film 88 has an SiO 2 film 89 as a low dielectric constant portion whose dielectric constant is relatively low and a High-k film 90 as a high dielectric constant portion whose dielectric constant is relatively high.
  • the SiO 2 film 89 is formed on a surface 9 of an epitaxial layer 8 , has an opening 91 in a portion opposed to the interbody region 16 , and is opposed to peripheral edge portions of body regions 12 and outer peripheral edges of source regions 15 .
  • the High-k film 90 is stacked on the SiO 2 film 89 , and part thereof fills up the opening 91 of the SiO 2 film 89 .
  • the gate insulating film 88 having such a two-layer structure that the SiO 2 film 89 and the High-k film 90 are successively stacked from the surface 9 of the epitaxial layer 8 is formed in FIG. 19 .
  • the gate insulating film 88 can be formed by thermally oxidizing the surface 9 of the epitaxial layer 8 following the step shown in FIG. 3G thereby forming the SiO 2 film 89 , then forming the opening 91 in the SiO 2 film 89 by etching, and thereafter stacking the High-k material by CVD, for example.
  • a portion of the gate insulating film 88 opposed to the interbody region 16 is the High-k film 90 .
  • dielectric breakdown voltage of the portion (the High-k film 90 ) in the gate insulating film 88 can be rendered greater than that of the remaining portion (the SiO 2 film 89 ).
  • the High-k film 90 does not dielectrically break down, but can relax the applied electric field therein. Therefore, dielectric breakdown of the gate insulating film 88 can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between a source and a drain and further in practical use. Therefore, the semiconductor device 87 excellent in withstand voltage can be manufactured with a high yield.
  • a single-layer structure of an SiO 2 film 92 may be employed as a substrate of a gate insulating film 88 , and a High-k film 93 may not be stacked on the SiO 2 film 92 but may simply be embedded in an opening 91 of the SiO 2 film 92 , as shown in FIG. 20 , for example.
  • a High-k film 93 may not be stacked on the SiO 2 film 92 but may simply be embedded in an opening 91 of the SiO 2 film 92 , as shown in FIG. 20 , for example.
  • the gate insulating film 88 may be in a structure having a High-k film 95 formed on a surface 9 of an interbody region 16 and an SiO 2 film 94 stacked on an epitaxial layer 8 to cover the High-k film 95 , as shown in FIG. 21 .
  • FIG. 22 is an enlarged sectional view of a principal portion of a semiconductor device according to a fifth embodiment of the present invention, and shows a section corresponding to FIG. 2( a ).
  • portions corresponding to the respective portions shown in the aforementioned FIG. 1 and the like are denoted by the same reference signs.
  • a semiconductor device 96 according to the fifth embodiment only an interbody region 97 of an epitaxial layer 8 is enlarged toward the side of a gate insulating film 19 .
  • the interbody region 97 has a protrusion 98 projecting from a surface 9 of the epitaxial layer 8 to be raised with respect to the surface 9 of the epitaxial layer 8 .
  • the conductivity type of the protrusion 98 As the conductivity type of the protrusion 98 , the conductivity type (n ⁇ -type) of the epitaxial layer 8 is maintained.
  • the gate insulating film 19 is formed on the surface 9 of the epitaxial layer 8 to cover the protrusion 98 .
  • the protrusion 98 can be formed by forming the epitaxial layer 8 following the step shown in FIG. 3A , thereafter forming a mask (not shown) covering only a region for forming the protrusion 98 , and etching an unnecessary portion (a portion other than the protrusion 98 ) of the epitaxial layer 8 through the mask, for example.
  • the protrusion 98 is so provided on the interbody region 97 that the distance from a back surface 7 of an SiC substrate 5 up to the gate insulating film 19 lengthens by the quantity of projection of the protrusion 98 in the interbody region 97 . Therefore, voltage applied to a drain electrode 30 can be further dropped before the same is applied to the gate insulating film 19 as compared with a case where no protrusion 98 is present. Therefore, voltage of equipotential surfaces distributed immediately under the gate insulating film 19 in the interbody region 97 can be reduced. Consequently, an electric field applied to the gate insulating film 19 can be relaxed.
  • the conductivity type of the epitaxial layer 8 may not necessarily be maintained as the conductivity type of the protrusion 98 , but a p ⁇ -type may be employed, as shown in FIG. 23 , for example.
  • a depletion layer resulting from junction (p-n junction) between the protrusion 98 and a drift region 13 can be generated in the interbody region 97 .
  • equipotential surfaces of potential with reference to a gate electrode 20 can be lowered toward the side of an SiC substrate 5 and separated from the gate insulating film 19 , due to the presence of the depletion layer. Consequently, the electric field applied to the gate insulating film 19 can be further reduced.
  • the protrusion 98 is formed by first forming the epitaxial layer 8 following the step shown in FIG. 3A , thereafter forming a mask (not shown) covering only a region for forming the protrusion 98 and etching an unnecessary portion (a portion other than the protrusion 98 ) of the epitaxial layer 8 through the mask, for example.
  • the p ⁇ -type protrusion 98 can be formed by forming a sidewall on the protrusion 98 after the formation of the protrusion 98 and thereafter implanting a p-type impurity also into the protrusion 98 in the step shown in FIG. 3B .
  • a gate insulating film may have an SiO 2 film and a High-k film, similarly to the fourth embodiment.
  • a gate insulating film 99 may have an SiO 2 film 101 formed on a surface 9 of an epitaxial layer 8 , having an opening 100 exposing a protrusion 98 and opposed to peripheral edge portions of body regions 12 and outer peripheral edges of source regions 15 and a High-k film 102 stacked on the SiO 2 film 101 and formed to cover the protrusion 98 exposed from the opening 100 of the SiO 2 film 101 , as shown in FIG. 24 .
  • a High-k film 103 may not be stacked on an SiO 2 film 104 , but may be formed to cover a protrusion 98 exposed from an opening 105 of the SiO 2 film 104 , as shown in FIG. 25 .
  • a gate insulating film 99 may be in a structure having a High-k film 106 formed to cover a protrusion 98 and an SiO 2 film 107 stacked on an epitaxial layer 8 to cover the High-k film 106 , as shown in FIG. 26 .
  • portions of the gate insulating films 99 opposed to the protrusions 98 are the High-k films 102 , 103 and 106 .
  • dielectric breakdown voltage of these portions (the High-k films 102 , 103 and 106 ) in the gate insulating films 99 can be rendered greater than that of the remaining portions (the SiO 2 films). Therefore, electric fields applied to the gate insulating films 99 can be further relaxed.
  • a structure inverting the conductivity type of each semiconductor portion of each of the aforementioned semiconductor devices may be employed.
  • the p-type portions may be of the n-type, and the n-type portions may be of the p-type.
  • the present invention is also applicable to a power semiconductor device employing Si, for example.
  • the implantation region 21 in the first embodiment may be deeper than body regions 12 , as shown in a semiconductor device 110 of FIG. 27 , for example.
  • a semiconductor device 111 shown in FIG. 28 can be prepared by combining the components of the semiconductor device 1 according to the first embodiment shown in FIGS. 2( a ) and 2 ( b ) and the components of the semiconductor device 66 according to the second embodiment shown in FIGS. 12( a ) and 12 ( b ) with one another.
  • FIGS. 28 portions corresponding to the respective portions shown in FIGS. 2( a ) and 2 ( b ), FIGS. 12( a ) and 12 ( b ) etc. are denoted by the same reference signs.
  • a semiconductor device 112 shown in FIG. 29 can be prepared by combining the components of the semiconductor device 1 according to the first embodiment shown in FIGS. 2( a ) and 2 ( b ) and the components of the semiconductor device 73 according to the third embodiment shown in FIGS. 15( a ) and 15 ( b ) with one another.
  • FIG. 29 portions corresponding to the respective portions shown in FIGS. 2( a ) and 2 ( b ), FIGS. 15( a ) and 15 ( b ) etc. are denoted by the same reference signs.
  • a semiconductor device 113 shown in FIG. 30 can be prepared by combining the components of the semiconductor device 1 according to the first embodiment shown in FIGS. 2( a ) and 2 ( b ) and the components of the semiconductor device 87 according to the fourth embodiment shown in FIG. 19 with one another.
  • portions corresponding to the respective portions shown in FIGS. 2( a ) and 2 ( b ), FIG. 19 etc. are denoted by the same reference signs.
  • the semiconductor device can be built into a power module employed for an inverter circuit constituting a driving circuit for driving an electric motor utilized as a power source for an electric automobile (including a hybrid car), a train, an industrial robot or the like, for example. Further, the same can also be built into a power module employed for an inverter circuit converting power generated by a solar cell, a wind turbine generator or still another power generator (particularly a private power generator) to match with power of a commercial power supply.
  • 22 semiconductor devices 1 in total each having the structure shown in FIG. 1 were prepared following the steps shown in FIGS. 3A to 3K (Example 1). 22 semiconductor devices in total were prepared by a method similar to that for Example 1, except that no implantation regions were formed.
  • An HTRB test was conducted on the 22 semiconductor devices and the 22 semiconductor devices obtained according to Example 1 and comparative example 1 respectively. Conditions of the HTRB test were set identical (150° C./150 hours/600 V bias) as to all semiconductor devices.
  • interbody region 41 . . . line region, 42 . . . intersectional region, 43 . . . implantation region, 44 . . . intersectional portion, 45 . . . linear portion, 46 . . . body region, 47 . . . interbody region, 48 . . . first line region, 49 . . . second line region, 50 . . . intersectional region, 51 . . . implantation region, 52 . . . intersectional portion, 53 . . . linear portion, 54 . . . straight line, 55 . . . body region, 57 . . . source region, 59 . . . implantation region, 60 . .
  • SiO 2 film 102 . . . High-k film, 103 . . . High-k film, 104 . . . SiO 2 film, 106 . . . High-k film, 107 . . . SiO 2 film, 110 . . . semiconductor device, 111 . . . semiconductor device, 112 . . . semiconductor device, 113 . . . semiconductor device

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US16/905,440 Pending US20200321451A1 (en) 2010-03-30 2020-06-18 Semiconductor device having a gate insulating film having a high dielectric constant portion for relaxing an electric field generated in the gate insulating film
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US20200321451A1 (en) 2020-10-08
US20170092743A1 (en) 2017-03-30
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US20240170558A1 (en) 2024-05-23
EP3651206B1 (de) 2022-04-27
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