US20060158948A1 - Memory device - Google Patents

Memory device Download PDF

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Publication number
US20060158948A1
US20060158948A1 US11/333,344 US33334406A US2006158948A1 US 20060158948 A1 US20060158948 A1 US 20060158948A1 US 33334406 A US33334406 A US 33334406A US 2006158948 A1 US2006158948 A1 US 2006158948A1
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Prior art keywords
state
memory
cells
cell
memory device
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Abandoned
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US11/333,344
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English (en)
Inventor
Yukio Fuji
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Micron Memory Japan Ltd
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Elpida Memory Inc
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Assigned to ELPIDA MEMORY, INC reassignment ELPIDA MEMORY, INC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJI, YUKIO
Publication of US20060158948A1 publication Critical patent/US20060158948A1/en
Priority to US12/207,077 priority Critical patent/US7580277B2/en
Priority to US12/500,673 priority patent/US7751227B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Definitions

  • This invention relates to a memory with a programmable resistor element (phase change memory).
  • a phase change memory is a non-volatile memory taking advantage of characteristics e.g. of a chalcogenide material, such as Ge, Sb or Te that, when the chalcogenide material is heated, it takes on an amorphous state (high resistance)/crystalline state (low resistance).
  • a chalcogenide material such as Ge, Sb or Te
  • the material undergoes a transition between the high resistance (reset) state and the low resistance (set) state, by the Joule's heat, generated by the electric current, depending on the time duration of current application.
  • the write time on the order of tens to about one hundred nanoseconds is said to be necessary.
  • the number of times of repeated write operations is on the order of 10 12 , which is of the same order of magnitude as that of the FLASH memory (electrically programmable erasable non-volatile memory) and lower by about four orders of magnitude than that of the DRAM (dynamic random access memory).
  • phase change memory With the phase change memory, there is a possibility that device characteristics are deteriorated to destruct stored data with increase in the number of times of repetition of read/write operations.
  • Patent Document 1 U.S. Pat. No. 6,646,902B2
  • Patent Document 2 U.S. Pat. No. 6,560,155B1
  • An example disclosed in Patent Document 1 U.S. Pat. No. 6,646,902B2 is now briefly described with reference to FIG. 11 .
  • the programmable resistor element, used in this technique is of a structure comprised of a silver (Ag) containing solid electrolyte 1103 , as an example, sandwiched between an upper electrode 1101 and a lower electrode 1102 .
  • the possible retention time of the programmed state is on the order of hours or days. Although the retention time is longer than with the DRAM, the retention characteristic is inferior as compared to that of the normal FLASH memory. With this in view, a proposal is made for applying a voltage V 2 which would not cause disturbances as compared to the voltage VI at the time of programming (about 35 to 60% of VI) for improving the retention characteristic.
  • Patent Document 2 U.S. Pat. No. 6,560,155B1
  • Patent Document 1 U.S. Pat. No. 6,646,902B2
  • the inner refresh timing of a DRAM is delayed by a delay circuit, and a voltage is periodically applied to improve retention characteristic as well as to reduce the refresh current and power.
  • phase change device is a non-volatile memory device
  • the resistance value thereof is changed by the voltage and the current applied to the device by read disturbances to cause a change in the resistance value of the phase change device to deteriorate the retention characteristic and the read margin.
  • Patent Document 1 U.S. Pat. No. 6,646,902 (U.S. Pat. No. 6,646,902B2)
  • Patent Document 2 U.S. Pat. No. 6,560,155 (U.S. Pat. No. 6,560,155B1)
  • the number of times of repetitive write operations is on the order of 10 12 , which is of the same order of magnitude as that with the FLASH memory and lower by about four orders of magnitude than that of the DRAM.
  • FIG. 10 shows change and the distribution of the resistance value of a conventional phase change device on write and read, and specifically shows initial reset resistance distribution (RReset), reset resistance distribution after n times of the write operations (Rreset′), initial set resistance distribution (RSset) and set resistance distribution after n times of the write operations (Rset′).
  • the present invention has been completed in view of the above problems. It is an object of the present invention to provide a memory device with improved retention characteristic of a phase change device.
  • phase change memory of the present invention is a DRAM interface compatible memory.
  • reference cells stressed in accordance with the number of times of read and write operations. A change in the resistance value of the reference cells is detected and, if the resistance value have been changed beyond a predetermined reference value (specifically, to a low resistance value), a refresh request is issued to an internal circuit, not shown, to refresh a memory cell and a reference cell transitorily. In this manner, correction is made for variations in the programmed resistance value of the phase change device to assure the margin as well as to improve retention characteristic.
  • the present invention provides a memory device comprising: a memory cell, including a programmable resistance element, at an intersection of a bit line and a word line, and a control circuit managing control for performing a refresh operation of the memory cell responsive to a change in resistance value of the memory cell.
  • changes in the resistance value of the phase change device of a dummy cell of interest, stressed in accordance with the number of times of read and write operations, are detected. If the resistance value of the phase change device of the dummy cell of interest has been changed beyond a predetermined reference value, a refresh request is issued to an internal circuit, and the memory and dummy cells are refreshed in accordance with the refreshing request.
  • the number of times of read of a memory cell of interest, having a phase change device may be counted and, when the number of times of read has reached a preset value, a refresh request may be issued to the internal circuit.
  • first and second reference currents corresponding to first and second states of a memory cell having a phase change device may be compared with the current flowing through the memory cell, and a refresh request may be issued to an internal circuit when a predetermined offset (difference) has been produced in the current flowing through the memory cell to refresh the memory cells based on the refresh request.
  • a method for refreshing in a memory device comprises the steps of:
  • a method for refreshing in a memory device comprises the steps of:
  • the memory device comprises:
  • a data register for holding data read from said memory cell at the time of refreshing
  • a verification amplifier for comparing and detecting the data write state of said memory cell at the time of refreshing
  • said method comprises the steps of
  • setting data of the first state in the verification amplifier adapted for comparing and detecting the data write state in said memory cell; effecting writing to the first state out under verification reading; comparing the current with a predetermined resistance; discontinuing the writing for a cell where a predetermined resistance has been reached; and continuing writing for the other cell;
  • a method for refreshing in a memory device comprises the steps of:
  • the method according to the present invention further comprises the steps of:
  • FIG. 1 is a diagram illustrating the configuration of an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating the circuit configuration of a memory cell and a dummy cell of an embodiment of the present invention.
  • FIG. 3 is a diagram illustrating the circuit configuration of a comparator circuit for monitoring a Set resistance according to an embodiment of the present invention.
  • FIG. 4 is a diagram illustrating the circuit configuration of a comparator circuit for monitoring a Reset resistance according to an embodiment of the present invention.
  • FIG. 5 is a diagram illustrating the circuit configuration of a verification amplifier according to an embodiment of the present invention.
  • FIG. 6 is a diagram illustrating the circuit configuration of a sense amplifier according to an embodiment of the present invention.
  • FIG. 7 shows the result of comparison of the verification current and the sense current according to an embodiment of the present invention.
  • FIG. 8A shows the relation between the change in the device resistance value and the refresh according to an embodiment of the present invention and FIG. 8B shows the relation between the Set/Reset current/verification current of FIG. 8A and the pulse applied.
  • FIG. 9 shows changes in the resistance value of a conventional phase change device in write and read.
  • FIG. 10 shows changes and distribution of resistance value of a conventional phase change device in write and read.
  • FIG. 11 shows the structure of memory cell electrodes and the applied voltage in the memory cell electrode structure of Patent Document 1.
  • FIG. 12 is a diagram illustrating the configuration of a second embodiment of the present invention.
  • FIG. 13 is a diagram illustrating the configuration of a third embodiment of the present invention.
  • FIG. 14A shows the relation between changes in the device resistance value of the second embodiment and the refresh and FIG. 14B shows the relation between FIG. 14A and the Set/Reset current pulses.
  • the memory device includes a reference cell, stressed in accordance with the number of times of the phase change memory cell, and means for detecting a change in the resistance value of the phase change devices constituting the reference cell and issuing a refresh request to an internal circuit in case the resistance value has been changed beyond the set reference value (specifically, to a low resistance value), thereby improving data retention characteristic.
  • a memory includes a memory cell 101 , a sense amplifier 102 for sensing and amplifying data written in the memory cell 101 , a write amplifier 103 for writing data in the memory cell 101 , a data register 105 for retreating and storing data therein, and a verification amplifier 104 for comparing and detecting the state of data written in the memory cell at the refreshing time.
  • the memory also includes a Set dummy cell 109 , having a Set resistance programmed therein, a Reset dummy cell 110 , having a Reset resistance programmed therein, a Set comparator circuit 111 for monitoring the resistance value of the Set dummy cell 109 , and a Reset comparator circuit 112 for monitoring the resistance value of the Reset dummy cell 110 .
  • the memory further includes a refresh request circuit 107 , a write pulse control circuit 106 , and a dummy cell write amplifier 108 .
  • the refresh request circuit 107 decides the presence or absence of a refresh request from the results of comparison in the Set comparator circuit 111 and in the Reset comparator circuit 112 and makes a refresh request to an internal circuit.
  • the write pulse control circuit 106 controls the write pulse at the time of program verification.
  • the dummy cell write amplifier 108 simultaneously performs write operation to the dummy cells at the time of the refresh operation.
  • FIG. 2 shows the circuit configuration of a memory cell, a dummy cell, a sense amplifier and a write amplifier.
  • a plurality of memory cells 101 are arranged in an X/Y matrix configuration.
  • a phase change device schematically shown as a resistor element, is arranged between the source of a memory cell transistor and a bit line.
  • the phase change device is amorphized and presents a high resistance on heating on application of a high voltage plus a short pulse followed by quenching.
  • the high resistance state is termed a ‘Reset’.
  • the phase change device is crystallized and presents a low resistance on being warmed for some time duration with a lower current and a longer pulse length. This low resistance state is termed a ‘Set’.
  • phase change device is changed between the amorphous state and the crystalline state and is thereby changed in its resistance value to effect programming.
  • the Set dummy cell 109 and the Reset memory cell 110 are written to the set state or to the reset state. These cells are arranged in memory cell areas, and have the word lines in common with the memory cells. There are provided bias circuits 302 and 402 , shown in FIGS. 3 and 4 , on the bit lines, so that the current stress will be applied to the bit lines at the time of memory cell selection.
  • FIGS. 3 and 4 show the configuration of comparator circuits for monitoring the resistance value of the dummy cells.
  • FIG. 3 is a diagram illustrating the configuration of a Set comparator circuit 111 for monitoring the resistance of the Set dummy cell.
  • FIG. 4 is a diagram illustrating the configuration of a Reset comparator circuit 112 for monitoring the resistance of the Reset dummy cell.
  • predetermined current values are set from constant current sources 303 and 403 , respectively.
  • a resistance device other than the phase change device for setting the resistance value to be written in the Set cell 301 may be provided as reference resistance, and a constant current source may then be provided by biasing means.
  • the reference value is equal to the write resistance of the Set dummy cell, the write resistance of the memory cell and to the resistance of the biasing means.
  • a current iSet is the reference current
  • a current equal to the reference current iSet flows through an NMOS transistor N 10 connected to a constant current source 303 . Since an NMOS transistor N 10 and N 10 constitute a current mirror circuit, the current iSet also flows through the NMOS transistor N 11 as a mirror current.
  • a current of iSetCell that is, a current flowing through the Set cell, flows through this PMOS transistor P 11 , because the bias circuit 302 and a PMOS transistor P 11 constitute a current mirror circuit.
  • the PMOS transistor P 11 and the NMOS transistor N 11 constitute a ratio inverter, so that, in case iSet ⁇ iSetCell (the current iSet flowing through the Set cell is larger than the reference current iset), that is, if the resistance value of the phase change device of the Set dummy cell 109 has become lower than the predetermined resistance value, under the effect of the read disturbance or the write disturbance, a comparison result output CompiSet goes HIGH.
  • iSet>iSetCell that is, the current iSetCell flowing through the Set cell is smaller than the reference current iSet, viz. if the resistance value of the phase change device of the Set dummy cell 109 has not become lower than the predetermined resistance value, under the effect of the read disturbance or the write disturbance, the comparison result output CompiSet outputs a LOW level.
  • An iReset monitor of FIG. 4 performs detection in a similar manner, such that
  • the refresh request circuit 107 is activated to make a refresh request to an internal circuit (refresh control circuit).
  • the ratio of the resistance of the biasing means, the reference resistance value and the write resistance is assumed to be 1:1:1.
  • the current ratio may be suitably set by properly setting the W/L (channel width/channel length) ratio of the MOS transistors making up the current mirror. This provides for a margin taking variations into account to enable setting to an optimum value.
  • FIGS. 5 and 6 show a circuit configuration of a verification amplifier 104 and a circuit configuration of a sense amplifier 102 , respectively.
  • the current values IVerify and iSense of constant current sources 503 and 603 are selected such that IVerify>iSense, so as to be used for verification and for normal read, respectively.
  • the write resistance value for the memory cell and the dummy cell correspond to the reference current provided by iVerify and, in case of sensing (read), may be set so that the margin for iSense is on the order of one-half of iVerify, taking into account the variation as well as shown in FIG. 7 .
  • the ratio may be changed to a proper value, depending on the transistor size.
  • a Set cell and a Reset cell are defined as 1 and 0 of data, respectively.
  • the memory cell data of a refresh unit is set in the data register 105 and, after resetting the data of the verification amplifier 104 , it is set to 1.
  • the Reset cell undergo Set writes and verifications by the verification amplifier in plural stages. This operation is repeated until Pass is obtained, at which time the Set is completed with the Pass.
  • the cells are matched for the time being to the resistance value of the Set state of the reference current + ⁇ for taking the operating margin into account.
  • writing is carried out in similar manner for the dummy cells, that is, Set dummy cells and Reset dummy cells.
  • FIGS. 8A and 8B show changes in the resistance value of the Set/Reset cells in case a sequence of operations in accordance with an embodiment of the present invention has been carried out.
  • FIG. 8A schematically shows the change in the programmed resistance value of the memory cell and the dummy call
  • FIG. 8B schematically shows the current and the pulse width at the time of writing.
  • the resistance value of the phase change device has been programmed in the RReset/Rset.
  • the write/read is carried out repeatedly.
  • Reset write If next the Reset write (RW) is written in the same memory cell with a current of iReset with a short pulse, the resistance value does not revert to RReset and is reset to a low resistance value of RReset′.
  • the refresh request circuit 107 issues a refresh request.
  • the refresh operation is now initiated. That is, memory cell data are temporally read and transferred to the data register 105 .
  • the value of the data register 105 is then referenced and Reset write is carried out only in the cells in the Set state.
  • the resistance value of the Reset cell, not stressed, is RReset, while that of the stressed device is RReset′.
  • Verify write (VW) is carried out.
  • data ‘1’ is set and Set write is carried out a plural number of times with the current iSet>iVerify as verify-read is carried out.
  • the current value is lowered because it is expected that the effect of suppressing variations in the resistance value may be obtained by controlling the progressing rate of crystallization from the amorphous state.
  • the current is compared to the predetermined resistance value, by the verification amplifier 104 .
  • the writing is discontinued for cells where the predetermined resistance has been reached. For other cells, writing is carried out with addition. By so doing, the resistance of the Set cell may be matched to the RSet cell even if variations in the Reset resistance are produced.
  • control may be by controlling the width or the time duration of application of the Set pulse.
  • data register values may be referenced to effect Reset only of the Reset cell to match the resistance value to RReset.
  • matching to the Set side is carried out once and Reset rewriting is carried out.
  • matching on the Reset side and the rewriting to Set may also be effected by applying high voltage and large current to achieve the operation and effect similar to those described above.
  • the reference cell stressed in accordance with the number of times of read and write operations a means for detecting a change in the resistance of the phase change device of the reference cell and for requesting an internal circuit to perform refresh operation in case the resistance value has been changed beyond a set reference value, and a means for counting the number of read operations and requesting the internal circuit to perform refresh operation in accordance with a predetermined number of times, or a means for detecting the difference of the reference current and the current flowing in the memory cell and requesting the internal circuit to perform refresh operation in case the resistance value has been changed beyond the predetermined reference value, are provided, and memory cells and the reference cells are temporarily refreshed or only the memory cell is refreshed to correct the variations of the phase change device.
  • the variations in the programmed resistance value of the phase change device may be corrected to provide for a margin as well as to improve retention characteristic.
  • FIG. 12 is a diagram illustrating the configuration of the second embodiment of the present invention.
  • the number of times of read is counted by a counter 1214 , with an inputting of a command at a command input circuit 1213 as a start point.
  • a refresh request is made in a similar manner to effect memory cell refresh. In this case, similar meritorious effects may be achieved.
  • FIG. 13 is a diagram illustrating the configuration of a third embodiment of the present invention.
  • no dummy cell is provided.
  • the currents flowing through a Set reference current circuit 1313 produced from the reference current source, a Reset reference current circuit 1314 and through the memory cell, are compared and, in case a predetermined offset has been produced, a request is made for performing refresh operations to the internal circuit.
  • the aforementioned refresh operations are carried out during the refresh period.
  • the refresh operation represents a technique whereby the resistances of the Reset/Set cells may be matched to a high accuracy. It is, however, time-consuming because the verifying operation has to be carried out simultaneously.
  • FIG. 14 shows an embodiment of a refreshing method for shortening the processing time.
  • this modified embodiment for the refreshing operation is such that a refresh request is verified by any of the refresh decision techniques of the aforementioned first to third embodiments and
  • Reset overwrite is carried out by applying the current or the voltage larger than that at the time of the Reset operation to establish the high resistance state of RReset+ ⁇ .
  • the current equal to iReset+ ⁇ is caused to flow and the crystal is fused by the Joule's heat to set an amorphous state of a higher resistance.
  • the Reset time ⁇ Set time and, in the above-described refresh method, the Set operation needs to be carried out a number of times until the state of the memory cell reaches the predetermined Set level.
  • the processing may be finished with at least two Reset operations and one Set operation, and hence the refresh may be finished in a short time.
  • the second refresh system is slightly inferior to the first refresh method as to the accuracy in matching the resistance value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
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US12/207,077 US7580277B2 (en) 2005-01-19 2008-09-09 Memory device including a programmable resistance element
US12/500,673 US7751227B2 (en) 2005-01-19 2009-07-10 Memory device including a programmable resistance element

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JP2005011626A JP4282612B2 (ja) 2005-01-19 2005-01-19 メモリ装置及びそのリフレッシュ方法
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Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070279975A1 (en) * 2006-06-06 2007-12-06 Hudgens Stephen J Refreshing a phase change memory
EP1883074A1 (de) * 2006-07-27 2008-01-30 Qimonda North America Corp. Lesestörungssensor für Phasenwechselspeicher
US20080074918A1 (en) * 2006-09-27 2008-03-27 Yu-Hwan Ro Phase change memory device and related programming method
US20080117663A1 (en) * 2006-11-22 2008-05-22 Jan Boris Philipp Resistive memory including refresh operation
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