TWI645567B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI645567B
TWI645567B TW103106156A TW103106156A TWI645567B TW I645567 B TWI645567 B TW I645567B TW 103106156 A TW103106156 A TW 103106156A TW 103106156 A TW103106156 A TW 103106156A TW I645567 B TWI645567 B TW I645567B
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Taiwan
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layer
connection terminal
insulating
electrode
metal
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TW103106156A
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English (en)
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TW201438245A (zh
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市川純廣
山野孝治
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新光電氣工業股份有限公司
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Abstract

本發明有關一半導體裝置，其包括一半導體基材。一貫通孔通過半導體基材。一第一絕緣層覆蓋半導體基材的上表面，並包括與貫通孔相通的一開口。一絕緣膜覆蓋貫通孔的壁面及開口的壁面。一貫通電極係形成於貫通孔及開口中。一第一連接端子包括一無電電鍍金屬層，其係形成於貫通電極的端面及絕緣膜的端面。第一連接端子具有較貫通電極大的直徑。一佈線圖案係層合於半導體基材的下表面上。一電極墊連接至佈線圖案。貫通電極連接至佈線圖案。

Description

半導體裝置及其製造方法
本發明有關一種半導體裝置及一種製造半導體裝置之方法。
由於更小更複雜的電子產品有所需求，因此用於這些產品中的半導體裝置(半導體晶片)例如ICs和LSIs需要有更高的積集度及更多的容量。半導體晶片亦被要求有更輕薄的封裝，包括更多的針腳(pin)，並具有更高的密度。為迎合這些需求，發展出系統級封裝(a system in package，SiP)，將複數個半導體晶片安裝於同一基材(substrate)上。例如，以三維方式疊合半導體晶片(即，晶片堆疊封裝(chip-stacked package))的SiP三維安裝技術漸受歡迎。此種晶片堆疊封裝可有高積集度。此外，因可縮短佈線長度，故電路可較高速操作，並可降低線路內的雜散電容(stray capacitance)。
已知的三維安裝技術，藉由將複數個半導體晶片疊合(stack)於基材上，並以打線接合的線將半導體晶片的電極與基材的電極電性連接，以製造晶片堆疊封裝。然而，在此種使用打線接合的線將半導體晶片與基材電性連接的構形中，線很細，因而增加阻抗。結果，此種構形無法應用於高速半導體晶片。再者，可能需要在封裝內提供線 迴路(wire loop)的區域，因而會增大封裝尺寸。
另一已知的三維安裝技術，藉由將複數個具有貫通電極(through electrode)的半導體晶片堆疊於基材上，並以此等貫通電極將半導體晶片彼此電性連接，以製造晶片堆疊封裝，例如可參考日本公開專利第2006-179562號。相較於打線接合(wire bonding)技術而言，此技術的佈線長度較短，因而可使封裝的尺寸更小。
然而，當複數個半導體晶片堆疊於基材上時，填充於半導體晶片間的底部填充材料中易形成空洞(void)。當堆疊的半導體晶片如上述以貫通電極彼此電性連接時，半導體晶片間的縫隙極窄。如此便難以均勻地在半導體晶片間填充底部填充材料。如此，縫隙中易形成空洞。當底部填充材料包括空洞時，而封裝體的溫度也在例如重流(reflow)製程中上升時，空洞中的氣體膨脹，導致半導體晶片間有裂痕。這樣會降低半導體晶片間電性連接的可靠性(reliability)。
本發明之一方面是一半導體裝置，其包括一半導體基材(semiconductor substrate)、一第一絕緣層(insulating layer)、一絕緣膜(insulating film)、一貫通電極、一第一連接端子(connection terminal)、一佈線圖案(wiring pattern)、一第二絕緣層、及一電極墊(electrode pad)。半導體基材包括一第一表面、一第二表面、及從第一表面通過半導體基材延伸到第二表面的一貫通孔(through hole)。第一絕緣層覆蓋半導體基材的第二表面。第一絕緣層包括與貫通孔相通的一開口(opening)，開口的直徑(diameter)與貫通孔的直徑相同。一絕緣膜覆蓋貫通孔的壁 面及開口的壁面。貫通電極形成於被絕緣膜覆蓋的貫通孔及開口中。貫通電極包括一金屬阻障層(metal barrier layer)及一導電層。金屬阻障層覆蓋貫通孔及開口中的絕緣膜，導電層填充被金屬阻障層圍繞的貫通孔及開口。第一連接端子包括形成於貫通電極的一端面上與絕緣膜的一端面上的一無電電鍍(electroless plating)金屬層。第一連接端子具有比貫通電極大的直徑。佈線圖案與第二絕緣層層合(laminated)於半導體基材的第一表面上。電極墊與佈線圖案連接。貫通電極與佈線圖案連接。
本發明另外之目的及優點，部份見於下文之敘述，部份由該敘述而顯而易見，或可由實施本發明而得知。經由所附的申請專利範圍所指出的元件與組合，可了解及獲得本發明之目的及優點。應了解上列一般敘述及下列詳述僅是例示與說明，非限制本發明之申請專利範圍。
1‧‧‧半導體封裝物
1A‧‧‧半導體封裝物
1B‧‧‧半導體封裝物
1C‧‧‧半導體封裝物
1D‧‧‧半導體封裝物
3B‧‧‧半導體晶片(下晶片)
2‧‧‧佈線基材
3‧‧‧半導體晶片(下晶片)
3A‧‧‧半導體晶片(下晶片)
3C‧‧‧半導體晶片(下晶片)
4‧‧‧半導體晶片(上晶片)
4A‧‧‧半導體晶片(上晶片)
5‧‧‧封裝樹脂
6a‧‧‧半導體晶片
6b‧‧‧半導體晶片
7‧‧‧封裝樹脂
10‧‧‧基材體
11‧‧‧基材芯
12‧‧‧絕緣層
13‧‧‧絕緣層
14‧‧‧佈線
15‧‧‧佈線
16‧‧‧介質孔
17‧‧‧介質孔
20‧‧‧佈線圖案
20P‧‧‧電極墊
21‧‧‧連接端子
22‧‧‧防焊層
22X‧‧‧開口
23‧‧‧佈線圖案
23P‧‧‧外部連接墊
24‧‧‧外部連接端子
25‧‧‧防焊層
25X‧‧‧開口
26‧‧‧絕緣層
26A‧‧‧絕緣層
30‧‧‧半導體基材
30A‧‧‧第一表面
30B‧‧‧第二表面
30C‧‧‧基材
30X‧‧‧貫通孔
31‧‧‧絕緣層
31A‧‧‧第一表面
31B‧‧‧突出部
31C‧‧‧上表面
31X‧‧‧開口
32‧‧‧貫通電極
32A‧‧‧導電層
32B‧‧‧上端面
32C‧‧‧突出部
32D‧‧‧突出部
32E‧‧‧突出部
32X‧‧‧凹處
33‧‧‧絕緣膜
33A‧‧‧突出部
34‧‧‧連接端子
35‧‧‧晶種層
36‧‧‧金屬膜
36A‧‧‧突出部
37‧‧‧金屬膜
40‧‧‧佈線圖案
41‧‧‧介質孔
42‧‧‧絕緣層
42X‧‧‧開口
43‧‧‧佈線層
43P‧‧‧電極墊
44‧‧‧保護膜
44X‧‧‧開口
45‧‧‧連接端子
46‧‧‧金屬層
50‧‧‧半導體基材
50A‧‧‧第一表面
51‧‧‧保護膜
51X‧‧‧開口
52P‧‧‧電極墊
53‧‧‧連接端子
54‧‧‧絕緣層
54A‧‧‧絕緣層
55‧‧‧連接端子
56‧‧‧焊料層
60‧‧‧基材
60A‧‧‧第一表面
60B‧‧‧第二表面
60X‧‧‧凹槽
61‧‧‧光阻層
61X‧‧‧開口
64‧‧‧晶種層
65‧‧‧鈦膜
66‧‧‧銅膜
67‧‧‧光阻層
67X‧‧‧開口
68‧‧‧銅膜
69‧‧‧焊料層
70‧‧‧黏著劑
71‧‧‧支撐體
73‧‧‧切割帶
80‧‧‧半導體基材
80A‧‧‧第一表面
80B‧‧‧第二表面
80X‧‧‧貫通孔
81‧‧‧絕緣層
81A‧‧‧第一表面
81X‧‧‧開口
82‧‧‧貫通電極
82B‧‧‧上端面(第一端面)
83‧‧‧絕緣膜
84‧‧‧連接端子
90‧‧‧佈線圖案
91‧‧‧介質孔
92‧‧‧絕緣層
93‧‧‧佈線層
93P‧‧‧電極墊
94‧‧‧保護膜
95‧‧‧連接端子
96‧‧‧絕緣層
96A‧‧‧絕緣層
100‧‧‧連接端子
101‧‧‧Ni層
101A‧‧‧Ni膜
101B‧‧‧突出部
102‧‧‧Au層
110‧‧‧連接端子
111‧‧‧Ni層
111A‧‧‧突出部
112‧‧‧Au層
本發明和其目的及優點可由一起參考下列較佳實施例之敘述與附圖而更加了解。
圖1為顯示第一實施例中半導體封裝物(semiconductor package)之剖面示意圖；圖2為顯示第一實施例中半導體晶片之放大剖面示意圖；圖3A至3D、4A至4D、5A至5D、6A至6C、7A至7C、8A至8C、9A、9B及10A至10C、11A、11B、及12各為顯示第一實施例中半導體晶片之製法之 剖面示意圖；圖13為顯示第二實施例中半導體封裝物之剖面示意圖；圖14至16各為顯示第二實施例中半導體封裝物之製法之剖面示意圖；圖17A及17B各為顯示第三實施例中半導體封裝物之製法之剖面示意圖；圖18為顯示第三實施例中半導體封裝物之製法之剖面示意圖；圖19A及19B各為顯示第四實施例中半導體封裝物之製法之剖面示意圖；圖20A為顯示第五實施例中半導體封裝物之剖面示意圖；圖20B為顯示圖20A中半導體晶片之放大剖面示意圖；圖21A至21E各為顯示第五實施例中半導體封裝物之製法之剖面示意圖；圖22為顯示一修飾例中半導體晶片部分放大剖面示意圖；圖23A至23C各為顯示圖22之半導體晶片之製法之剖面示意圖；圖24至26為顯示另一修飾例中半導體晶片部分放大剖面示意圖；圖27A至27C各為顯示圖24之半導體晶片之製法之剖面示意圖；圖28至34各為顯示一修飾例中半導體晶片部分放大剖面示意圖；圖35A為顯示第六實施例中半導體封裝物之剖面示意圖；圖35B為顯示圖35A之半導體晶片部分之放大剖面示意圖；圖36A至36C各為顯示第六實施例中半導體晶片之製法之剖面示意圖；圖37至49各為顯示一修飾例中半導體晶片部分放大剖面示意圖；及圖50A及50B各為顯示半導體封裝物之另一製法之剖面示意圖。
參考圖式說明實施例。於圖式中，元件簡潔清楚標示，且不一定依照比例繪示。為易於了解，剖面圖中可能未繪示剖面陰影線。再者，在全部實施例中，使用相同或類似的符號表示相同或類似的部件。
如圖1所示，一半導體封裝物1包括一佈線基材2、安裝於佈線基材2的一半導體晶片3、堆疊於半導體晶片3上的一半導體晶片4、以及將堆疊於佈線基材2上的半導體晶片3及4密封的一封裝樹脂5。半導體封裝物1是所謂的晶片堆疊封裝，其中，半導體晶片3及4以三維的方式堆疊於佈線基材2上。堆疊的半導體晶片3可為邏輯裝置(例如CPU或MPU)用的半導體晶片。半導體晶片4可為記憶裝置(例如DRAM或SDRAM)用的半導體晶片。於後述中，亦將堆疊於佈線基材2上的二半導體晶片中的下方的半導體晶片3稱為下晶片3，將上方的半導體晶片4稱為上晶片4。
將封裝樹脂5塗敷於佈線基材2上以將疊合的下晶片3及上晶片4密封。封裝樹脂5的材料可為絕緣樹脂，例如環氧樹脂(epoxy resin)或聚醯亞胺樹脂(polyimide resin)。封裝樹脂5可從樹脂液、樹脂錠、或樹脂粉形成。可藉由轉移成型(transfer molding)、壓縮成型(compression molding)、射出成型(injection molding)或澆封(potting)塗敷封裝樹脂5。或者，可藉由印刷(print)樹脂膏(paste)的方式塗敷封裝樹脂5。
其次，說明佈線基材2的結構。佈線基材2包括基材體(substrate body)10、形成最上層的佈線圖案20、防焊層(或稱焊阻層，solder resist layer)22、形成最下層的佈線圖案23、及防焊層25。
基材體10包括一基材芯(substrate core)11、層合(laminated)於基材芯11上的複數個絕緣層12及13、以及形成於絕緣層12和13上的複數個佈線(wires)14和15及複數個介質孔(vias)16和17。基材體10上的佈線14和15及介質孔16和17電性連接至佈線圖案20及佈線圖案23。佈線14和15及介質孔16和17的材料可為銅(Cu)。絕緣層12和13的材料可為絕緣樹脂，例如環氧樹脂或聚醯亞胺樹脂。
佈線圖案20位於安裝有下晶片3和上晶片4的安裝面上(圖1，上側)。佈線圖案20包括電極墊20P。佈線圖案20的材料可為銅。
連接端子21形成於各電極墊20P上。連接端子21可為預焊層(pre-solder)或表面處理層。預焊層的材料可為共熔焊料(eutectic solder)或無鉛銲料(Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金或類似者)。表面處理層的例子包括Sn層、金(Au)層、鎳(Ni)層/Au層(將Ni層與Au層以此順序層合而形成的金屬層)、Ni層/鈀(Pd)層/Au層(將Ni層、Pd層、與Au層以此順序層合而形成的金屬層、以及Pd層/Au層(將Pd層與Au層以此順序層合而形成的金屬層)。Sn層、Ni層、Au層、及Pd層各可為藉由無電電鍍方式形成的金屬層(無電電鍍金屬層)。Sn層是由Sn或Sn合金製得的金屬層、Au層是由Au或Au合金製得的金屬層、Ni層是由Ni或Ni合金製得的金屬層、以及Pd層是由Pd或Pd合金製得的金屬層。可對電極墊20P進行抗氧化處理，例如有機可焊性保存(organic solderability preservative，OSP)處理，以形成表面處理層(連接端子21)。
防焊層22位於基材體10的上側以覆蓋部分的佈線圖案20。防 焊層22具有複數個開口22X。部分的佈線圖案20從各開口22X曝露出，作為電極墊20P的功能。防焊層22的材料可為絕緣樹脂，例如環氧樹脂。
佈線圖案23位於基材體10的下側。佈線圖案23包括複數個外部連接墊23P。各外部連接墊23P包括用以將佈線基材2安裝於安裝板(例如主機板)上的外部連接端子24。各外部連接端子24可為焊球(solder ball)或引線針腳(lead pin)。外部連接墊23P是藉由從基材體10下側所形成的防焊層25中的開口25X暴露部分佈線圖案23所形成。佈線圖案23的材料可為銅。可藉由對銅層表面施加特定鍍層(例如鍍鎳或鍍金)以形成佈線圖案23。防焊層25的材料可為絕緣樹脂，例如環氧樹脂。
於佈線基材2與安裝於佈線基材2上的下晶片3之間形成絕緣層26。絕緣層26增加佈線基材2上的電極墊20P與下晶片3上的連接端子45的連接強度。再者，絕緣層26抑制佈線圖案20的腐蝕及電遷移的發生，以維持佈線圖案20的可靠性。絕緣層26的材料可為絕緣樹脂，例如環氧樹脂及聚醯亞胺樹脂。例如，絕緣層26的材料可為一絕緣樹脂黏著層，例如非導電膜(non-conductive film，NCF)，或絕緣樹脂膏(paste of insulating resin)，例如非導電膏(non-conductive paste，NCP)。絕緣層26的材料可為堆積樹脂(build-up resin)(含填充料的環氧樹脂)或晶質聚合物液(crystal polymer liquid)。絕緣層26的材料可為非等向性導電樹脂黏著層，例如非等向性導電膜(anisotropic conductive film，ACF)，或非等向性導電樹脂膏，例如非等向性導電膏(anisotropic conductive paste，ACP)。此處，ACP及ACF是將塗覆著Ni/Au的樹脂小粒分布於基質為環氧樹脂或氰酸酯樹脂的絕緣樹脂中而形成的樹脂。再者，ACP及ACF 在垂直方向具有導電性，而在水平方向具有絕緣性。絕緣層26的厚度為例如約10至100μm。
以此方式，在本實施例的半導體封裝物1中，佈線基材2的作用如中介層(interposer)，用以將半導體晶片3及4與一安裝板(圖未示)例如主機板連接。佈線基材2僅需要具有一結構，其通過安裝板的內部將身為最外層的佈線圖案20及23電連接。因此，從佈線圖案20及23往內的層結構並無限制。例如，基材內不一定需要形成佈線層(wiring layer)。基材體10可為不包括基材芯11的一無芯基材，而非包括基材芯11的一有芯構成的基材(cored build-up substrate)。
其次，將說明下晶片3的結構。下晶片3包括一半導體基材30、一絕緣層31、複數個貫通電極32、一絕緣膜33、一佈線圖案40、複數個介質孔41、一絕緣層42(第二絕緣層)、複數個電極墊43P、一保護膜44、及複數個連接端子45。將下晶片3以覆晶接合(flip-chip bonded)的方式與佈線基材2接合。
於半導體基材30中，第一表面30A(圖1的下表面)上有半導體積體電路(圖未示出)形成。半導體積體電路包括形成於半導體基材30上的擴散層(圖未示出)、層合於半導體基材30上的一絕緣層、及配置於層合的絕緣層中的複數個介質孔及佈線。從半導體基材30的第一表面30A延伸至第二表面30B(圖1的上表面)的複數個貫通孔30X係形成於半導體基材30中的特定位置。半導體基材30的材料可為矽(Si)。半導體基材30的厚度為例如約10至200μm。半導體基材30為例如一薄化的Si晶圓(wafer)的片段(fragment)。
絕緣層31(第一絕緣層)係形成以覆蓋半導體基材30的第二表面30B(其表面係疊合著上晶片4)。絕緣層31包括相對於貫通孔30X的複數個開口31X。各開口31X實質上具有與對應的貫通孔30X的直徑相同的直徑，並與對應的貫通孔30X相通。
絕緣層31的材料可為絕緣樹脂，例如環氧樹脂或聚醯亞胺樹脂。例如，絕緣層31的材料可為絕緣樹脂黏著層(例如NCF)、絕緣樹脂膏(例如NCP)、積建(或稱堆積)樹脂(含填充料的環氧樹脂)或晶質聚合物液。絕緣層31的厚度為例如約0.1至50μm。
絕緣膜33係形成以覆蓋半導體基材30的第一表面30A、貫通孔30X的壁面、及開口31X的壁面。絕緣膜33可為由SiN或SiO2製得的無機絕緣膜。絕緣膜33的厚度為例如約0.1至1.0μm。
各貫通電極32填入被覆蓋著絕緣膜33的貫通孔30X及開口31X。貫通電極32的下端面實質上與半導體基材30的第一表面30A上的絕緣膜33齊平。貫通電極32的下端面與佈線圖案40電性連接。
如圖2所示，絕緣層31包括與半導體基材30的第二表面30B接觸的一接觸面及位於此接觸面相對側的一外表面(亦稱為第一表面31A)。貫通電極32的上端面(第一端面)32B實質上與絕緣層31的第一表面31A齊平。當上晶片4疊合於下晶片3上時，貫通電極32的上端面32B作用如下晶片3的墊片(pads)。例如，各貫通電極32為圓柱形，具有約5至20μm的直徑。例如，貫通電極32具有約20至200μm的節距(pitch)。
連接端子34形成於貫通電極32的各上端面32B上。連接端子34可為Sn層、Ni層/Sn層、Au層、Ni層/Au層(將Ni層與Au層以此順序層合 而形成的金屬層)、Pd層/Au層(將Pd層與Au層以此順序層合而形成的金屬層)、或Ni層/Pd層/Au層(將Ni層、Pd層、與Au層以此順序層合而形成的金屬層)。各Sn層、Ni層、Au層、及Pd層各可為藉由無電電鍍方式形成的金屬層(無電電鍍金屬層)。例如，當連接端子34為Ni層/Au層時，Ni層具有約0.1至5.0μm的厚度，及Au層具有約0.001至1.0μm的厚度。例如，當連接端子34為Ni層/Pd層/Au層時，Ni層具有約0.1至5.0μm的厚度，Pd層具有約0.01至0.3μm的厚度，及Au層具有約0.001至1.0μm的厚度。
貫通電極32係形成於包含貫通孔30X及開口31X的一空間中，絕緣膜33被形成以完全覆蓋貫通孔30X的壁面及開口31X的壁面。晶種層35完全覆蓋貫通孔30X及開口31X中的絕緣膜33的壁面。於所示實例中，晶種層35可為一層合體(laminated body)，由氮化鉭(TaN)所製得的金屬膜36及層合於金屬膜36內側且由銅(Cu)製得的金屬膜37所形成。導電層32A填充於晶種層35(金屬膜37)之內側的貫通孔30X及開口31X中。導電層32A及晶種層35(金屬膜36及金屬膜37)形成貫通電極32。形成晶種層35的金屬膜36位在外側，為一金屬阻障層，避免銅由位於內側的金屬膜37(Cu膜)或導電層32A擴散至絕緣膜33。金屬阻障層(即，金屬膜36)的材料並不限於TaN，而可為鉭(Ta)、鉻(Cr)、或鈦(Ti)。導電層32A的材料可為銅或銅合金。
佈線圖案40係形成於覆蓋半導體基材30的第一表面30A的絕緣膜33的下表面上。佈線圖案40的第一端與貫通電極32的下端面連接，及佈線圖案40的第二端經由介質孔41與電極墊43P連接。即，佈線圖案 40及介質孔41將貫通電極32與電極墊43P電性連接。佈線圖案40及介質孔41的材料可為銅或銅合金。
絕緣層42係形成以覆蓋佈線圖案40。供曝露部分佈線圖案40用的開口42X，係形成於絕緣層42中的特定位置。介質孔41係形成於開口42X中。絕緣層42的材料可為具有低介電常數的低介電材料(所謂Low-k材料)。低介電材料的實例包括SiOC、SiOF、及有機聚合物。例如，絕緣層42的介電常數為約3.0至3.5。例如，絕緣層42的厚度為約0.5至2μm。
佈線層43係形成於各介質孔41的下表面上。佈線層43的形狀自上方看來較介質孔41的形狀大。佈線層43的材料可為鋁(Al)。佈線層43的材料可為Cu/Al合金或Cu/Al/Si合金。
保護膜44係形成於絕緣層42的下表面上以覆蓋絕緣層42的下表面及部分佈線層43。保護膜44具有複數個開口44X，用以曝露部分之佈線層43以做為電極墊43P。保護膜44可保護形成於半導體基材30的第一表面30A的半導體積體電路(圖未示出)，亦稱為鈍化膜(passivation layer)。保護膜44可為SiN膜或PSG膜。保護膜44可為將一聚醯亞胺層層合於SiN膜或PSG膜上而形成的層合體。
連接端子45係分別形成於電極墊43P上。連接端子45電性連接至貫通電極32及半導體積體電路(圖未示出)。各連接端子45為圓柱狀連接凸塊(bump)，其自電極墊43P的下表面向下延伸。連接端子45位於對應於佈線基材2的電極墊20P的位置。如圖1所示，當將下晶片3安裝於佈線基材2上時，連接端子45電性連接至對應的電極墊20P。連接端子 45的高度為例如約20至40μm。連接端子45的直徑為例如約10至40μm。連接端子45的材料可為銅。
如圖2所示，金屬層46係形成於各連接端子45的下表面上。金屬層46可為Au層、Ni層/Au層(藉由將Ni層及Au層以此順序層合所得的金屬層)、Pd層/Au層(藉由將Pd層及Au層以此順序層合所得的金屬層)、或Ni層/Pd層/Au層(藉由將Ni層、Pd層及Au層以此順序層合所得的金屬層)。金屬層46可為無鉛焊料(例如以Sn-Ag為主的(Sn-Ag-based))鍍層。
接著，將參照圖1說明上晶片4的結構。
上晶片4包括一半導體基材50、一保護膜51、複數個電極墊52P、複數個連接端子53、及一絕緣層54。上晶片4係覆晶接合至下晶片3。
半導體積體電路(圖未示出)係形成於半導體基材50的第一表面50A上(圖1的下表面)。半導體積體電路具有形成於半導體基材50上的一擴散層、位於半導體基材50上的層合的(laminated)一絕緣層、及配置於層合的絕緣層內的複數個介質孔及佈線。半導體基材50的材料可為矽(Si)。半導體基材50的厚度為例如約30至200μm。半導體基材50為例如一薄化的Si晶圓的片段。
保護膜51係形成以覆蓋半導體基材50的第一表面50A。保護膜51具有複數個開口51X，電極墊52P從開口51X曝露出來。保護膜51保護於半導體基材50的第一表面50A所形成的半導體積體電路(圖未示出)，亦稱為鈍化膜。保護膜51可為SiN膜或PSG膜。保護膜51可為將一聚醯亞胺層層合於SiN膜或PSG膜所形成的層上，而形成的層合體。
電極墊52P電性連接至半導體積體電路(圖未示出)。電極墊52P的位置對應於下晶片3的貫通電極32。當上晶片4疊合於下晶片3上時，如圖1所示，電極墊52P電性連接至對應的貫通電極32(連接端子34)。再者，電極墊52P分別經由貫通電極32電性連接至佈線基材2上的電極墊20P。電極墊52P係從保護膜51中的開口51X曝露出所形成的。電極墊52P的材料可為鋁(Al)。電極墊52P的材料可為Cu/Al合金或Cu/Al/Si合金。
連接端子53係形成於對應的電極墊52P上。連接端子53經由電極墊52P電性連接至半導體積體電路(圖未示出)。當上晶片4疊合於下晶片3上時，如圖1所示，連接端子53藉由半導體晶片3的連接端子34，電性連接對應的貫通電極32。如上述，下晶片3藉由下晶片3中所形成的貫通電極32，電性連接上晶片4。
連接端子53可為Ni層/Au層/Sn層(藉由將Ni層、Au層及Sn層以此順序層合所得的金屬層)或Ni層/Pd層/Au層/Sn層(藉由將Ni層、Pd層、Au層及Sn層以此順序層合所得的金屬層)，其係藉由鋁的浸鋅處理(Al zincate)或無電電鍍所形成。連接端子53可為Ni層/Au層(藉由將Ni層及Au層以此順序層合所得的金屬層)、Ni層/Pd層/Au層(藉由將Ni層、Pd層及Au層以此順序層合所得的金屬層)、或Ni/Sn層(藉由將Ni層及Sn層以此順序層合所得的金屬層)，其係藉由鋁的浸鋅處理(Al zincate)或無電電鍍所形成。如下晶片3的連接端子45及金屬層46，各連接端子53可為在圓柱狀連接凸塊上所形成的焊料層(solder ayer)、或圓柱狀連接凸塊(cylindrical connection bump)、Ni層及焊料層的層合體。於此例中， 連接凸塊的材料可為Cu層，焊料層的材料可為無鉛焊料(例如Sn-2.5Ag)。
當上晶片4疊合於下晶片3上時，絕緣層54係形成於保護膜51的下表面，以覆蓋上晶片4的連接端子53及下晶片3的連接端子34及貫通電極32。絕緣層54增加下晶片3的連接端子34與上晶片4的連接端子53的連接強度、抑制貫通電極32的腐蝕及電遷移的發生、及維持貫通電極32的可靠性。絕緣層54的材料是與下晶片3的最上層絕緣層31(即，當上晶片4疊合於下晶片3時，與絕緣層54接觸的絕緣層31)的材料相同的絕緣樹脂，或是與絕緣層31不同的絕緣樹脂。例如，當絕緣層54是與絕緣層31由相同的絕緣樹脂製造時，絕緣層54的材料可為絕緣樹脂，例如環氧樹脂或聚醯亞胺樹脂。例如絕緣層54的材料可為一絕緣樹脂的黏著層(例如NCF)、絕緣樹脂膏(例如NCP)、積建(build-up)樹脂(含填充料的環氧樹脂)或晶質聚合物液。絕緣層54的材料可為非等向性導電樹脂黏著層(例如ACF)、或非等向性導電樹脂膏(例如ACP)。絕緣層54的厚度為例如約5至15μm。
於下晶片3中，貫通電極32的上端面實質上與半導體基材30的第二表面30B上的絕緣層31的第一表面31A齊平。如此，下晶片3的上表面(即，在疊合的下晶片3與上晶片4之間的縫隙中的下表面)為平面。於本實施例中，上晶片4的絕緣層54對應於底部填充材料(underfill material)。因為與絕緣層54接觸的下晶片3的絕緣層31的上表面為平面，當絕緣層54黏著於絕緣層31時，此二絕緣層之間的界面不會產生空洞，並且，此二絕緣層的黏著令人滿意。
當上晶片4未設置絕緣層54時，在將上晶片4安裝於下晶片3後，於下晶片3與上晶片4之間填充底部填充材料。此處，因為，如上述，下晶片3的絕緣層31的上表面為平面，所以增強了下晶片3與上晶片4之間所填充的底部填充材料的流動性(flowability)，而改善了底部填充材料的填充性質。
接著，說明製造半導體封裝物1的方法。
首先，參照圖3至圖8說明製造下晶片3的方法。雖然圖式顯示單一放大晶片，但下晶片3係從一晶圓所製得。因此，從一個單一晶片製得一批下晶片，然後將下晶片一一分開。此處將不敘述半導體積體電路的製法。
於圖3A所示的步驟中，準備了製造半導體基材30用的基底材料，即，基材60。基材60比半導體基材30厚，(例如約725至775μm)。基材60可為矽基材。
其次，於圖3B所示的步驟中，於基材60的第一表面60A形成光阻層(resist layer)61，其包括開口61X。開口61X曝露基材60的第一表面60A對應於貫通孔30X(參照圖1)的部位。
然後，使用光阻層做為遮罩，藉由非等向蝕刻例如深反應離子蝕刻(DRIE)，於基材60中形成凹槽60X。凹槽60X係從基材60的第一表面60A通至基材60的一個深度(halfway)。當基材60在後述的圖7A所示的步驟中被薄化後，凹槽60X會成為貫通孔30X。因此，所形成的凹槽60X是比貫通孔30X深。圖3B的步驟中所形成的凹槽60X的深度可有不同的變化。在形成凹槽60X後，圖3B所示的光阻層61可藉由灰化(ashing) 或類似方法移除。
其次，於圖3C所示的步驟中，形成絕緣膜33以覆蓋基材60的第一表面60A及凹槽60X的壁面。當基材60為矽基材時，可藉由將基材60予以熱氧化而形成絕緣膜33。絕緣膜33可藉由例如CVD形成。
然後，於圖3D所示的步驟中，形成晶種層35以覆蓋絕緣膜33。晶種層可藉由進行濺鍍或無電電鍍而形成。例如進行濺鍍以沉積氮化鉭(TaN)而覆蓋絕緣膜33，藉以形成金屬膜36。然後，進行濺鍍以沉積銅於金屬膜36上，而形成金屬膜37。此形成具有二層(two-layered)(TaN/Cu)結構的晶種層35。金屬膜36可具有約0.1μm的厚度，及金屬膜37可具有約0.2μm的厚度。
其次，於圖4A所示的步驟中，使用晶種層35做為饋電層(power feeding layer)，進行電解銅鍍層，以在晶種層35上形成導電層32A。導電層32A填入覆蓋著絕緣膜33及晶種層35的凹槽60X。導電層32A可藉由於凹槽60X中內嵌(embedding)例如導電膏、熔融金屬、或金屬線而形成。
接著，於圖4B所示的步驟中，可利用例如化學機械研磨(CMP)裝置研磨並移除多餘的導電層32A及晶種層35。例如進行研磨，直到曝露出形成於基材60的第一表面60A上的絕緣膜33為止。
接著，於圖4C所示的步驟中，經由任何已知的方法，將佈線圖案40、絕緣層42、介質孔41、及佈線層43層合於圖4B所示的結構的上側。
然後，於圖4D所示的步驟中，於絕緣層42及佈線層43上形成 包括開口44X的保護膜44，僅有形成於部分佈線層43上的電極墊43P會從開口44X曝露出。保護膜44可藉由下述步驟形成：以CVD形成覆蓋絕緣層42及佈線層43的保護膜44、於保護膜44上形成光阻層(其暴露要形成開口44X的地方)、及然後使用光阻層做為遮罩進行乾蝕刻移除保護膜44暴露的部分。
其次，於圖5A所示的步驟中，形成晶種層64以覆蓋保護膜44的上表面、開口44X的壁面、及從開口44X露出的電極墊43P的上表面。可進行濺鍍或無電電鍍以形成晶種層64。例如進行濺鍍以沉積鈦(Ti)而形成鈦膜65而覆蓋保護膜44的上表面、開口44X的壁面、及電極墊43P的上表面。然後，進行濺鍍以沉積銅於鈦膜65上，而形成銅膜66。此形成二層(two-layered)(Ti/Cu)晶種層64。鈦膜65的厚度為例如約0.1μm，及銅膜66的厚度為例如約0.2μm。晶種層64的下層之鈦膜65是可增加下層的保護膜44與上層的銅膜66之間的黏著性的金屬層。做為黏著層的金屬層的材料可為Ti或鉻(Cr)。
其次，於圖5B所示的步驟中，於晶種層64上形成包括開口67X的光阻層67。開口67X曝露晶種層64上表面之對應於連接端子45及金屬層46在電極墊43P上形成的部位(參照圖2)。光阻層67的材料可為感光性的乾膜或液態光阻劑(liquid photoresist)(酚醛清漆樹脂(novolac resin)、環氧樹脂、或類似者的液態阻劑)。當使用乾膜時，進行熱壓縮將乾膜層合於晶種層64上，及將乾膜經過曝光與顯影而圖形化，形成具有對應於連接端子45的開口67X預定圖形的光阻層67。當使用液態阻劑時，亦可以類似步驟形成光阻層67。
然後，於圖5C所示的步驟中，使用光阻層67做為鍍層遮罩，對晶種層64進行電解鍍層，其使用晶種層64做為鍍層饋電層(plating power-feeding layer)。例如，藉由對光阻層67的開口67X所曝露出的晶種層64的上表面進行電解鍍層，於各開口67X中依序形成成為連接端子45的銅層68及形成為金屬層46的金屬層69。例如，藉由使用晶種層64做為鍍層饋電層進行電解鍍層，而於晶種層64上形成圓柱形銅層68。其次，當金屬層69為無鉛焊料(例如以Sn-Ag為基底(Sn-Ag-based))鍍層時，使用晶種層64做為鍍層饋電層進行電解焊鍍，使Sn-Ag焊料層(solder layer)黏著於銅層68。
其次，於圖5D所示的步驟中，進行灰化或類似者移除圖5C所示之光阻層67。然後，使用銅層68及焊料層69做為遮罩，蝕刻並移除晶種層(鈦膜65及銅膜66)不需要的部分。結果，晶種層(鈦膜65及銅膜66)的剩餘部分及銅層68形成連接端子45。
其次，於圖6A所示的步驟中，將助焊(熔)劑(flux)塗覆於圖5D所示的焊料層69上，及於例如約240℃至260℃的溫度下進行迴焊(回填)製程(reflow process)以熔融焊料層69及形成電性連結至連接端子45的金屬層46。然後，將殘留在金屬層46周圍的助焊劑洗除。於此步驟中，可進行不使用助焊劑的無助焊劑迴焊製程以形成金屬層46。
其次，於圖6B所示的步驟中，使用黏著劑70將支撐體(support body)71黏著至已經翻轉倒置的圖6A的結構的下表面，即，有連接端子45及金屬層46形成的表面。支撐體71的材料可為矽或玻璃。
然後，於圖6C所示的步驟中，例如使用背面研磨裝置(back surface polishing device)研磨基材60的第二表面60B，以將基材60薄化。例如，於此步驟中，將基材60從第二表面60B的這側薄化，使導電層32A及絕緣膜33不會曝露。
當在此步驟中研磨基材60的第二表面60B時，晶圓的周邊成為刀狀。此狀況也許會使晶圓龜裂。因此，在黏著支撐體71之前，可先修剪(trim)晶圓的外緣(邊緣)，以便不使晶圓的邊緣成為刀狀。此種邊緣修剪可藉由已知切割技術進行。可在黏著支撐體71後進行邊緣修剪。
其次，於圖7A所示的步驟中，將基材60進一步薄化以露出絕緣膜33。例如，從絕緣膜33選擇性移除部分基材60(矽基材)。將基材60薄化，於基材60中形成貫通孔30X，基材60成為對應於半導體基材30(參照圖1)的基材30C。可藉由進行使用含硝酸(HNO3)或氟化氫(HF)的溶液做為蝕刻液的濕蝕刻或進行電漿蝕刻(乾蝕刻)，將基材60薄化。於此例中，因為絕緣膜33未被蝕刻，絕緣膜33所覆蓋的導電層32A的部分亦從基材30C曝露出。
其次，於圖7B所示的步驟中，於基材30C的第二表面30B上形成絕緣層31，以覆蓋從基材30C曝露出的絕緣膜33及導電層32A。例如，絕緣層31可藉由真空，層合一樹脂膜例如環氧樹脂，以覆蓋基材30C的第二表面30B、絕緣膜33、及導電層32A，緊壓(推)樹脂膜，及然後在約150℃至190℃進行加熱製程將樹脂膜固化(cure)而形成。或者，絕緣層31可藉由塗覆樹脂液例如環氧樹脂，以覆蓋基材30C的第二表面30B、絕緣膜33、及導電層32A，及然後在約150℃至190℃進行加熱製程將樹脂固化而形成。
其次，於圖7C所示的步驟中，將絕緣層31、絕緣膜33、導電層32A、及晶種層35平坦化，以使導電層32A及晶種層35的上表面與絕緣層31的上表面齊平。此使導電層32A及晶種層35的上表面從基材30C曝露出，及於絕緣層31中形成開口31X，以形成貫通電極32，其填充被覆蓋有絕緣膜33的貫通孔30X及開口31X。此時，絕緣層31的開口31X的壁面完全被絕緣膜33覆蓋，及各貫通電極32係藉由導電層32A及形成於絕緣膜33與導電層32A之間的晶種層35(TaN製得的金屬膜36及Cu製得的金屬膜37)所形成。平坦化方法可為碾磨(grinding)及/或研磨(polishing)。於本實施例中，使用碳化鎢或鑽石磨刃(工具)進行碾磨(grinding)，以達平坦化。
其次，於圖8A所示的步驟中，於對應的貫通電極32的上端面32B形成連接端子34。當連接端子34為Ni層/Au層時，Ni層及Au層係藉由無電電鍍的方式，以此順序層合於貫通電極32的上端面32B上。此形成一對應於支撐體71上方的下晶片3的結構。
其次，於圖8B所示的步驟中，將對應下晶片3的結構表面(有連接端子34形成於其上)黏著至被一切割架(dicing frame)支撐的切割帶(dicing tape)73。然後，於圖8C所示的步驟中，將圖8B所示的黏著劑70及支撐體71移除。然後，使用切割器(dicer)的刀片將晶圓(基材30C)沿著顯示各晶片區域的線進行切割，以獲得各下晶片3。結果，基材30C成為半導體基材30。切割之後，將被切割帶73黏住的下晶片3撿起，於下一步驟中使用該撿起的下晶片3。
其次，於圖9A所示的步驟中，製備佈線基材2。佈線基材2可 經由任何已知的製法製造，如參照圖9A所述者。
當製造佈線基材2時，首先製備基材芯11。例如，基材芯11係藉由於銅箔基板(copper-clad laminate，CCL)中形成貫通孔，並在貫通孔的壁面上鍍層所形成，使得兩相對的表面電性連接。然後，於減除製程(subtractive process)中形成佈線14和15。接著，藉由真空層合樹脂膜、加熱及固化，而於基材芯11的二表面上形成絕緣層12及13。絕緣層12及13可藉由塗覆及加熱一樹脂而製得。然後，於各絕緣層12及13中形成一開口，若需要的話，進行去污處理(desmearing)。然後，例如經由半加成處理(semiadditive method)，形成介質孔16及17、以及佈線圖案20及23。接著，形成防(抗)焊層22及25，其包括開口22X及25X，供部分曝露出佈線圖案20及23，以分別做為電極墊20P及23P。
其次，於電極墊20P上形成連接端子21。當連接端子21為預焊料(pre-solder)時，將Sn/Ag合金做成之焊料膏(solder paste)塗覆至電極墊20P，及進行迴焊製程。當連接端子21為Sn層(表面處理過的層)時，進行無電電鍍於電極墊20P上，形成Sn層。此等步驟可製得佈線基材2。
然後，於佈線基材2的上側形成B階段狀態(B-stage state)(半固化狀態(semi-cured state))的絕緣層26A，以覆蓋連接端子21。絕緣層26A的厚度依下晶片3的連接端子45的高度而定。意即，當將下晶片3安裝於佈線基材2上時，將絕緣層26A的厚度設定為完全覆蓋連接端子45的表面。當絕緣層26A的材料為絕緣樹脂片材時，將絕緣樹脂片材層合於佈線基材2的上表面。然而，於此步驟中，並未將絕緣樹脂片材熱固化，其仍在B階段狀態。在真空中層合絕緣層26A時，可防止絕緣層26A中 形成空洞。當絕緣層26A的材料為絕緣樹脂液或膏時，藉由例如印刷或旋塗，將絕緣樹脂液或膏塗覆於佈線基材2的上表面。然後，將塗覆的絕緣樹脂液或膏預烘(prebake)至B階段狀態。
其次，於圖9A所示的步驟中，將撿起的下晶片3配置於有絕緣層26A形成於其上表面的佈線基材2的上方。例如佈線基材2之位於電極墊20P側的表面被配置與下晶片3之位於電極墊43P側的表面相對，使得連接端子45及金屬層46與連接端子21相對。
然後，於圖9B所示的步驟中，下晶片3的連接端子45以覆晶接合的方式與對應之其上形成有連接端子21的電極墊20P接合。例如，首先將下晶片3安裝於佈線基材2上，使絕緣層26A位於二者之間，並藉由處於B階段狀態的未經熱固化的絕緣層26A的黏性暫時固定。當需要時，可將下晶片3往絕緣層26A(佈線基材2)推壓。此時，下晶片3的連接端子45(以及形成於連接端子45上的金屬層46)與佈線基材2的電極墊20P上的連接端子21相對。例如，藉由加熱至約240至260℃的溫度及來自下晶片3的負載，將電極墊20P電性連接至連接端子45。此處，當使用焊料於連接端子21或連接端子45之至少一者上，可使焊料熔融及固化以將連接端子21與連接端子45連接。加熱將絕緣層26A熱固化。結果，使電極墊20P及43P以及連接端子45被熱固化的絕緣層26所覆蓋。
其次，製備上晶片4，其係疊合於以覆晶接合方式與佈線基材2連接的下晶片3上。上晶片4的製法將參照圖10說明。雖然圖式顯示單一放大晶片，上晶片4係從一晶圓所製得。因此，從一個單一晶圓製得一批上晶片，然後將上晶片一一分離。此處將不敘述分離的步驟。
於圖10A所示的步驟中，製備半導體基材50，其包括半導體積體電路(圖未示出)，並經由已知方法製造。例如，在對半導體基材50進行若干裝置的製程後，於其上有半導體基材50的半導體積體電路(圖未示出)形成的第一表面50A(圖10A中的上表面)上形成保護膜51。再者，移除保護膜51的複數個部分，這些保護膜51的複數個部分係對應於複數個電極墊52P，這些電極墊52P係由具有特定圖形的各裝置上所形成的大量佈線層的複數個部分所界定的。結果，可在保護膜51中形成開口51X。可藉由使用YAG雷射、準分子雷射(excimer laser)、或類似者形成開口51X。
其次，於圖10B所示的步驟中，於電極墊52P上形成連接端子53。於此步驟中，首先對電極墊52P的鋁表面進行4浸鋅處理(zincate treatment)，以對電極墊52P進行無電電鍍。然後，若連接端子53為Ni層/Au層/Sn層，則藉由無電電鍍，將Ni層、Au層、及Sn層以此順序層合於電極墊52P上而形成連接端子53。
其次，於圖10C所示的步驟中，於保護膜51上形成B階段狀態(半固化狀態)的絕緣層54A(第三絕緣層)以覆蓋連接端子53。當絕緣層54A的材料為絕緣樹脂片材時，將絕緣樹脂片材層合於保護膜51的上表面。然而，於此步驟中，並未將絕緣樹脂片材熱固化，而使其仍在B階段狀態。在真空中層合絕緣層54A，可避免絕緣層54A中形成空洞。當絕緣層54A的材料為絕緣樹脂液或膏時，藉由例如印刷或旋塗將絕緣樹脂液或膏塗覆於保護膜51的上表面。然後，將塗覆的絕緣樹脂液或膏預烘至B階段狀態。
上述製程製造本實施例的上晶片4。
其次，於圖11A所示的步驟中，將製得的上晶片4配置於下晶片3的上方，其中，連接端子34係形成於貫通電極32的上端面32B上。例如，下晶片3位於連接端子34之側的表面係與上晶片4位於電極墊52P之側的表面相對。因此，下晶片3的連接端子34係與電極墊52P上所形成的連接端子53相對。
然後，於圖11B所示的步驟中，上晶片4的連接端子53以覆晶接合的方式與對應之其上形成有連接端子34的貫通電極32接合。例如，當將下晶片3的絕緣層31的上表面黏著至上晶片4的絕緣層54A的下表面時，上晶片4的連接端子53穿透半固化狀態的絕緣層54A而與下晶片3的連接端子34接觸。此將連接端子34及53電性連接。此處，當於連接端子34或連接端子53之至少一者上使用焊料，使焊料熔融及固化，以便將連接端子34與連接端子53連接。當絕緣層54係由ACF或ACP所製得時，藉由將絕緣層54(ACF或ACP)配置於連接端子53與連接端子34之間，並推壓絕緣層54，則絕緣層54之位於相對的連接端子34與53之間的部分，被強力推壓而於厚度方向具導電性。此將連接端子34及53電性連接。當連接端子34電性連接至連接端子53時，上晶片4的電極墊52P藉由連接端子53及34電性連接至貫通電極32。此經由貫通電極32，可使上晶片4的電極墊52P與佈線基材2的電極墊20P電性連接。將上晶片4堆疊於下晶片3上的方法的實例包括使用接合工具(bonding tool)將下晶片3與上晶片4熱壓縮的方法、及使用迴焊技術的方法。在堆疊期間或之後進行加熱，將B階段狀態的絕緣層54A於固化溫度或更高的溫 度下，加熱一段預定時間及熱固化。結果，熱固化的絕緣層54的下表面黏合至絕緣層31的上表面，並且，熱固化的絕緣層54覆蓋貫通電極32、連接端子34及53、及電極墊52P。此處，絕緣層54的材料與形成於絕緣層54下方的絕緣層31的材料為相同。此避免因絕緣層54的材料與絕緣層31的材料之間的物理性質(熱膨脹係數等等)差異，而引起絕緣層54與絕緣層31之間界面處發生脫層(delamination)。
其次，於圖12所示的步驟中，形成封裝樹脂5以將堆疊於佈線基材2上的半導體晶片3及4密封。例如，當使用可熱固化的模塑樹脂(mold resin)做為封裝樹脂5時，將圖11B所示之結構置於模(die)中，將一模塑樹脂填入模中，對模塑樹脂施加壓力(例如5至10MPa)。然後，將模塑樹脂加熱(加熱溫度為例如180℃)及固化，形成封裝樹脂5。
然後，於圖12所示的步驟中，於佈線基材2的外部連接墊23P上形成外部連接端子24。每一外部連接端子24可各為焊料凸塊。依據上述製程而製得本實施例之半導體封裝物1。
於本實施例中，圖3至8所示的製程為第一方法之實例，圖9所示的製程為第二方法之實例，圖10所示的製程為第三方法之實例，圖11所示的製程為第四方法之實例。
第一實施例具有下述優點。
(1)於下晶片3中，貫通電極32的上端面實質上與絕緣層31的位於半導體基材30的第二表面30B這一側的第一表面31A齊平。因此，下晶片3的上表面(即，位於下晶片3與上晶片4之間的縫隙中的下表面)是平的。當下晶片3與上晶片4之間填充底部填充材料時，所要填入底部 填充材料的表面其階梯高度差為小。此可改善底部填充材料的流動性及底部填充材料的填充性質。再者，因為底部填充材料中不會形成空洞，所以改善了下晶片3與上晶片4之間的電性連接的可靠性。
(2)形成絕緣膜33，使其完全覆蓋貫通孔30X的壁面及開口31X的全部壁面。再者，形成金屬膜36，使其覆蓋絕緣膜33。金屬膜36是金屬阻障層，其可阻礙銅從導電層32A擴散至絕緣膜33及絕緣層31。此改善半導體晶片3在平面方向的絕緣可靠性。
(3)連接端子34係形成於貫通電極32的上端面32B上，在將上晶片4翻轉倒置以與下晶片3接合時，成為接合墊。因此，當將上晶片4翻轉倒置做接合時，焊料的濕潤性(wettability)是足夠的。當未形成連接端子34時，焊料的濕潤性也許不足夠。因此，由於焊料的濕潤性充足，可維持連接的可靠性。
(4)當將絕緣層31、絕緣膜33、及導電層32A薄化以形成貫通電極32時，於絕緣層31、絕緣膜33、及導電層32A上進行碾磨(grinding)。因為碾磨(grinding)是均勻的移除絕緣層31、絕緣膜33、及導電層32A，不論其材料為何，因此貫通電極32的上端面可與絕緣層31的第一表面31A齊平。此可形成平滑面。由於碾磨(grinding)是進行直到最淺的凹槽60X中所形成的導電層32A的上表面曝露出為止，各凹槽60X的深度可變得相同。
再者，因為碾磨(grinding)不像CMP，碾磨(grinding)不使用化學藥劑(例如研磨液)，所以可減少處置這類液體的成本，而可減少製造成本。
(5)於上晶片4的下表面這一側(與下晶片3相對的表面)形成半固化狀態的絕緣層54A。在將上晶片4疊合至下晶片3後，將絕緣層54熱固化。絕緣層54因此有與底部填充材料相同的功能。當將上晶片4疊合至下晶片3時，半固化狀態的絕緣層54A變形而覆蓋連接端子34及53及電極墊52P。此阻礙底部填充材料中形成空洞的機會。再者，可省略填充底部填充材料的步驟。
(6)絕緣層54的材料及絕緣層54下方的絕緣層31的材料是具有相同組成的相同絕緣樹脂。因此在絕緣層54與絕緣層31之間的界面處不會發生脫層。在絕緣層54的材料及絕緣層31的材料之間的物理性質(熱膨脹係數等等)若有差異時，會導致脫層。
(7)下晶片3的連接端子係以無電電鍍所形成。上晶片4的連接端子53係以無電電鍍或電鍍所形成。進行濕式製程例如無電電鍍或電解鍍層，可輕易形成精細的薄膜端子。因此，可輕易增加針腳數目，並可輕易配置窄節距的接合墊。再者，連接端子34係以電解鍍層所形成。因此，相較於經由光蝕刻(photolithography)或使用遮罩(mask)形成連接端子34的方式，本實施例可降低製造成本，並可縮短製程。
參照圖13至16敘述第二實施例。
於第一實施例中，半導體封裝物1包括半導體晶片3及4二者疊合於佈線基材2上。於第二實施例中，半導體封裝物1A包括三或更多個(例如四個)半導體晶片疊合於佈線基材2上。
如圖13所示，半導體封裝物1A包括佈線基材2、安裝於佈線基材2上的半導體晶片3、疊合於半導體晶片3上的半導體晶片6a、6b及4、 以及將疊合於佈線基材2上的半導體晶片3、6a、6b及4予以密封的封裝樹脂7。半導體晶片3可為邏輯裝置(例如CPU或MPU)用的半導體晶片。半導體晶片6a、6b、及4各可為記憶裝置(例如DRAM或SDRAM)用的半導體晶片。半導體晶片3是在第一階段疊合的半導體晶片，半導體晶片6a是在第二階段疊合的半導體晶片，半導體晶片6b是在第三階段疊合的半導體晶片，及半導體晶片4是在第四階段疊合的半導體晶片。
將封裝樹脂7塗敷於佈線基材2上，將疊合的半導體晶片3、6a、6b、及4密封。封裝樹脂7的材料可為絕緣樹脂，例如環氧樹脂或聚醯亞胺樹脂。絕緣樹脂可為樹脂液、樹脂錠、或樹脂粉。填充封裝樹脂7的方法的實施例包括轉移成型、壓縮成型、射出成型及澆封。或者，可藉由塗敷樹脂膏的方式進行印製。
其次，將說明半導體晶片6a的結構。半導體晶片6a包括一半導體基材80、一絕緣層81(第一絕緣層)、複數個貫通電極82、一絕緣膜83、一佈線圖案90、複數個介質孔91、一絕緣層92(第二絕緣層)、複數個電極墊93P、一保護膜94、複數個連接端子95(第二連接端子)、一絕緣層96。半導體晶片6a的連接端子95以覆晶接合的方式與半導體晶片3的連接端子34接合。
於半導體基材80的第一表面80A(圖13的下表面)上形成半導體積體電路(圖未示出)。半導體積體電路具有形成於半導體基材80上的一擴散層(圖未示出)、層合於半導體基材80上的一絕緣層、及配置於層合的絕緣層中的複數個介質孔及佈線。複數個貫通孔80X係形成於半導體基材80中的特定位置，貫通孔80X從半導體基材80的第一表面80A延伸 至第二表面80B(圖13的上表面)。半導體基材80的材料可為矽(Si)。半導體基材80的厚度約為例如30至200μm。半導體基材80為例如一薄化的Si晶圓的片段。
絕緣層81覆蓋半導體基材80的第二表面80B(其表面係堆疊著半導體晶片6a)。於絕緣層81之相對於貫通孔80X的位置，形成複數個開口81X。開口81X與對應的貫通孔80X相通，並且具有與貫通孔80X實質上相同的直徑。
絕緣層81的材料可為絕緣樹脂，例如環氧樹脂或聚醯亞胺樹脂。例如，絕緣層81的材料可為絕緣樹脂黏著片材(例如NCF)、絕緣樹脂膏(例如NCP)、積建(build-up)樹脂(含填充料的環氧樹脂)或晶質聚合物液。絕緣層81的材料可為非等向導電樹脂的黏著片材(例如ACF)、或非等向導電樹脂的黏著膏(例如ACP)。絕緣層81的厚度約為例如0.1至50μm。
絕緣膜83覆蓋半導體基材80的第一表面80A、貫通孔80X的全部壁面、及開口81X的全部壁面。絕緣膜83可為由SiN或SiO2製得的無機絕緣膜。絕緣膜83的厚度約為例如0.1至1.0μm。
貫通電極82填入覆蓋著絕緣膜83的貫通孔80X及開口81X中。貫通電極82的下端面實質上與半導體基材80的第一表面80A上的絕緣膜83齊平。貫通電極82的下端面與佈線圖案90電性連接。
貫通電極82的上端面(第一端面)82B實質上與絕緣層81的第一表面81A(與半導體基材80接觸的表面的相對面)齊平，絕緣層81係位於半導體基材80的第二表面80B的這一側。例如，各貫通電極82從上方看 來為圓形，具有約5至20μm的直徑。貫通電極82的節距為例如約20至200μm。
於貫通電極82的上端面82B上形成連接端子84。連接端子84可為Sn層、Ni層/Sn層、Au層、Ni層/Au層(將Ni層與Au層以此順序層合而形成的金屬層)、Pd層/Au層(將Pd層與Au層以此順序層合而形成的金屬層)、或Ni層/Pd層/Au層(將Ni層、Pd層、與Au層以此順序層合而形成的金屬層)。各Sn層、Ni層、Au層、及Pd層各可為藉由無電電鍍方式形成的金屬層(無電電鍍金屬層)。當連接端子84為Ni層/Au層時，連接端子84的厚度可為Ni層具有約0.1至5.0μm的厚度、及Au層具有約0.001至1.0μm的厚度。當連接端子84為Ni層/Pd層/Au層時，連接端子84的厚度可為Ni層具有約0.1至5.0μm的厚度、Pd層具有約0.01至0.3μm的厚度、及Au層具有約0.001至1.0μm的厚度。
佈線圖案90係形成於覆蓋半導體基材80的第一表面80A的絕緣膜83的下表面上。佈線圖案90的第一端連接至貫通電極82的下端面，及佈線圖案90的第二端經由介質孔91連接至電極墊93P。即，佈線圖案90與介質孔91將貫通電極82與電極墊93P電性連接。佈線圖案90及介質孔91的材料可為銅。
絕緣層92係形成以覆蓋佈線圖案90。供曝露部分佈線圖案90用的複數個開口，係形成於絕緣層92中的特定位置。介質孔91係形成於開口中。絕緣層92的材料可為具有低介電常數的低介電材料(所謂Low-k材料)。低介電材料的實例包括SiOC、SiOF、及有機聚合物。絕緣層92的介電常數為例如約3.0至3.5。絕緣層92的厚度為例如約0.5至2 μm。
佈線層93係形成於各介質孔91的下表面上。佈線層93的形狀自上方看來較介質孔91的形狀大。佈線層93的材料可為鋁(Al)。佈線層93的材料可為Cu/Al合金或Cu/Al/Si合金。
保護膜94係形成於絕緣層92的下表面上，以覆蓋絕緣層92的下表面及部分佈線層93。保護膜94具有複數個開口，用以曝露部分之佈線層93以做為電極墊93P。保護膜94係一種膜，以保護形成於半導體基材80的第一表面80A這一側的半導體積體電路(圖未示出)，亦稱為鈍化膜。保護膜94可為SiN膜或PSG膜。保護膜94可為將一聚醯亞胺層層合於SiN膜或PSG膜上而形成的層合層(laminated layer)。
連接端子95係分別形成於電極墊93P上。連接端子95電性連接至貫通電極82及半導體積體電路(圖未示出)。當將半導體晶片6a疊合於半導體晶片3上時，連接端子95藉著半導體晶片3的連接端子34與貫通電極32電性連接。因此，半導體晶片6a的貫通電極82是藉著佈線圖案90、介質孔91、電極墊93P、連接端子95、及連接端子34與對應的半導體晶片3的貫通電極32電性連接。即，半導體晶片3藉由貫通電極32及82與半導體晶片6a電性連接。
連接端子95各可為Ni層/Au層/Sn層(藉由將Ni層、Au層及Sn層以此順序層合所得的金屬層)或Ni層/Pd層/Au層/Sn層(藉由將Ni層、Pd層、Au層及Sn層以此順序層合所得的金屬層)，其係藉由鋁的浸鋅處理(Al zincate)或無電電鍍所形成。連接端子95各可為Ni層/Au層(藉由將Ni層及Au層以此順序層合所得的金屬層)、或Ni層/Pd層/Au層(藉由將Ni 層、Pd層及Au層以此順序層合所得的金屬層)，其係藉由鋁的浸鋅處理(Al zincate)或無電電鍍所形成。如圖1中之連接端子45及金屬層46，各連接端子95可為在圓柱狀連接凸塊上所形成的焊料層。於此例中，連接凸塊的材料可為Cu層，焊料層的材料可為無鉛焊料。
當半導體晶片6a疊合於半導體晶片3上時，絕緣層96係形成於保護膜94的下表面，以覆蓋半導體晶片6a的連接端子95及半導體晶片3的連接端子34及貫通電極32。絕緣層96增加半導體晶片3的連接端子34與半導體晶片6a的連接端子95的連接強度。再者，絕緣層96可抑制貫通電極32的腐蝕及電遷移的發生。絕緣層96亦維持貫通電極32的可靠性。絕緣層96的材料與最上層的絕緣層31(即，當半導體晶片6a疊合於半導體晶片3時，與絕緣層96接觸的絕緣層31)是相同的絕緣樹脂。即，絕緣層96的材料可為絕緣樹脂，例如環氧樹脂或聚醯亞胺樹脂。例如，絕緣層96的材料可為一絕緣樹脂的黏著層(例如NCF)、絕緣樹脂膏(例如NCP)、積建樹脂(含填充料的環氧樹脂)或晶質聚合物液。絕緣層96的材料可為非等向性導電樹脂黏著層(例如ACF)、或非等向性導電樹脂膏(例如ACP)。絕緣層96的厚度為例如約5至15μm。
其次，將說明半導體晶片6b的結構。因為半導體晶片6b實質上具有與半導體晶片6a相同的結構，所以使用相同的符號標示相同的構件，而不再詳述。
如半導體晶片6a，半導體晶片6b包括貫通電極82、形成於貫通電極82的上表面的連接端子84、形成於貫通電極82的下側並與貫通電極82電性連接的電極墊93P、形成於電極墊93P上的連接端子95、及 覆蓋連接端子95的絕緣層96。半導體晶片6b的連接端子95以覆晶接合的方式與半導體晶片6a的連接端子84接合。半導體晶片6a及6b藉著形成於半導體晶片6a及6b二者中的貫通電極82，彼此電性連接。將半導體晶片4的連接端子53以覆晶接合的方式與半導體晶片6b的連接端子84接合。半導體晶片4及6b藉著形成於半導體晶片6b中的貫通電極82彼此電性連接。
接著，說明製造半導體封裝物1A的方法。首先，參照圖3至圖9所述之製程可製得圖14中的結構，其中，半導體晶片3係覆晶接合至佈線基材2。半導體晶片6a可經由與圖3至10中所示實質上相同的製造步驟製得。因此不再詳述此等步驟。類似於圖3A至8C中所示的製造步驟，可用以形成半導體基材80、絕緣層81、貫通電極82、絕緣膜83、連接端子84、佈線圖案90、介質孔91、絕緣層92、保護膜94、及連接端子95。然而，可用圖10B所示的步驟取代圖5A至6A所示的步驟形成連接端子95。於保護膜94的下表面上形成B階段狀態(半固化狀態)的絕緣層96A(第三絕緣層)以覆蓋連接端子95。當絕緣層96A的材料為絕緣樹脂片材時，將絕緣樹脂片材層合於保護膜94的下表面。然而，於此步驟中，並未將絕緣樹脂片材熱固化，而使其仍處於B階段狀態。在真空中層合絕緣層96A，可避免於絕緣層96A中形成空洞。當絕緣層96A的材料為絕緣樹脂液或膏時，藉由例如印刷或旋塗，將絕緣樹脂液或膏塗敷於保護膜94的上表面。然後，將塗敷的絕緣樹脂液或膏預烘至B階段狀態。此製造半導體晶片6a。
於圖14所示的步驟中，將製得的半導體晶片6a配置於半導體 晶片3的上方，其中，連接端子34係形成於貫通電極32的上端面32B上。例如，半導體晶片3位於連接端子34之側的表面，係與半導體晶片6a位於電極墊93P之側的表面相對。因此，半導體晶片3的連接端子34係與電極墊93P上所形成的連接端子95相對。
然後，於圖15所示的步驟中，半導體晶片6a的連接端子95以覆晶接合的方式與其上形成有連接端子34的貫通電極32接合。結果，半導體晶片6a的電極墊93P藉著連接端子95及連接端子34，與貫通電極32電性連接。因此，半導體晶片6a的電極墊93P藉著貫通電極32與佈線基材2的電極墊20P電性連接。將半導體晶片6a疊合於半導體晶片3上的方法的實例包括使用接合工具(bonding tool)將半導體晶片3與6a進行熱壓縮的方法、及進行迴焊製程的方法。在堆疊期間或之後進行加熱，將B階段狀態的絕緣層96A於固化溫度或更高的溫度下加熱一段預定時間及熱固化。結果，熱固化的絕緣層96覆蓋貫通電極32、連接端子34及95、及電極墊93P。此時，因為絕緣層96的材料與形成於絕緣層96下方的絕緣層31的材料相同，此使得絕緣層96與絕緣層31之間界面處不易發生脫(離)層，當絕緣層96的材料與絕緣層31的材料之間的物理性質(熱膨脹係數等等)有差異時會引起脫層。
然後，於圖16所示的步驟中，使半導體晶片6b的連接端子95覆晶接合至半導體晶片6a的貫通電極82。然後，使半導體晶片4的連接端子53覆晶接合至半導體晶片6b的貫通電極82。形成封裝樹脂7，以將堆疊於佈線基材2上的複數個半導體晶片3、6a、6b及4密封。此製得本實施例之半導體封裝物1A。
第二實施例具有與第一實施例相同的優點。
將參照圖17及18說明第三實施例。本實施例與第一實施例不同處，在於下晶片與上晶片之間的連接。下列敘述將著重在與第一實施例不同處。
圖17及18繪示本實施例之半導體封裝物1B在製造期間的狀態。例如，圖17繪示圖11所示步驟(即，將上晶片4A疊合於與佈線基材2覆晶接合的下晶片3A上的步驟)中的半導體封裝物1B。
如圖17A所示，於本實施例的下晶片3A中，連接端子34A係由貫通電極32的上端面32B所形成。連接端子34A可為一初步焊料(preliminary solder)(預焊料)。初步焊料的材料可為無鉛焊料，例如Sn-3.5Ag、Sn-2.5Ag、Sn-3.0Ag-0.5Cu、或Sn-Cu。例如，連接端子34A(初步焊料)可藉由將球狀超微細粉末(例如，直徑10μm或更少)黏於貫通電極32的上端面32B、及將焊料粉末熔融而形成。或者，連接端子34A可藉由將焊料膏塗敷於貫通電極32的上端面32B、或將焊球安裝於貫通電極32的上端面32B，然後進行迴焊製程而形成。
於本實施例的上晶片4A中，於保護膜51的開口51X曝露出的各電極墊52P上形成連接端子55。連接端子55經由電極墊52P電性連接至半導體積體電路(圖未示出)。各連接端子55為圓柱狀連接凸塊，其自電極墊52P的下表面向下延伸。連接端子55相對於下晶片3A中形成的連接端子34A。連接端子55的高度為例如約20至40μm。連接端子55的直徑為例如約10至40μm。連接端子55的節距為例如約30至60μm。連接端子55的材料可為銅或銅合金。
於各連接端子55的下表面上形成一焊料層(solder layer)56。焊料層56可為鍍的無鉛焊料(例如Sn-2.5Ag)。焊料層56的高度為例如約5至10μm。可使用與形成連接端子45及金屬層46(例如，參照圖5A至圖6A)相同的方法形成連接端子55及焊料層56。以B階段狀態的絕緣層54A覆蓋連接端子55及焊料層56。
於圖17A所示的步驟中，將上晶片4A配置於其上形成有連接端子34A的下晶片3A上方。例如，使下晶片3A位於連接端子34A之側的表面與上晶片4A位於電極墊52P之側的表面相對。因此，下晶片3A的連接端子34A與上晶片4A的連接端子55相對。
其次，於圖17B所示的步驟中，上晶片4A的連接端子55以覆晶接合的方式與其上形成有連接端子34A的貫通電極32接合。例如，將上晶片4A的絕緣層54A的下表面黏著於下晶片3A的絕緣層31的上表面；及，上晶片4A的連接端子55與焊料層56穿透半固化狀態的絕緣層54A，並且電性連接至連接端子34A。藉由例如將焊料層56及連接端子34A加熱至約230至260℃使焊料熔融及固化，而使連接端子55與連接端子34A連接。此時，由於焊料層56及連接端子34A係由焊料所製得，焊料層56與連接端子34A熔融成合金而形成焊料凸塊34B。藉由焊料凸塊34B，貫通電極32與連接端子55電性連接。然後，藉著連接端子55，上晶片4A的電極墊52P與貫通電極32電性連接。因此，藉著貫通電極32，上晶片4A的電極墊52P佈線基材2的電極墊20P電性連接。在堆疊期間或之後進行加熱，將B階段狀態的絕緣層54A於固化溫度或更高的溫度下加熱一段預定時間及熱固化。結果，熱固化的絕緣層54的下表面黏合 至絕緣層31的上表面，再者，熱固化的絕緣層54覆蓋貫通電極32、焊料凸塊34B、連接端子55、及電極墊52P。
然後，於圖18所示的步驟中，形成封裝樹脂5以將疊合於佈線基材2上的複數個半導體晶片3A及4A密封。然後，將外部連接端子24形成於佈線基材2的外部連接墊23P上。此製得本實施例的半導體封裝物1B。
第三實施例除了具有第一實施例的優點(1)至(6)，還具有下列優點。
(8)分別於下晶片3A的貫通電極32的上端面32B上，形成由初步焊料製得的連接端子34A。圓柱狀連接端子55及焊料層56係形成於上晶片4A的電極墊52P上。因此，下晶片3A的焊料可與上晶片4A的焊料接合。相較於僅在下晶片3A上或上晶片4A上形成焊料時，本法的濕潤性有改善，並且由於增加接合焊料的量(接合容積(solder volume))，連接強度亦有改善。因此，改善了下晶片3A與上晶片4A之間連接的可靠性。
藉由將超微細焊料粉黏於貫通電極的上端面32B上，將焊料粉熔融，可形成微細連接端子34。因此，可輕易增加針腳數目，並可輕易配置較窄節距的接合墊。
將參照圖19說明第四實施例。於各上述實施例中，形成於貫通電極32及82的上端面32B及82B上的連接端子34及84的材料，與形成於電極墊52P及93P上的連接端子53及95的材料的組合是可改變的。例如，當各連接端子34及84為Ni層/Au層時，各連接端子53及95較佳為Ni 層/Au層/Sn層或Ni層/Pd層/Au層/Sn層。當各連接端子34及84為Sn層時，各連接端子53及95較佳為Ni層/Au層或Ni層/Pd層/Au層。
當各連接端子34及84為Ni層/Au層時，連接端子53及95較佳為，形成於圓柱狀連接凸塊上的焊料層。於此例中，例如，如圖19A所繪示，連接端子34係為Ni層/Au層，其形成於下晶片3的貫通電極32的上端面32B上，及，圓柱狀連接端子55及焊料層56從上晶片4A的電極墊52P的下表面向下延伸。於圖19A所示的步驟中，上晶片4A係配置於下晶片3的上方，使得下晶片3的連接端子34與上晶片4A的連接端子55相對。然後，如圖19B所示，上晶片4A的連接端子55以覆晶接合的方式與其上形成有連接端子34A的貫通電極32接合。例如，將上晶片4A的絕緣層54A的下表面黏著於下晶片3的絕緣層31的上表面，及，上晶片4A的連接端子55與焊料層56穿透半固化狀態的絕緣層54A，並且電性連接至連接端子34。此時，將焊料層56加熱至約230至260℃使焊料熔融及固化。此使得連接端子55與連接端子34以焊料層56電性連接。以此方式，藉著連接端子55、焊料層56、及連接端子34，使上晶片4A的電極墊52P與貫通電極32電性連接。
將參照圖20及21A說明第五實施例。本實施例與第三及第四實施例不同處在於貫通電極32的上端面32B上所形成的連接端子的形狀。下文的敘述將著重在第五實施例與第三及第四實施例的不同。
如圖20A所繪示，半導體封裝物1C包括一佈線基材2、安裝於佈線基材2上的一半導體晶片(下晶片)3B、疊合於半導體晶片3B上的一半導體晶片(上晶片)4A、及用以將疊合於佈線基材2上的半導體晶片3B 及4A密封的一封裝樹脂5。半導體晶片3B是半導體裝置的一個實例。
下晶片3B包括一半導體基材30、一絕緣層31、複數個貫通電極32、一絕緣膜33、一佈線圖案40、複數個介質孔41、一絕緣層42、複數個電極墊43P、一保護膜44、複數個連接端子45、及複數個連接端子100(第一連接端子)。使下晶片3覆晶接合於佈線基材2。
可藉由環氧樹脂或聚醯亞胺所製得的有機絕緣膜，或由SiN或SiO2所製得的無機絕緣膜形成絕緣層31。
如圖20B所繪示，各連接端子100係形成於絕緣層31的第一表面31A、絕緣膜33的上表面、及貫通電極32的上端面32B上。連接端子100具有較貫通電極32大的直徑。因此，於絕緣層31的第一表面31A、絕緣膜33的上表面、及貫通電極32的上端面32B上，形成具有較貫通電極32大的直徑的連接端子100。連接端子100覆蓋貫通電極32(導電層32A及晶種層35)的上端面32B的一部份、絕緣膜33的上表面(絕緣膜33覆蓋金屬膜36的側面)、及絕緣層31的第一表面31A的一部份(絕緣層31覆蓋絕緣膜33的側面)。此處，例如，貫通電極32從上方看來為圓形，具有約5至20μm的直徑。貫通電極32的節距為例如約20至200μm。連接端子100從上方看來為圓形，具有約5.2至30μm的直徑。連接端子100的厚度為例如約0.1至10μm。連接端子100的直徑，可由貫通電極32直徑加上連接端子100厚度的約大於二倍值所獲得。
各連接端子100可為Ni層/Au層、Ni層/Pd層/Au層、Ni層/Sn層、或Sn層。各Ni層、Au層、Pd層、及Sn層可為例如藉由進行無電電鍍所形成的金屬層(無電電鍍金屬層)。當連接端子100為Ni層/Pd層/Au層 時，Ni層厚度為例如約0.1至10μm、及Pd層與Au層各厚度為例如約0.001至1.0μm。當連接端子100為Ni層/Au層時，Ni層厚度為例如約1.0至5.0μm，及Au層厚度為例如約0.001至1.0μm。當連接端子100為Ni層/Sn層時，Ni層厚度為例如約0.1至10μm，及Sn層厚度為例如約0.1至10μm。當連接端子100為Sn層時，Sn層厚度為例如約1至10μm。於本實施例中，Ni層101及Au層102以此順序層合於絕緣層31的第一表面31A及貫通電極32的上端面32B上，以形成連接端子100。Au層102完全覆蓋Ni層101的表面(上表面及側表面)。
如圖20A所繪示，當將上晶片4A疊合於下晶片3B上時，連接端子100藉由焊料層56與上晶片4A的連接端子55接合。再者，連接端子100藉著焊料層56與連接端子55電性連接。
其次，將參照圖21說明製造半導體封裝物1C的方法(製造連接端子100的方法)。
首先，進行圖3A至7C所繪示的步驟的製程，以形成圖21A所示的結構。即，製得其中絕緣層31的第一表面31A實質上與貫通電極32的上端面32B齊平的結構。
其次，於圖21B至21D所繪示的步驟中，藉著進行無電電鍍，於貫通電極32的上端面32B及絕緣層31的第一表面31A上，形成直徑較貫通電極32大的Ni層101。詳言之，當對圖21A所繪示的結構進行無電電鍍Ni時，首先，如圖21B所示，於貫通電極32的上端面32B上沉積一無電電鍍Ni膜101A。然後，如圖21C及圖21D所示，進一步繼續無電電鍍Ni而等向性沉積無電電鍍Ni膜101A。結果，Ni層101具有較絕緣膜33 的上表面及絕緣層31的第一表面31A上所形成的貫通電極32大的直徑。因此，Ni層101的直徑實質上等於大於Ni層101厚度(即，從貫通電極32的上端面32B至Ni層101的上表面的厚度)二倍的值與貫通電極32直徑的總合。Ni層101覆蓋絕緣膜33的上表面及貫通電極32(絕緣膜33)周圍的絕緣層31的第一表面31A的一部分。
然後，於圖21E所示的步驟中，藉著進行無電電鍍，於Ni層101上形成Au層102。詳言之，當對圖21D所示的結構進行無電電鍍Au時，於如圖21E所示的金屬Ni層101的表面(側表面及上表面)上沉積了一無電電鍍Au膜。此形成Au層102，其覆蓋Ni層101的側表面及上表面。
此製程可於貫通電極32、絕緣層31、及絕緣膜33上形成連接端子100，其包括Ni層101及Au層102。
第五實施例除了具有第一實施例的優點(1)至(7)，還具有下列優點。
(9)於絕緣層31的第一表面31A、絕緣膜33的上表面、及貫通電極32的上端面32B上形成具有較貫通電極32大的直徑的連接端子100。因此，相較於僅在貫通電極32的上端面32B形成連接端子時，下晶片3B的連接端子100與上晶片4A的連接端子55之間的接合面積增加。此增加連接端子100與連接端子55之間的連接強度。因此，改善下晶片3B與上晶片4A之間連接的可靠性。
第五實施例的修飾例
如圖22所示的，可修飾連接端子100周圍的結構。詳言之，可於絕緣層31上形成一突出部31B(第一突出部)，從絕緣層31的第一表面 31A向上突出(向著半導體基材30的相對側(opposite side))。貫通電極32及絕緣膜33可與突出部31B的上表面31C實質上齊平。意即，部分的貫通電極32及絕緣膜33從絕緣層31的第一表面31A向上突出。連接端子100可形成於從絕緣層31的第一表面31A突出的貫通電極32的上端面32B、絕緣膜33的上表面、及突出部31B的上表面31C上。因此，形成連接端子100，其從絕緣層31的第一表面31A突出。藉由使連接端子100(墊)從絕緣層31的第一表面31A突出，例如，即使上晶片4A的連接端子55具有小的直徑，亦可輕易將連接端子100與連接端子55連接。詳言之，當連接端子55的直徑小，在絕緣層31的第一表面31A不平坦(uneven)時，連接端子55與連接端子100之間可能會發生連接失敗。然而於此修飾例中，因為，連接端子100從絕緣層31的第一表面31A突出，即使當絕緣層31的第一表面31A不平坦時，影響亦有限。此使得連接端子55與連接端子100以令人滿意的方式連接。
從絕緣層31的第一表面31A到連接端子100的下表面的高度(厚度)，意即，突出部31B的高度為例如約0.1至10μm。
接著，將參照圖23說明突出部31B及連接端子100的製法。
首先，進行圖3A至7A所示的步驟製造圖23A所繪示的結構。此獲得一結構，其中部分之絕緣膜33、導電層32A、及金屬膜36及37從基材30C曝露出。
接著，於圖23B所示的步驟中，形成絕緣層31以覆蓋基材30C的第二表面30B及從基材30C曝露出的絕緣膜33。於此步驟中，絕緣層31與基材30C的第二表面30B及從基材30C曝露出的絕緣膜33的側表面 與上表面共形(shaped in conformance)。換言之，形成絕緣層31，使得從基材30C的第二表面30B上突出的導電層32A，不會如圖7B所示的步驟被內嵌(embed)於絕緣層31的厚度中。當絕緣層31的材料為由SiN、SiO2、或類似者所形成的無機絕緣膜時，絕緣層31可藉由化學氣相沉積法(CVD)形成。當絕緣層31的材料是由環氧樹脂或類似者所製得的有機絕緣膜時，例如，可將樹脂膜層合於基材30C的第二表面30B上，及然後在約150℃至190℃進行加熱及固化，同時推壓，以形成絕緣層31。
其次，於圖23C所示的步驟中，利用例如CMP裝置或類似者移除(研磨(polish))導電層32A上的絕緣膜33、及金屬膜36及37。例如進行移除，直到曝露出導電層32A的上表面(端面)為止，並在開始移除絕緣層的第一表面31A之前結束。因此，導電層32A的上表面從絕緣層31的第一表面31A向上突出。於此步驟中，於絕緣層31中形成包括突出部31B的開口31X。再者，於覆蓋著絕緣膜33的貫通孔30X及開口31X中，形成包括導電層32A及晶種層35的貫通電極32。此時，部分的貫通電極32及絕緣膜33從絕緣層31的第一表面31A向上突出。從第一表面31A向上突出的突出部31B係形成於絕緣層31上。再者，突出部31B的上表面31C、貫通電極32的上端面32B、及絕緣膜33的上表面實質上彼此齊平。
然後，藉著對如圖23C所示之結構進行無電電鍍，於如圖22所示的貫通電極32的上表面、絕緣膜33、及突出部31B上形成包括Ni層101及Au層102的連接端子100。
然後，使形成於上晶片4A上的連接端子55與形成於下晶片3B上的連接端子100接合。例如，於類似於圖11B所示的步驟中，於上晶 片4A的下側上形成半固化狀態的絕緣層，並黏合至絕緣層31。此時，上晶片4A的連接端子55及焊料層56穿透半固化狀態的絕緣層，並與連接端子100電性連接。當連接端子100從絕緣層31的第一表面31A向上突出時，可輕易將連接端子100及連接端子55之間的絕緣樹脂移除。此改善連接端子100及連接端子55的連接可靠性。
圖22所示的連接端子100覆蓋著貫通電極32的上端面32B、絕緣膜33的上表面、及突出部31B的上表面31C。但，可修飾連接端子100的形狀。
例如，如圖24所示，連接端子100可完全覆蓋從絕緣層31的第一表面31A向上突出的突出部31B、絕緣膜33、及貫通電極32的表面。例如，Ni層101除了覆蓋突出部31B的側表面之外，還覆蓋突出部31B的上表面31C、絕緣膜33的上表面、及貫通電極32的上端面32B。再者，Ni層101亦覆蓋位於突出部31B周圍的部分絕緣層31的第一表面。Au層102與Ni層101共形，而覆蓋Ni層101的表面(上表面及側表面)。可藉由在形成Ni層101時增加無電電鍍Ni的處理時間，而形成此種亦覆蓋部分絕緣層31的第一表面31A的連接端子100。
於此結構中，當將連接端子100與對應的連接端子55電性連接時，可增加焊料層56的接合面積。此可增加連接端子100與連接端子55之間的接合強度。
例如，如圖25所示，Ni層101覆蓋突出部31B的上表面31C、絕緣膜33的上表面、及貫通電極32的上端面32B，Ni層101可具備從突出部101B的外側面橫向突出的突出部101B，以形成Au層102，Au層102 覆蓋Ni層101的全部表面，包括突出部101B的下表面。意即，Au層102係形成以覆蓋Ni層101的上表面及側表面、以及突出部101B的下表面(部分Ni層101的下表面)。可藉由在形成Ni層101時增加無電電鍍Ni的處理時間，而形成包括Ni層101及Au層102的連接端子100。
於圖22至25所示的修飾例中，絕緣層31(突出部31B)、絕緣膜33、及貫通電極32此三者均有部分，從絕緣層31的第一表面31A向上突出。於另外的例子中，僅有絕緣層31(突出部31B)、絕緣膜33、或貫通電極32三者的部分，從絕緣層31的第一表面31A向上突出。
例如，如圖26所示，於一部分絕緣層31(突出部31B)、絕緣膜33、及貫通電極32三者中，可僅有貫通電極32(導電層32A及晶種層35)從絕緣層31的第一表面31A向上突出。即，可形成貫通電極32使其包括一突出部32C(突出端)，其從絕緣層31曝露出並從絕緣層31的第一表面31A向上突出。再者，於此例中，可形成連接端子100，使其完全覆蓋突出部32C的表面(上表面及側表面)、絕緣膜33的上表面、及形成於貫通電極32周圍的絕緣層31的第一表面31A的一部分。從絕緣層31的第一表面31A到突出部32C的上表面的高度，即，突出部32C的高度，為例如約1至10μm。將說明圖26中的貫通電極32及連接端子100的製法。
首先，於圖27A所示的步驟中，在圖3A至7A所示的步驟之後，進行圖23B所示的步驟。此形成絕緣層31，其覆蓋基材30C的第二表面30B及從基材30C曝露出的絕緣膜33。
其次，於圖27B及27C所示的步驟中，使用例如CMP裝置移除(研磨(polish))形成於導電層32A上的絕緣膜33及金屬膜36及37。此時， 可調整CMP的研磨液(slurry)材料及研磨墊(polishing pad)硬度。此可調整各絕緣層31、絕緣膜33、晶種層35、及導電層32A的磨除量(polished amount)。於此例中，藉調整研磨液材料及研磨墊硬度，使得絕緣層31及絕緣膜33的磨除量較晶種層35及導電層32A的磨除量大。因此，如圖27B及27C所示，晶種層35及導電層32A部分被留下來，而自未研磨移除的絕緣層31及絕緣膜33曝露出。進行使用CMP的研磨，直到絕緣層31的上表面與位於較絕緣膜33的上表面及第一表面31A為高的位置的第一表面31A齊平，如圖27C所示。此形成貫通電極32，其具有從絕緣層31的第一表面31A及絕緣膜33的上表面向上突出的突出部32C。於此步驟中，開口31X係形成於絕緣層31中。
然後，對如圖27C所示之結構進行無電電鍍而形成Ni層101，其除了覆蓋形成於貫通電極32周圍的絕緣膜33及絕緣層31的上表面的一部分之外，還覆蓋貫通電極32的上表面及側表面，如圖26所示。然後，藉著進行無電電鍍形成Au層102，使其覆蓋Ni層101的上表面及側表面，以形成包括Ni層101及Au層102的連接端子100。
如圖28至30所示，可修飾連接端子100周圍的結構。詳言之，絕緣層31可包括突出部31B，絕緣膜33的上表面可與突出部31B的上表面31C實質地齊平。再者，貫通電極32可包括一突出部32D(突出端)，其從絕緣膜33及突出部31B的上表面31C向上突出。此種結構可藉由例如進行圖27B所示步驟中且使用CMP的精磨(finishing polishing)而形成。再者，此結構可包括具有下列結構的連接端子100。
例如，如圖28所示，連接端子100可為形成於絕緣膜33及突出 部31B上，連接端子100除了覆蓋絕緣膜33的上表面及突出部31B的上表面31C之外，還完全覆蓋突出部32D的表面(側表面及上表面)。
例如，如圖29所示，Ni層101可包括從突出部31B的外表面向側面突出的突出部101B，及Au層102可完全覆蓋Ni層101的表面，包括Ni層101的下表面。
例如，如圖30所示，可形成連接端子100，使其完全覆蓋突出部32D的表面及完全覆蓋突出部31B及絕緣膜33的表面(側表面及上表面)。再者，可形成連接端子100，使其部分覆蓋形成於突出部31B周圍的絕緣層31的第一表面31A。
如圖31所示，可修飾連接端子100的結構及連接端子100周圍的結構。詳言之，貫通電極32的上端面32B可具有一凹陷(recess)32X，其延伸至貫通電極32(向著如圖31所示的下側)中。於此修飾例中，具有實質的半橢圓剖面並從絕緣層31的第一表面31A向著如圖31所示的下側延伸的凹陷32X，係形成於貫通電極32的上端面32B中。即，凹陷32X的底面是曲面(curved surface)，其從第一表面31A向下凹。再者，於此例中，可形成連接端子100(Ni層101)，使其填入凹陷32X，並覆蓋絕緣膜33的上表面、及形成於貫通電極32周圍的絕緣層31的第一表面31A的一部分。換言之，可使連接端子100具有一突出部，其從絕緣層31的第一表面31A向下突出(向貫通電極32)。
例如，於圖27B及27C所示的步驟中，使用CMP時，可調整研磨液材料及研磨墊硬度，使得晶種層35及導電層32A的磨除量大於絕緣層31及絕緣膜33的磨除量，以形成凹陷32X。
雖然於圖31所示的修飾例中，凹陷32X的底面是曲面，然而，如圖32所示，凹陷32X的底面可為一平面，其與絕緣層31的第一表面31A實質上平行。再例如，可於貫通電極32的上端面32B中，形成具有實質的四方形剖面並從絕緣層31的第一表面31A向著如圖32所示的下側延伸的凹陷32X。換言之，貫通電極32的上端面32B可較絕緣層31的第一表面31A低。
於圖31及32所示的修飾例中，絕緣膜33及貫通電極32的結構是可改變的。
例如，如圖33所示，絕緣膜33的一部分可從絕緣層31的第一表面31A向上突出。即，可形成絕緣膜33，其包括從絕緣層31的第一表面31A向上突出的突出部33A。再者，於此例中，可形成連接端子100，使其完全覆蓋突出部33A的表面(上表面及側表面)。例如，使用圖27B所示步驟中的CMP時，可調整研磨液材料及研磨墊硬度，使得晶種層35及導電層32A的磨除量大於絕緣層31及絕緣膜33的磨除量，及絕緣膜33的磨除量小於絕緣層31的磨除量，而形成突出部33A。
例如，如圖34所示，晶種層35中的金屬膜36的一部分可從絕緣層31的第一表面31A向上突出。即，可形成金屬膜36，使其包括一突出部36A，突出部36A從絕緣層31的第一表面31A向上突出。再者，於此例中，可形成連接端子100，使其完全覆蓋突出部36A的表面(上表面及側表面)。例如，使用圖27B所示步驟中的CMP時，調整研磨液材料及研磨墊硬度，使得金屬膜37及導電層32A的磨除量大於絕緣層31及絕緣膜33的磨除量，及金屬膜36的磨除量小於絕緣層31及絕緣膜33的磨 除量，而形成突出部36A。
可將圖22至34所示的第五實施例及修飾例中的絕緣層31、貫通電極32、絕緣膜33、及連接端子100，應用於第一及第二實施例的半導體晶片3以及第二實施例中的半導體晶片6a及6b。例如，當應用於半導體晶片3時，使用第五實施例及修飾例中的絕緣層31、貫通電極32、絕緣膜33、及連接端子34，而不使用圖1及13所示的絕緣層31、貫通電極32、絕緣膜33、及連接端子100。再者，當應用於半導體晶片6a及6b時，使用第五實施例及修飾例中的絕緣層31、貫通電極32、絕緣膜33、及連接端子100，而不使用絕緣層81、貫通電極82、絕緣膜83、及連接端子84。
圖22至34所示的各連接端子100的端面，可為圓形。
第六實施例
將參照圖35及36說明第六實施例。本實施例與圖22至34所示的第五實施例及修飾例不同處在於絕緣層31的第一表面31A上所形成的連接端子的形狀。下文的敘述將著重在與第五實施例不同之處。
如圖35A所繪示，半導體封裝物1D包括一佈線基材2、安裝於佈線基材2上的一半導體晶片(下晶片)3C、疊合於半導體晶片3C上的一半導體晶片(上晶片)4A、及用以將疊合於佈線基材2上的半導體晶片3C及4A密封的一封裝樹脂5。
下晶片3C包括一半導體基材30、一絕緣層31、複數個貫通電極32、一絕緣膜33、一佈線圖案40、複數個介質孔41、一絕緣層42、複數個電極墊43P、一保護膜44、複數個連接端子45、及複數個連接端 子110(第一連接端子)。使下晶片3覆晶接合於佈線基材2。
可藉由環氧樹脂或聚醯亞胺所製得的有機絕緣膜或由SiN或SiO2所製得的無機絕緣膜形成絕緣層31。
如圖35B所繪示，貫通電極32包括導電層32A及晶種層35。導電層32A具有一突出部32E(突出端)，其從絕緣層31的第一表面31A及絕緣膜33的上表面向上突出。突出部32E具有實質上半圓形或凸曲面的剖面。即，突出部32E具有從第一表面31A向上彎曲的上表面。此例的突出部32E包括具有實質的四方形剖面的第一部及具有實質的半圓形剖面且與第一部一體成型的第二部。晶種層35的上表面與絕緣膜33的上表面及絕緣層31的第一表面31A實質上齊平。
連接端子110係形成於絕緣層31的第一表面31A及絕緣膜33的上表面上。連接端子110的直徑比貫通電極32的直徑大。連接端子110完全覆蓋突出部32E的表面(上表面及側表面)及晶種層35的上表面。再者，連接端子110覆蓋絕緣膜33的上表面及覆蓋形成於絕緣膜33周圍的絕緣層31的第一表面31A的一部分。連接端子110與突出部32E共形。因此，與突出部32E類似，連接端子110具有實質上半圓形或凸曲面的剖面。即，連接端子110包括一上表面，其從第一表面31A向上彎曲。於此例中，連接端子110包括具有實質上四方形剖面的第一部及具有實質上半圓形剖面且與第一部一體成型的第二部。例如，各貫通電極32從上方看來為圓形，且具有約5至20μm的直徑。例如，各連接端子110從上方看來為圓形，且具有約5.2至30μm的直徑。連接端子110的厚度(從突出部32E的側面到連接端子110的側面的厚度)為例如約1至5μm。
各連接端子110可為Ni層/Au層、Ni層/Pd層/Au層、Ni層/Sn層、或Sn層。各Ni層、Au層、Pd層、及Sn層可為藉由進行無電電鍍所形成的金屬層(無電電鍍金屬層)。當連接端子110為Ni層/Pd層/Au層時，Ni層厚度為約0.1至5.0μm、及Pd層與Au層各厚度為約0.001至1.0μm。當連接端子110為Ni層/Au層時，Ni層厚度為約1.0至5.0μm，及Au層厚度為約0.001至1.0μm。當連接端子110為Ni層/Sn層時，Ni層厚度為約3.0μm，及Sn層厚度為約2.0μm。當連接端子110為Sn層時，Sn層厚度為約2.0μm。於本實施例中，連接端子110包括一Ni層111及一Au層112，Ni層111除了覆蓋晶種層35的上表面、絕緣膜33的上表面、及形成於絕緣膜33周圍的絕緣層31的第一表面31A之外，還完全覆蓋突出部32E的表面(上表面及側表面)，Au層112完全覆蓋Ni層111的表面。
如圖35A所繪示，當將上晶片4A疊合於下晶片3C上時，連接端子110藉由焊料層56與上晶片4A的連接端子55接合，以及，連接端子100藉著焊料層56與連接端子55電性連接。
其次，將參照圖36說明製造半導體封裝物1D的方法(此處，製造貫通電極32的突出部32E的方法)。
首先，於圖36A所示的步驟中，於圖3A至7A所繪示的步驟之後，進行圖23B所示的步驟。此形成絕緣層31，其覆蓋基材30C的第二表面30B及從基材30C曝露出的絕緣膜33。
其次，於圖36B及36C所示的步驟中，使用例如CMP裝置移除(研磨(polish))形成於導電層32A上的絕緣膜33及金屬膜36及37。此時，可調整研磨液材料及研磨墊硬度，使得絕緣層31、絕緣膜33、及晶種 層35的磨除量大於導電層32A的磨除量。因此，如圖36B及36C所示，導電層32A的一部分留下來而自未研磨移除的絕緣層31、絕緣膜33及晶種層35曝露出。再者，如圖36B及36C所示，於CMP中，藉由將導電層32A稍微研磨，使導電層32A的上表面圓化。換言之，於CMP中，調整研磨液材料及研磨墊硬度，使得導電層32A的上表面成為曲面。如圖36C所示，進行CMP的研磨，直到絕緣層31的上表面、絕緣膜33的上表面、以及位於較第一表面31A為高的位置晶種層35的上表面與第一表面31A齊平為止。於此步驟中，於絕緣層31中形成開口31X，以及，形成貫通電極32，貫通電極32包括具有突出部32E的導電層32A及晶種層35。
然後，對如圖36C所示之結構進行無電電鍍Ni，而形成Ni層111，其除了覆蓋晶種層35的上表面、絕緣膜33的上表面、及形成於絕緣膜33周圍的絕緣層31的第一表面31A的一部分之外，還覆蓋突出部32E的上表面及側表面，如圖35B所示。此時，無電電鍍Ni膜是等向性的沉積於突出部32E的表面上，形成Ni層111。因此，Ni層111與突出部32E共形。其次，藉著進行無電鍍Au，形成Au層112，使其覆蓋Ni層111的上表面及側表面，以形成包括Ni層111及Au層112的連接端子110。
然後，使形成於下晶片3C上的連接端子110接合至形成於上晶片4A上的連接端子55。例如，進行圖11B所示的製造步驟，以於黏至絕緣層31的上晶片4A的下側形成半固化狀態的絕緣層。然後，上晶片4A上的連接端子55及焊料層56穿透半固化狀態的絕緣層，並與連接端子110電性連接。此時，因為連接端子100的上表面(與連接端子55相對的表面)為曲面，故連接端子110與連接端子55之間的半固化狀態的絕緣層 令人滿意的被排出。因此，連接端子110與連接端子55之間並不包括半固化狀態的絕緣層。此改善連接端子110與連接端子55之間的連結可靠性。
第六實施例的修飾例
可修飾第六實施例中連接端子110周圍的結構。
例如，如圖37及39所示，絕緣層31可包括突出部31B。絕緣膜33的上表面及晶種層35的上表面可與突出部31B的上表面31C實質上齊平。可將從突出部31B的上表面31C向上突出的突出部32E配置於導電層32A上。此種結構可藉由進行圖36B所示步驟中使用CMP的精磨而形成。再者，此結構可包括具有下列結構的連接端子110。
例如，如圖37所示，連接端子110可形成於絕緣膜33及突出部31B上，連接端子100除了覆蓋晶種層35的上表面、絕緣膜33的上表面及突出部31B的上表面31C之外，還完全覆蓋突出部32E的表面。
例如，如圖38所示，可形成Ni層111，其具有從突出部31B的外側表面向側面突出的突出部111A，及可形成Au層112，其完全覆蓋Ni層111的表面，包括突出部111A的下表面。
例如，如圖39所示，可形成連接端子110，使其除了覆蓋絕緣膜33的上表面、晶種層35的上表面、及突出部31B的全部表面之外，還完全覆蓋突出部32E的表面。再者，可形成連接端子110，使其覆蓋形成於突出部31B周圍的絕緣層31的第一表面31A的一部分。
於圖37至39的第六實施例及修飾例中，導電層32A的突出部32E可具有實質的半球形的剖面(semispherical cross-section)。另一種情形， 如圖40所示，突出部32E可具有實質上梯形剖面。於此例中，與突出部32E類似，連接端子110具有實質上半球形的剖面。
可修飾圖40中連接端子110周圍的結構。
例如，如圖41至43所示，絕緣層31可包括突出部31B。絕緣膜33的上表面及晶種層35的上表面可與突出部31B的上表面31C實質上齊平，以及，導電層32A可包括具有實質上梯形剖面的突出部32E，其從突出部31B的上表面31C向上突出。再者，此結構可包括具有下列結構的連接端子110。
例如，如圖41所示，可於絕緣膜33及突出部31B上形成連接端子110，以除了覆蓋晶種層35的上表面、絕緣膜33的上表面、及突出部31B的上表面31C之外，還完全覆蓋具有實質的梯形剖面的突出部32E的表面。於此例中，類似突出部32E，連接端子110具有實質上梯形的剖面。
例如，如圖42所示，可形成Ni層111，使其包括從突出部31B的外表面側向突出的突出部111A。可形成Au層112，使其完全覆蓋Ni層111的表面，包括突出部111A的下表面。於此例中，類似突出部32E，連接端子110具有實質上梯形的剖面。
例如，如圖43所示，可形成連接端子110，使其除了覆蓋絕緣膜33的上表面、晶種層35的上表面、及突出部31B的全部表面之外，還完全覆蓋具有實質上梯形剖面的突出部32E的表面。再者，連接端子110可覆蓋形成於突出部31B周圍的絕緣層31的第一表面31A的一部分。於此例中，類似突出部32E，連接端子110具有實質上梯形的剖面。
如圖44所示，導電層32A的突出部32E可為拱形(arched)。即，於此例中的突出部32E係從導電層32A的外緣向導電層32A的中心向上隆起。於此例中，類似突出部32E，連接端子110亦在絕緣層31的第一表面31A及絕緣膜33的上表面拱起，以完全覆蓋突出部32E的表面。即，本實施例之連接端子110係從貫通電極32的外緣向貫通電極32的中心而向上隆起。
導電層32A的突出部32E可為實質的鐘形(bell-shaped)。即，於此例中，突出部32E在導電層32A的外緣溫和隆起，而在導電層32A的中心附近陡然隆起。再者，於此例中，類似於突出部32E，連接端子110為實質的鐘形。
可修飾圖44中的連接端子110周圍的結構。
例如，如圖45至47所示，絕緣層31可包括突出部31B。絕緣膜33的上表面及晶種層35的上表面可與突出部31B的上表面31C實質上齊平。可將從絕緣膜33、晶種層35、及突出部31B的上表面向上隆起的突出部32E配置於導電層32A上。再者，此種結構可包括具有下列結構的連接端子110。
例如，如圖45所示，可於絕緣膜33及突出部31B上形成連接端子110，其除了覆蓋晶種層35的上表面、絕緣膜33的上表面、及突出部31B的上表面之外，還完全覆蓋拱起的突出部32E的表面。於此例中，類似於突出部32E，連接端子110也拱起。
例如，如圖46所示，可形成Ni層111，其包括從突出部31B的外側表面側向突出的突出部111A，及可形成Au層112，其完全覆蓋Ni 層111的表面，包括突出部111A的下表面。於此例中，類似於突出部32E，連接端子110也拱起。
例如，如圖47所示，可形成連接端子110，使其完全覆蓋突出部32E的表面，以及覆蓋絕緣膜33的上表面、晶種層35的上表面、及突出部31B的全部表面。再者，可形成連接端子110，使其覆蓋形成於突出部31B周圍的絕緣層31的第一表面31A的一部分。於此例中，類似於突出部32E，連接端子110也拱起。
可將圖37至47所示的第六實施例及修飾例中的絕緣層31、貫通電極32、絕緣膜33、及連接端子100，應用於第一及第二實施例的半導體晶片3以及第二實施例中的半導體晶片6a及6b。當應用於半導體晶片3時，形成第六實施例及修飾例中的絕緣層31、貫通電極32、絕緣膜33、及連接端子110，取代圖1及13所示的絕緣層31、貫通電極32、絕緣膜33、及連接端子34。當應用於半導體晶片6a及6b時，形成第六實施例及修飾例中的絕緣層31、貫通電極32、絕緣膜33、及連接端子110，取代絕緣層81、貫通電極82、絕緣膜83、及連接端子84。
圖40至43所示修飾例的連接端子100的端面可為圓形。
其他實施例
各上述實施例可如下述修飾。
例如，可使用SiN、SiO2、或SiON之無機絕緣膜，或是複數個無機絕緣膜層合而得的層合膜(例如將SiN膜與SiO2膜以此順序層合而形成的SiN膜/SiO2膜)做為第一至第四實施例中的絕緣層31及81。
於此例中，如圖48所示，例如，於絕緣層31上形成從絕緣層 31的第一表面31A向上突出的突出部31B。形成貫通電極32及絕緣膜33，使其與突出部31B的上表面31C實質上齊平。於貫通電極32的上端面32B上形成連接端子34，貫通電極32係從絕緣層31的第一表面31A突出並從絕緣層31及絕緣膜33曝露出。此種絕緣層31可經由圖23A至23C所示的製程所製得。
圖48繪示絕緣層31的修飾例。絕緣層81亦可以相同方式變形。
各上述實施例及修飾例的連接端子34、84、及100及圖40至圖43所示的連接端子110，具有包括角落的四方形剖面。取而代之，例如，連接端子34及84及100及110可各具有圓形剖面。
例如，如圖49所示，連接端子100可具有實質上半橢圓形的剖面。於此例中，例如，Ni層101係形成以具有實質上半橢圓形的剖面，及Au層102係形成以完全覆蓋Ni層101的表面。雖然圖49是繪示圖20所示的連接端子100的修飾例，但是可以相同方式修飾圖22、及圖24至圖34所示的其他連接端子100，及，可以相同方式修飾連接端子34及84及110。
於各上述實施例中，疊合於佈線基材2上的半導體晶片的種類及數量並無限制。例如，疊合於佈線基材2上的半導體晶片，可全部供一記憶裝置使用。
於各上述實施例中，當將上方與下方的半導體晶片疊合時，絕緣層54A係形成於上晶片4的下側，及，上晶片4係疊合於下晶片3上。然後，將絕緣層54熱固化。因此，絕緣層54具有與底部填充材料相同的功效。
取而代之的是，例如，如圖50A所示，當上方的與下方的半導體晶片疊合時，可於下晶片3的上側形成絕緣層54A。此時，絕緣層54A係形成以完全覆蓋形成於貫通電極32的上端面32B上的連接端子34的表面。當絕緣層54A的材料是絕緣樹脂片材時，將絕緣樹脂片材層合於絕緣層31的上表面上。然而，於圖50A所示的步驟中，絕緣樹脂片材尚未固化，而處於B階段狀態。當絕緣層54A的材料為絕緣樹脂液或膏(例如NCP)時，是藉由例如印刷或旋塗將絕緣樹脂液或膏塗敷於絕緣層31的上表面。當需要時，可將塗敷的絕緣樹脂液或膏預烘至B階段狀態。
然後，於圖50B所示的步驟中，再將下晶片3與上晶片4對準後，將上晶片4的連接端子53覆晶接合至其上形成有連接端子34的貫通電極32。於絕緣層54A為半固化狀態時，將上晶片4的保護膜51的下表面黏著至下晶片3的絕緣層54A的上表面，以及，上晶片4的連接端子53穿透半固化狀態的絕緣層54A，而觸及下晶片3的連接端子34。因此，使連接端子34及53彼此電性連接。將半固化狀態的絕緣層54A於一固化溫度或更高的溫度下加熱一段預定時間，而熱固化。當絕緣層54A仍為液體時，可將上晶片4覆晶接合至下晶片3，而絕緣層54A則可在將連接端子34與53連接的相同時間下熱固化。此種絕緣層54A具有與底部填充材料相同的功效。
或者，在將上晶片4疊合於下晶片3上之後，可於下晶片3與上晶片4之間填充底部填充材料。
於第一至第三實施例中，當將絕緣層31、絕緣膜33、及導電層32A薄化以形成貫通電極32(參照圖7C)時，將絕緣層31、絕緣膜33、 及導電層32A碾磨(ground)。或者，可使用CMP裝置將絕緣層31、絕緣膜33、及導電層32A薄化以形成貫通電極32。
對於熟習此技藝之人士而言，顯然本發明可以許多其他特定形式實施，而不悖離本發明之精神或範圍。因此，本發明之實例及實施例應解讀為說明性質而非限制性質，並且，本發明不限於本文中所給的詳細說明，而可在所附的申請專利範圍的範疇內及均等之下修飾。

Claims (8)

  1. 一種半導體裝置，包含：一半導體基材，其包括一第一表面、一第二表面、及一貫通孔，該貫通孔由該第一表面通過該半導體基材而延伸至該第二表面；一第一絕緣層，其覆蓋該半導體基材的第二表面，其中，該第一絕緣層包括一開口，該開口與該貫通孔相通並具有與該貫通孔相同的直徑；一絕緣膜，其覆蓋該貫通孔的一壁面與該開口的一壁面；一貫通電極，其形成於被該絕緣膜覆蓋的該貫通孔與該開口中，其中該貫通電極包括一金屬阻障層、一金屬膜、及一導電層，該金屬阻障層覆蓋該貫通孔與該開口中的該絕緣膜，該金屬膜覆蓋該金屬阻障層，該導電層充填於該貫通孔與該開口中被該金屬膜包圍的一空間；一第一連接端子，其包括形成於該貫通電極的一端面上與該絕緣膜的一端面上的一無電電鍍金屬層，其中該第一連接端子具有比該貫通電極大的直徑；一佈線圖案與一第二絕緣層，二者層疊於該半導體基材的該第一表面上；以及一電極墊，其與該佈線圖案連接，其中該絕緣膜的該端面、該金屬阻障層的一端面、該金屬膜的一端面以及該導電層的一端面露出並齊平於該第一絕緣層的一表面，其中該第一連接端子形成為覆蓋該絕緣膜的該端面、該金屬阻障層的該端面、該金屬膜的該端面、該導電層的該端面以及該第一絕緣層的該表面的一部份，該第一絕緣層的該表面的該部份包圍該絕緣膜的該端面，以 及其中該第一連接端子具有半橢圓剖面，以及其中該貫通電極的一第二端面與該佈線圖案連接，該第二端面相對於該貫通電極的該第一端面。
  2. 如請求項1所述之半導體裝置，其中，該第一連接端子包括：鎳(Ni)層具有半橢圓形剖面以及覆蓋該絕緣膜的該端面、該金屬阻障層的該端面、該金屬膜的該端面、該導電層的該端面、及該絕緣膜的該端面的該部分，該部分包圍該第一絕緣層的該表面；以及其中該無電電鍍金屬層是：在該鎳層上依順序層合鈀(Pd)層和金(Au)層而形成的金屬層；或一金(Au)層；或一錫(Sn)層。
  3. 如請求項1或2所述之半導體裝置，其中該第一絕緣層的該表面包括一突出部，該第一連接端子形成於其上，以及該絕緣膜的該端面、該金屬阻擋層的該端面、該金屬膜的該端面、及該導電層的該端面露出並齊平於該第一突出部的一表面。
  4. 如請求項3所述之半導體裝置，其中該第一連接端子完全覆蓋該第一突出部及圍繞著該第一突出部的該第一絕緣層的該表面的一部分。
  5. 一種製造半導體裝置的方法，包含： 於一基底材的一主表面形成一凹槽；形成一絕緣膜，其覆蓋該凹槽的一壁面；形成一金屬阻障層，其完全覆蓋該凹槽的該壁面；形成一金屬膜，其覆蓋該金屬阻障層；形成一導電層於該凹槽中，該導電層填滿被該金屬膜圍出的空間；於該基底材的該主表面上層化一佈線圖案及一第二絕緣層，使該佈線圖案與該導電層連接；藉由將該基底材從該主表面的相對側薄化，以形成一半導體基材，使得該凹槽成為一貫通孔，且被絕緣膜覆蓋的該導電層、該金屬膜、與該金屬阻障層的部分由該基材突出；以一第一絕緣層覆蓋由該基材突出的該導電層、該金屬膜、與該金屬阻障層的部分；碾磨(grinding)或研磨(polishing)該第一絕緣層、該絕緣膜、該導電層、該金屬層、及該金屬阻障層以曝露出該絕緣膜的一端面、該導電層的一端面、該金屬膜的一端面、及該金屬阻障層的一端面，其中該碾磨或該研磨包括於該第一絕緣層中形成一開口，該開口與該貫通孔相通，並且具有與該貫通孔相同的直徑，及於該貫通孔與該開口中形成一貫通電極，該貫通電極包括該導電層、該金屬膜、及該金屬阻障層；於該絕緣膜上形成一第一連接端子，該第一連接端子包括一無電電鍍金屬層，該無電電鍍金屬層覆蓋從該第一絕緣層所曝露出的該貫通電極的一端面，並且該第一連接端子具有比該貫通電極大的直徑，其中在形成該貫通電極中，該絕緣膜的該端面、該導電層的該端面、 該金屬膜的該端面、及該金屬阻障層的該端面形成為齊平於該第一絕緣層的該表面，其中在形成該第一連接端子中，該第一連接端子形成為覆蓋該絕緣膜的該端面、該金屬阻障層的該端面、該金屬膜的該端面、該導電層的該端面以及該第一絕緣層的該表面的一部份，該第一絕緣層的該表面的該部份包圍該絕緣膜的該端面，以及其中該第一連接端子具有半橢圓剖面。
  6. 如請求項5所述之製造半導體裝置的方法，其中該形成該第一連接端子包括：透過無電電鍍形成一鎳層，該鎳層具有半橢圓形剖面並覆蓋該絕緣膜的該端面、該金屬阻障層的該端面、該金屬膜的該端面、該導電層的該端面、及該第一絕緣層的該表面的該部分，其包圍該絕緣膜的該端面；以及透過無電電鍍形成一無電電鍍金屬層覆蓋該鎳層，其中該無電電鍍金屬層是：在該鎳層上依順序層合鈀(Pd)層和金(Au)層而形成的金屬層；或一金(Au)層；或一錫(Sn)層。
  7. 如請求項5或6所述之製造半導體裝置的方法，其中該研磨包括調整研磨液材料以得一研磨墊硬度，以調整該第一絕緣層、該絕緣膜、該金屬阻障層、該金屬膜、及該導電層的磨除量。
  8. 如請求項5或6所述之製造半導體裝置的方法，進一步包括於與該佈線圖案連接的一電極墊上形成一第二連接端子；以及在一半固化狀態中將一第三絕緣層覆蓋該第二連接端子。
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