TWI688017B - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

Info

Publication number
TWI688017B
TWI688017B TW108108896A TW108108896A TWI688017B TW I688017 B TWI688017 B TW I688017B TW 108108896 A TW108108896 A TW 108108896A TW 108108896 A TW108108896 A TW 108108896A TW I688017 B TWI688017 B TW I688017B
Authority
TW
Taiwan
Prior art keywords
chip
circuit substrate
adhesive layer
thermosetting adhesive
stage thermosetting
Prior art date
Application number
TW108108896A
Other languages
English (en)
Other versions
TW202036734A (zh
Inventor
東鴻 黃
黃國樑
Original Assignee
南茂科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW108108896A priority Critical patent/TWI688017B/zh
Priority to CN201910501116.6A priority patent/CN111696874A/zh
Application granted granted Critical
Publication of TWI688017B publication Critical patent/TWI688017B/zh
Publication of TW202036734A publication Critical patent/TW202036734A/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

本發明提供一種晶片封裝結構的製作方法。提供線路基板與晶片。線路基板形成有兩階段熱固性膠層。晶片的主動表面形成有導電柱與支撐柱。使線路基板透過兩階段熱固性膠層抵接晶片的主動表面。使兩階段熱固性膠層落在該導電柱與該支撐柱之間。進行接合程序,晶片透過導電柱電性連接線路基板,並受支撐柱支撐定位於線路基板。使兩階段熱固性膠層完全固化。形成封裝膠體於線路基板上,以包覆晶片、導電柱、支撐柱以及兩階段熱固性膠層。另提供一種晶片封裝結構。

Description

晶片封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種晶片封裝結構及其製造方法。
一般而言,傳統晶片於接合至基板時,例如是覆晶接合(flip chip mounting),由於晶片的接合處常位於晶片中央,晶片的兩邊沒有支撐,而易於接合時因受力不均導致晶片傾斜,造成電性連接不良。此外,由於應力集中於接合處,因此容易於接合處產生斷裂,引發電性接合失敗的可能。上述問題都會使晶片封裝結構的可靠度變差,因此,如何提升晶片封裝結構的可靠度,將成為重要的一門課題。
本發明提供一種晶片封裝結構及其製造方法,可以降低晶片傾斜的現象,且減少接合處斷裂的可能,因此可以提升晶片封裝結構的可靠度。
本發明提供的一種晶片封裝結構的製作方法,包括以下步驟。提供線路基板與晶片,其中線路基板形成有兩階段熱固性膠層。且晶片的主動表面形成有導電柱與支撐柱。使線路基板透過兩階段熱固性膠層抵接晶片的主動表面,並使兩階段熱固性膠層落在該導電柱與該支撐柱之間。接著,進行接合程序,該晶片透過導電柱電性連接線路基板,並受支撐柱支撐定位於線路基板。形成封裝膠體於線路基板上,以包覆晶片、導電柱、支撐柱以及兩階段熱固性膠層。使兩階段熱固性膠層完全固化。
在本發明的一實施例中,上述的製作方法更包括在使線路基板透過兩階段熱固性膠層抵接晶片的主動表面之前,使兩階段熱固性膠層預固化。
在本發明的一實施例中,上述的製作方法更包括在形成封裝膠體於線路基板上之前,形成底膠層於線路基板與晶片的主動表面之間,以包覆導電柱、支撐柱與兩階段熱固性膠層。
在本發明的一實施例中,上述的兩階段熱固性膠層呈糊狀,在使線路基板透過兩階段熱固性膠層抵接晶片的主動表面的過程中,兩階段熱固性膠層受壓變形,以包覆導電柱與支撐柱。
本發明的晶片封裝結構包括線路基板、晶片、兩階段熱固性膠層以及封裝膠體。晶片具有主動表面,其中主動表面設有導電柱與支撐柱。晶片透過導電柱電性連接該線路基板,並受支撐柱支撐定位於線路基板。兩階段熱固性膠層設置於晶片的主動表面與線路基板之間。封裝膠體設置於線路基板上,以包覆晶片、導電柱、支撐柱以及兩階段熱固性膠層。
在本發明的一實施例中,上述的兩階段熱固性膠層連接線路基板與晶片,並落在導電柱與支撐柱之間。
在本發明的一實施例中,上述的兩階段熱固性膠層連接線路基板與晶片,並包覆導電柱與支撐柱。
在本發明的一實施例中,更包括底膠層。底膠層設置於線路基板與晶片的主動表面之間,以包覆導電柱、支撐柱以及兩階段熱固性膠層。
在本發明的一實施例中,上述的晶片具有中心區及邊緣區,中心區較邊緣區遠離晶片的側壁,且導電柱位於中心區,支撐柱位於邊緣區。
在本發明的一實施例中,上述的晶片封裝結構包括多個導電柱與多個支撐柱,且多個導電柱位於多個支撐柱之間。
基於上述,本發明的晶片除了具有用於電性連接的導電柱外,還具有用於支撐定位的支撐柱,因此晶片於接合時可以降低受力不均而導致晶片傾斜的現象。此外,由於應力可以較均勻的分散,因此可以減少因接合處斷裂引發電性接合失敗的可能,進而提升晶片封裝結構的可靠度。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A至圖1D是依照本發明一實施例的一種晶片封裝結構100的製造流程的剖面示意圖。請參考圖1A,首先,提供線路基板110與晶片120。詳細來說,線路基板具有多個接墊112與防焊層114。防焊層114覆蓋線路基板110中的導電線路(未繪示)並裸露出多個接墊112,以利於接墊112進行後續的電性連接。晶片120具有主動表面120a。晶片120例如是記憶體晶片、微處理器晶片或特殊應用積體電路晶片(ASIC),然而,本發明不限制晶片120的種類,可視實際設計需求而定。
請繼續參考圖1A,線路基板110形成有兩階段熱固性膠層130。兩階段熱固性膠層130例如是半硬化階段環氧樹脂(b-stage epoxy resin)。形成兩階段熱固性膠層130的方法可以包括旋轉塗佈製程或印刷製程。兩階段熱固性膠層例如是於A階時為液態(Liquid),於B階時為部分固化之半固態(Jelly),而於C階時則為完全固化之固態(Solid)的環氧樹脂(epoxy resin)。在本實施例中,如圖1A所示,兩階段熱固性膠層130可以是先以液態方式塗佈於基板上,再經過升溫加熱程序預固化兩階段熱固性膠層130。在此,使A階兩階段熱固性膠層部份固化成B階兩階段熱固性稱膠層為預固化程序。在一些實施例中,兩階段熱固性膠層130可以是被接墊112所圍繞。
另一方面,晶片120的主動表面120a形成有導電柱122與支撐柱124。詳細來說,導電柱122位於晶片120的中心區1201;而支撐柱124位於晶片120的邊緣區1202,其中中心區1201較邊緣區1202遠離晶片120的側壁120s。換句話說,相對於支撐柱124來說,導電柱122較遠離晶片120的側壁120s。在一些實施例中,導電柱122與支撐柱124可以是多個,且多個導電柱122位於多個支撐柱124之間。應說明的是,儘管圖1A中僅具有兩個導電柱122與兩個支撐柱124,然而,本發明不限制導電柱122與支撐柱124的數量,可依實際設計需求而定。
請參考圖1B,使線路基板110朝下相對晶片120接合,線路基板110透過兩階段熱固性膠層130抵接晶片120的主動表面120a,並使該兩階段熱固性膠層130落在導電柱122與支撐柱124之間。換句話說,兩階段熱固性膠層130設置於晶片120的主動表面120a與線路基板110之間,並連接線路基板110與晶片120。詳細來說,線路基板110、導電柱122、支撐柱124與晶片120包圍兩階段熱固性膠層130,而導電柱122與支撐柱124對應抵接於線路基板110的接墊112上。在本實施例中,由於預固化的兩階段熱固性膠層130還具有部分黏性,因此可以輔助線路基板110,使其於接合程序前暫時固定於晶片120的主動表面120a上。
接著,進行接合程序,晶片120透過導電柱122電性連接線路基板110,並受支撐柱124支撐定位於線路基板110。接合程序例如是覆晶接合程序。在一些實施例中,支撐柱124除了支撐功能外也可以具有導電功能,因此可以增加線路佈局上的彈性。支撐柱124與導電柱122所選用之材質可為銅、銀、金或其它導電的合金,於本實施例中,支撐柱124與導電柱122為銅柱,並在銅柱頂部設置有材質含鍚之銲帽(未標號),以與線路基板110上之接墊112接合;於本實施例中,支撐柱124與導電柱122頂部之銲帽形狀為半球狀,於其它實施例中,亦可利用電鍍方式形成為平頂之銲錫層;然而,本發明不限於此,支撐柱124也可以是不具有導電功能,端視晶片設計而定。在本實施例中,由於晶片120除了具有用於電性連接的導電柱122外,還具有用於支撐定位的支撐柱124,因此晶片120於接合時可以降低受力不均而導致晶片傾斜的現象。此外,由於應力可以較均勻的分散,進而減少因接合處斷裂引發電性接合失敗的可能,進而提升晶片封裝結構100的可靠度。
請參考圖1C,使兩階段熱固性膠層130完全固化。例如是使用加熱製程進行固化,而加熱製程例如是升溫烘烤。也就是說,可以是對半固化的兩階段熱固性膠層130進行加熱,使半固化的兩階段熱固性膠層130變為完全固化的兩階段熱固性膠層130a。接著,形成封裝膠體140於線路基板110上,以包覆晶片120、導電柱122、支撐柱124以及兩階段熱固性膠層130a。封裝膠體140的材料例如是環氧模壓樹脂(Epoxy Molding Compound, EMC)。在一些實施例中,可以選擇性地於固化步驟與形成封裝膠體140的步驟之間進行上下翻面的步驟,但本發明不限於此。於此,大致完成晶片封裝結構100。值得一提的是,兩階段熱固性膠層130完全固化程序亦可於封裝膠體140模封之後再進行升溫加熱。
請參考圖1D,在一些其他的實施例中,在形成封裝膠體140於線路基板110上之前,可以更包括形成底膠層150於線路基板110與晶片120的主動表面120a之間,以包覆導電柱122、支撐柱124與兩階段熱固性膠層130a。詳細來說,底膠層150填入線路基板110與晶片120的主動表面120a之間的間隙中。底膠層150的材料可與封裝膠體140不同或相同。
在此必須說明的是,以下實施例沿用上述實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明,關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。
圖2A至圖2D是依照本發明一實施例的一種晶片封裝結構200的製造流程的剖面示意圖。請同時參考圖2A至圖2D,圖2A至圖2D的實施例與圖1A至圖1D中的實施例差別在於:在使線路基板110透過兩階段熱固性膠層230抵接晶片120的主動表面120a之前,兩階段熱固性膠層230並未進行加熱預固化程序。
詳細來說,兩階段熱固性膠層230一開始時是呈糊狀(Jelly),在使線路基板110透過兩階段熱固性膠層230抵接晶片120的主動表面120a的過程中,兩階段熱固性膠層230因覆晶接合而受壓向外略呈變形,以包覆導電柱122與支撐柱124,如圖2B所示。接著,再使兩階段熱固性膠層230升溫加熱至完全固化,以形成兩階段熱固性膠層230a,如圖2C所示。在本實施例的晶片封裝結構200中,兩階段熱固性膠層230先包覆導電柱122與支撐柱124,再透過封裝膠體140包覆晶片120、導電柱122、支撐柱124以及兩階段熱固性膠層230,因此可以進一步提供緩衝及防潮防塵等效果,進而提升晶片封裝結構200的可靠度。此外,兩階段熱固性膠層230加熱完全固化程序亦可於封裝膠體140模封後進行,其加熱時機可於模封前亦可於模封後。
綜上所述,本發明的晶片除了具有用於電性連接的導電柱外,還具有用於支撐定位的支撐柱,因此晶片於接合時可以降低受力不均而導致晶片傾斜的現象。此外,由於應力可以較均勻的分散,因此可以減少因接合處斷裂引發電性接合失敗之可能。進而提升晶片封裝結構的可靠度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200:晶片封裝結構 110:線路基板 112:接墊 114:防焊層 120:晶片 1201:中心區 1202:邊緣區 120a:晶片的主動表面 120s:晶片的側壁 122:導電柱 124:支撐柱 130、130a、230、230a:兩階段熱固性膠層 140:封裝膠體 150:底膠層
圖1A至圖1D是依照本發明一實施例的一種晶片封裝結構的製造流程的剖面示意圖。 圖2A至圖2D是依照本發明一實施例的一種晶片封裝結構的製造流程的剖面示意圖。
100:晶片封裝結構
110:線路基板
112:接墊
114:防焊層
120:晶片
120a:晶片的主動表面
122:導電柱
124:支撐柱
130a:兩階段熱固性膠層
140:封裝膠體

Claims (10)

  1. 一種晶片封裝結構的製作方法,包括:提供線路基板與晶片,其中該線路基板形成有兩階段熱固性膠層,且該晶片的主動表面形成有導電柱與支撐柱;使該線路基板透過該兩階段熱固性膠層抵接該晶片的該主動表面,並使該兩階段熱固性膠層落在該導電柱與該支撐柱之間,接著,進行接合程序,該晶片透過該導電柱電性連接該線路基板,並受該支撐柱支撐定位於該線路基板,其中該支撐柱與該晶片無電性連接;形成封裝膠體於該線路基板上,以包覆該晶片、該導電柱、該支撐柱以及該兩階段熱固性膠層;以及加熱使該兩階段熱固性膠層完全固化。
  2. 如申請專利範圍第1項所述的晶片封裝結構的製作方法,更包括:在使該線路基板透過該兩階段熱固性膠層抵接該晶片的該主動表面之前,使該兩階段熱固性膠層預固化。
  3. 如申請專利範圍第1項所述的晶片封裝結構的製作方法,更包括:在形成該封裝膠體於該線路基板上之前,形成底膠層於該線路基板與該晶片的該主動表面之間,以包覆該導電柱、該支撐柱與該兩階段熱固性膠層。
  4. 如申請專利範圍第1項所述的晶片封裝結構的製作方法,其中該兩階段熱固性膠層呈糊狀,在使該線路基板透過該兩階段熱固性膠層抵接該晶片的該主動表面的過程中,該兩階段熱固性膠層受壓變形,以包覆該導電柱與該支撐柱。
  5. 一種晶片封裝結構,包括:線路基板;晶片,具有主動表面,其中該主動表面設有導電柱與支撐柱,該晶片透過該導電柱電性連接該線路基板,並受該支撐柱支撐定位於該線路基板,其中該支撐柱與該晶片無電性連接;兩階段熱固性膠層,設置於該晶片的該主動表面與該線路基板之間;以及封裝膠體,設置於該線路基板上,以包覆該晶片、該導電柱、該支撐柱以及該兩階段熱固性膠層。
  6. 如申請專利範圍第5項所述的晶片封裝結構,其中該兩階段熱固性膠層連接該線路基板與該晶片,並落在該導電柱與該支撐柱之間。
  7. 如申請專利範圍第5項所述的晶片封裝結構,其中該兩階段熱固性膠層連接該線路基板與該晶片,並包覆該導電柱與該支撐柱。
  8. 如申請專利範圍第5項所述的晶片封裝結構,更包括底膠層,設置於該線路基板與該晶片的該主動表面之間,以包覆該導電柱、該支撐柱以及該兩階段熱固性膠層。
  9. 如申請專利範圍第5項所述的晶片封裝結構,其中該晶片具有中心區及邊緣區,該中心區較該邊緣區遠離該晶片的側壁,且該導電柱位於該中心區,該支撐柱位於該邊緣區。
  10. 如申請專利範圍第5項所述的晶片封裝結構,其中該晶片封裝結構包括多個該導電柱與多個該支撐柱,且該些導電柱位於該些支撐柱之間。
TW108108896A 2019-03-15 2019-03-15 晶片封裝結構及其製造方法 TWI688017B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW108108896A TWI688017B (zh) 2019-03-15 2019-03-15 晶片封裝結構及其製造方法
CN201910501116.6A CN111696874A (zh) 2019-03-15 2019-06-11 芯片封装结构及其制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108108896A TWI688017B (zh) 2019-03-15 2019-03-15 晶片封裝結構及其製造方法

Publications (2)

Publication Number Publication Date
TWI688017B true TWI688017B (zh) 2020-03-11
TW202036734A TW202036734A (zh) 2020-10-01

Family

ID=70766960

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108108896A TWI688017B (zh) 2019-03-15 2019-03-15 晶片封裝結構及其製造方法

Country Status (2)

Country Link
CN (1) CN111696874A (zh)
TW (1) TWI688017B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113496962A (zh) * 2020-03-20 2021-10-12 南茂科技股份有限公司 芯片封装结构及其制造方法
TWI779560B (zh) * 2020-05-05 2022-10-01 南亞科技股份有限公司 具有多個電壓供應源的半導體封裝結構及其製備方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201029136A (en) * 2008-11-25 2010-08-01 Sumitomo Bakelite Co Electronic component package and method for producing the same
TW201138037A (en) * 2010-04-20 2011-11-01 Walton Advanced Eng Inc Flip-chip bonding method and structure for non-array bumps
TW201438245A (zh) * 2013-02-27 2014-10-01 Shinko Electric Ind Co 半導體裝置及其製造方法
TW201909343A (zh) * 2017-07-13 2019-03-01 力成科技股份有限公司 封裝結構及其製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100576889B1 (ko) * 2000-12-29 2006-05-03 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
CN101552215A (zh) * 2008-04-01 2009-10-07 南茂科技股份有限公司 覆晶封装结构及其封装制程
CN101552245B (zh) * 2008-04-03 2010-12-01 南茂科技股份有限公司 覆晶封装制程
CN102194707B (zh) * 2010-03-01 2013-03-27 南茂科技股份有限公司 制造半导体结构的方法
TWI560834B (en) * 2015-05-29 2016-12-01 Chipmos Technologies Inc Flip chip package and chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201029136A (en) * 2008-11-25 2010-08-01 Sumitomo Bakelite Co Electronic component package and method for producing the same
TW201138037A (en) * 2010-04-20 2011-11-01 Walton Advanced Eng Inc Flip-chip bonding method and structure for non-array bumps
TW201438245A (zh) * 2013-02-27 2014-10-01 Shinko Electric Ind Co 半導體裝置及其製造方法
TW201909343A (zh) * 2017-07-13 2019-03-01 力成科技股份有限公司 封裝結構及其製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113496962A (zh) * 2020-03-20 2021-10-12 南茂科技股份有限公司 芯片封装结构及其制造方法
TWI779560B (zh) * 2020-05-05 2022-10-01 南亞科技股份有限公司 具有多個電壓供應源的半導體封裝結構及其製備方法
US11764191B2 (en) 2020-05-05 2023-09-19 Nanya Technology Corporation Method for preparing semiconductor package having multiple voltage supply sources

Also Published As

Publication number Publication date
TW202036734A (zh) 2020-10-01
CN111696874A (zh) 2020-09-22

Similar Documents

Publication Publication Date Title
US6841854B2 (en) Semiconductor device
TWI538071B (zh) 具連接結構之積體電路封裝系統及其製造方法
US6555917B1 (en) Semiconductor package having stacked semiconductor chips and method of making the same
TWI495021B (zh) 半導體封裝結構的製造方法
US20030001252A1 (en) Semiconductor package including stacked chips
JP2972096B2 (ja) 樹脂封止型半導体装置
US20130280865A1 (en) QFN Package and Manufacturing Process Thereof
US11031356B2 (en) Semiconductor package structure for improving die warpage and manufacturing method thereof
US9907186B1 (en) Electronic package structure and method for fabricating the same
TWI455269B (zh) 晶片封裝結構及其製作方法
TWI688017B (zh) 晶片封裝結構及其製造方法
TW201901908A (zh) 電子封裝件及其製法
US10811378B2 (en) Electronic package and manufacturing method thereof
US20060068332A1 (en) Method for fabricating carrier structure integrated with semiconductor element
US20010023994A1 (en) Semiconductor device and the method for manufacturing the same
KR101474189B1 (ko) 집적회로 패키지
US20080224284A1 (en) Chip package structure
CN113745199A (zh) 电子封装件
US20140099755A1 (en) Fabrication method of stacked package structure
TWI718801B (zh) 電子封裝件之製法
US7492037B2 (en) Package structure and lead frame using the same
TWI389296B (zh) 可堆疊式封裝結構及其製造方法及半導體封裝結構
JP3147106B2 (ja) 半導体装置
TWI750082B (zh) 半導體覆晶封裝結構及方法
KR20140045248A (ko) 집적회로 패키지 제조방법