TWI544517B - 半導體裝置的製作方法 - Google Patents
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- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
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- 238000006243 chemical reaction Methods 0.000 description 4
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- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
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- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 239000003795 chemical substances by application Substances 0.000 description 1
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- 239000005350 fused silica glass Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
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- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
Description
本發明係關於圖案化半導體裝置的方法,更特別關於採用三層光阻的改良圖案化技術。
半導體積體電路(IC)產業快速成長。由於IC材料與設計的技術進步,新一代的IC具有較小與較複雜的電路。製程尺寸縮小往往有利於增加製程效率並降低相關成本,但亦增加製程複雜度。然而製程尺寸縮小的優點顯而易見,因此需要更小的IC製程。在IC進化時,通常增加其功能密度(比如固定晶片面積中的內連線元件數目),與縮小其尺寸(比如製程形成的最小構件或連線)。
縮小尺寸亦會造成多種製程難題。舉例來說,三層光阻通常用於圖案化半導體製程中的層狀物。然而在裝置尺寸越來越小的情況下,三層光阻可能導致線路破損及/或光阻殘渣等問題,並劣化半導體裝置效能甚至導致裝置失效。
綜上所述,現有圖案化半導體裝置的方法通常只適用於其特定目的,而非適用於所有領域。
本發明一實施例提供之半導體裝置的製作方法,包括:形成材料層於基板上;形成三層光阻於材料層上,三層光阻包括底層、中間層位於底層上、以及光敏層位於中間層
上;進行光微影製程圖案化光敏層,以形成具有一或多個開口的遮罩;以第一蝕刻製程移除遮罩不需要的部份;以及之後以第二蝕刻製程圖案化中間層,其中第二蝕刻製程包括在蝕刻中間層時,形成塗層於遮罩周圍。
本發明一實施例提供之半導體裝置的製作方法,包括:形成材料層於基板上;形成三層光阻於材料層上,三層光阻包括第一層、第二層位於第一層上、以及第三層位於第二層上,其中第三層包括光敏材料;以光微影製程形成圖案化之第三層,且圖案化之第三層包括一或多個開口露出其下方的第二層;以第一蝕刻製程去除圖案化之第三層的殘渣;在去除殘渣之步驟後,以第二蝕刻製程形成圖案化之第二層,其中第二蝕刻製程包括在蝕刻第二層時,連續塗佈高分子層於圖案化之第三層周圍;以第三蝕刻製程形成圖案化之第一層,其中第三蝕刻製程一起移除圖案化之第二層與塗佈其上的高分子層;以及搭配圖案化之第一層,以圖案化材料層。
本發明一實施例提供之半導體裝置的製作方法,包括:形成材料層於基板上;形成三層光阻於材料層上,三層光阻包括底層、中間層位於底層上、以及光敏頂層位於中間層上,其中底層包括第一CxHyOz材料,中間層包括一SiCxHyOz材料,且光敏頂層包括第二CxHyOz材料與光敏單元;進行光微影製程以圖案化光敏頂層成遮罩,且遮罩具有一或多個開口,其中遮罩具有殘渣橫向延伸出遮罩外;進行第一蝕刻製程以去除遮罩的殘渣,其中第一蝕刻製程採用氬氣與四氟化碳氣體;接著以第二蝕刻製程圖案化中間層,其中第二蝕刻製程包括在蝕
刻中間層時,連續沉積高分子塗層於去除殘渣後的遮罩周圍,且其中第二蝕刻製程至少採用CxHyFz氣體與氫氣;以第三蝕刻製程圖案化底層,其中第三蝕刻製程一起移除遮罩與高分子塗層;以及搭配圖案化之底層,以圖案化材料層。
11‧‧‧方法
13、15、17、19、21、23、25‧‧‧步驟
30‧‧‧半導體裝置
35‧‧‧基板
40‧‧‧矽化物阻擋層
45‧‧‧四乙氧矽烷層
50‧‧‧低介電常數介電層
55‧‧‧抗反射塗層
60‧‧‧氮化鈦層
65‧‧‧四乙氧矽烷層
70‧‧‧非晶矽層
70A、70B、91A、91B、92A、92B、93A、93B‧‧‧部件
90‧‧‧三層光阻
91‧‧‧底層
92‧‧‧中間層
93‧‧‧頂層
100‧‧‧光微影製程
110‧‧‧開口
120、150、185‧‧‧高度
130‧‧‧光阻殘渣
140‧‧‧去渣製程
160、190‧‧‧蝕刻製程
180‧‧‧塗層
220、221、222‧‧‧狀態
第1圖係本發明實施例中,圖案化半導體裝置的方法之流程圖。
第2A至7A圖係本發明實施例中,不同製程階段中的部份半導體裝置之上視圖。
第2B至7B圖係本發明實施例中,對應第2A至7A圖內不同製程階段中的部份半導體裝置之剖視圖。
第8圖係本發明實施例中,用以圖案化半導體裝置之蝕刻製程中,不同氫氣流速之三種不同狀態的圖表。
可以理解的是,下述內容提供許多不同的實施例或實例以實施多種實施例中不同的特徵。下述構件與排列的特定實例係用以簡化本發明,而非用以侷限本發明。舉例來說,下述說明中形成第一結構於第二結構上可包括兩者直接接觸的實施例,且亦可包括額外結構形成於兩者之間的實施例(即第一結構與第二結構未直接接觸)。此外,本發明在多種實例中可採用重複標號及/或符號。這些重複僅用以簡化並清楚說明,並非限定不同實施例及/或組態之間具有相同標號的元件之間具有相同的對應關係。
第1圖係採用三層光阻圖案化半導體裝置之方法11的流程圖。方法11包含之步驟13形成材料層於基板上。方法11包含之步驟15形成三層光阻於材料層上。三層光阻包含底層、位於底層上的中間層、與位於中間層上的光敏頂層。底層包含第一CxHyOz材料,中間層包含SiCxHyOz材料,而光敏頂層包括第二CxHyOz材料與光敏單元。方法11包含之步驟17進行微影製程,使光敏頂層圖案化成具有一或多個開口的遮罩。遮罩包含的殘渣自遮罩向外水平延伸。方法11包含之步驟19進行第一蝕刻製程,以去除遮罩的殘渣。第一蝕刻製程採用氬氣與四氟化碳氣體。方法11包含之步驟21進行第二蝕刻製程以圖案化中間層。第二蝕刻製程包括在蝕刻中間層時,持續沉積高分子塗層於去除殘渣的遮罩周圍。第二蝕刻製程採用至少一CxHyFz氣體與氫氣。在某些實施例中,第二蝕刻製程的氫氣流速介於約50標準立方公分/分鐘(sccm)至約250sccm之間。在某些實施例中,第二蝕刻製程包括誘導耦合電漿(ICP)製程,其偏壓介於約120伏特至約240伏特之間。方法11包含之步驟23進行第三蝕刻製程圖案化底層。第三蝕刻製程移除遮罩與高分子塗層。方法11之步驟25採用圖案化之底層,以圖案化材料層。
第2A至7A圖係一實施例中,第1圖之方法11中不同圖案化階段之部份半導體裝置30的上視圖。第2A至7A圖為二維圖,分別沿著X軸與Y軸延伸,且Y軸垂直於X軸。第2B至7B圖係部份半導體裝置30沿著Y軸的剖視圖。換言之,剖視圖係沿著X軸的方向剖面。後述的多種形成與蝕刻步驟沿著Z軸進行於半導體裝置30上,且Z軸垂直於X軸及Y軸組成的想像平面。
半導體裝置30可為部份的積體電路(IC)晶片,且可包含多種被動與主動微電子裝置如電阻、電容、電感、二極體、金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極接面電晶體(BJT)、橫向擴散MOS(LDMOS)電晶體、高功率MOS電晶體、或其他種類的電晶體。可以理解的是,第2A至7A圖與第2B至7B圖已簡化,以利了解本發明概念。綜上所述,應注意在第1圖之方法11之前、之中、或之後可進行額外製程,且某些其他製程僅簡述於此。
如第2A與2B圖所示,半導體裝置30包含基板35。基板35可為半導體晶圓,或底層如金屬層(Mx至Mx+1)。舉例來說,基板35可包含矽。基板35亦可為某些其他合適的半導體元素如鑽石或鍺;合適的半導體化合物如碳化矽、砷化銦、或磷化銦;或合適的半導體合金如碳化矽鍺、磷化鎵砷、或磷化鎵銦。在另一實施例中,基板35可包含非半導體材料如玻璃基板以用於薄膜電晶體液晶顯示器(TFT-LCD)裝置,或熔融石英或氟化鈣以用於光罩。基板35可包含多種掺雜區及/或介電結構以用於多種微電子構件,比如互補式金氧半場效電晶體(CMOSFET)、影像感測器、記憶單元、及/或電容單元。
矽化物阻擋層(SBL)40係形成於基板35上。矽化物阻擋層40亦可稱作矽化阻擋層。在某些實施例中,矽化物阻擋層40之形成方法為合適製程如物理氣相沉積(PVD)、化學氣相沉積(CVD)、原子層沉積(ALD)、或上述之組合。此實施例之矽化物阻擋層40包含介電材料如氧化矽或氮化矽,但其他實施例之矽化物阻擋層40可包含其他合適材料。可以理解的是某些
實施例中,矽化物阻擋層40可不直接形成於基板35的上表面上,即其他合適層狀物可形成於基板35與矽化物阻擋層40之間。
四乙氧矽烷(TEOS)層45係形成於矽化物阻擋層40上。在某些實施例中,四乙氧矽烷層45之形成製程為PVD、CVD、電漿增強式化學氣相沉積(PECVD)、上述之組合、或其他合適技術。
低介電常數介電層50係形成於四乙氧矽烷層45上。在某些實施例中,低介電常數介電層50之形成製程為PVD、CVD、PECVD、ALD、上述之組合、或其他合適技術。低介電常數介電層50包含低介電常數材料,其介電常數小於標準二氧化矽的介電常數(約3.9)。在多種實施例中,低介電常數介電材料可包含但不限於掺雜氟的二氧化矽、掺雜碳的二氧化矽、孔洞二氧化矽、旋轉塗佈的有機高分子介電物、旋轉塗佈的矽酮為主之高分子介電物、聚亞醯胺、芳香高分子、掺雜氟之非晶碳、氣相沉積之聚對二甲苯、或類似物。
抗反射塗層55係形成於低介電常數介電層50上。在某些實施例中,抗反射塗層55係無氮的抗反射塗層(NFARC)。抗反射塗層55之形成方法可為本技術領域已知的合適沉積技術。
接著形成氮化鈦層60於抗反射塗層55上。在此實施例中,氮化鈦層60之形成方法為射頻物理氣相沉積製程。在另一實施例中,氮化鈦層之形成方法可為其他製程。
接著形成四乙氧矽烷(TEOS)層65於氮化鈦層60
上。在某些實施例中,四乙氧矽烷層65之形成方法為PVDVD電漿增強化學氣相沉積(PECVD)、上述之組合、或另一合適技術。
非晶矽層70係形成於四乙氧矽烷層65上。非晶矽層70的形成製程為PVD、CVD、濺鍍、或另一合適技術。非晶矽層70在這可作為下述光阻層欲圖案化之遮罩層。在其他實施例中,另一合適材料之遮罩層可取代非晶矽層。
可以理解的是,上述標號40至70的層狀物僅用以舉例,說明光阻層可圖案化之層狀物。在其他實施例中,層狀物40至70之子集或不同層狀物可形成於基板35上,且可由下述光阻層圖案化。
三層光阻90係形成於多晶矽層70上。在此實施例中,三層光阻90包含底層91、中間層92、與頂層93。在某些實施例中,底層91包括CxHyOz材料,中間層92包括SiCxHyOz材料,且頂層93包括CxHyOz材料。在某些實施例中,底層91之CxHyOz材料與頂層93之CxHyOz材料相同,但其他實施例中上述兩者可不同。頂層93亦包含光敏單元如光酸起始劑(PAG)。上述組成讓光微影製程得以圖案化頂層93。可以理解的是在其他實施例中,可省略三層光阻中的一或多層或額外新增其他層狀物作為光阻的一部份,且光阻的層狀物可採用不同順序形成。
一般而言,用以圖案化頂層之光微影製程可包含一或多道微影製程、顯影、潤濕、與烘烤製程,且上述步驟不限於上述順序。光微影製程圖案化頂層以形成光阻遮罩,其具有一或多個開口以露出其下方的中間層92。接著搭配光阻遮罩
蝕刻中間層92以形成圖案化之中間層,再搭配圖案化之中間層蝕刻底層91以形成圖案化之底層。接著搭配圖案化之底層圖案化其下之多個層狀物。不幸的是,習知技術在進行上述圖案化與蝕刻製程時,容易造成線路破損及/或光阻殘渣等問題,造成半導體裝置效能劣化或失效。
依據本發明的多種實施例,改良的微影/圖案化技術可實質上降低或減少習知技術造成的線路破損及/或光阻殘渣等問題。本發明細節將詳述於下。
如第3A至3B圖所示,對頂層93進行光微影製程100以形成圖案化之光阻遮罩。圖案化之光阻遮罩包括部件93A與93B,兩者之間隔有開口110。在某些實施例中,開口的寬度(如水平尺寸)介於約20nm至約100nm之間。部件93A與93B具有高度(如垂直尺寸)120。在某些實施例中,高度120介於約400Å至700Å之間。
光微影製程100的多種缺陷會形成不需要的光阻殘渣。舉例來說,接近部件93A底部之橫向突起部份為光阻殘渣130。如圖所示,光阻殘渣130會大幅縮短相鄰之部件93A與93B之間的開口110,並增加部件93A的尺寸。如此一來,光阻殘渣130的存在會導致後續圖案化製程不準確或其他問題。綜上所述,需移除光阻殘渣以解決上述問題。
如第4A與4B圖所示,以去渣製程140移除光阻殘渣130。在某些實施例中,去渣製程包含蝕刻製程。在本發明多種實施例中,在蝕刻腔室中採用連續電漿製程以進行蝕刻製程,比如誘導耦合電漿(ICP)製程。在此實施例中,去渣製程
140的蝕刻氣體包括氬氣與四氟化碳。氬氣與四氟化碳各自的流速可介於約30sccm至約50sccm之間,比如約40sccm。在某些實施例中,氬氣與四氟化碳的流速比為約1:1。蝕刻製程的氣體壓力可介於約1毫托(mT)至約3mT之間,比如約2mT。用於ICP製程的電源功率可介於約200瓦至約250瓦之間,比如約220瓦。用於ICP製程的偏壓可介於約80伏特至約150伏特之間,比如約110伏特。
經上述去渣製程140後,部件93A與93B降低至高度150,其小於去渣製程140前之高度120(見第3圖)。在某些實施例中,高度150介於約300Å至約500Å之間。接著可將圖案化之頂層的部件93A與93B用於圖案化中間層92。
接著如第5A與5B圖所示,進行蝕刻製程160使中間層92具有開口。換言之,圖案化中間層92以形成部件92A與92B。在蝕刻製程160中,部件93A與93B作為光阻遮罩。蝕刻製程160與前述去渣製程140可在相同蝕刻腔室中進行。換言之,蝕刻製程160亦關於連續電漿製程(非脈衝製程),比如ICP製程。在此實施例中,蝕刻製程160之蝕刻氣體包含四氟化碳、氟仿、氫氣、氮氣、與氬氣。在此實施例中,氟仿作為主要氣體,而氮氣與氬氣作為輔助氣體。四氟化碳氣體之流速可介於約50sccm至約70sccm之間,比如約60sccm。氟仿氣體之流速可介於約45sccm至約65sccm之間,比如約55sccm。氫氣之流速可介於約50sccm至約250sccm之間,比如約150sccm。氮氣之流速可介於約50sccm至約80sccm之間,比如約65sccm。氬氣之流速可介於約40sccm至約60sccm之間,比如約50sccm。
可以理解的是,氫氣流速的最佳化範圍介於約50sccm至約250sccm之間,過慢的流速會導致不完整或無效的蝕刻,而過快的流速會導致光阻損失過多(比如損失部件93A與93B)。上述現象將搭配第8圖詳述於後。應理解的是其他實施例中,可採用其他合適氣體CxHyFz(x>0,y0,且z>0)取代此實施例之氟仿作為主要氣體。
蝕刻製程之製程壓力可介於約5mT至約20mT之間,比如約12mT。ICP製程之電源功率可介於約500瓦至約700瓦之間,比如約600瓦。ICP製程的偏壓可介於約120V至約240V之間,比如約200V。需理解的是,偏壓介於120V至約240V之間為最佳化偏壓,低於120V的偏壓會導致不完全或無效的蝕刻,而高於約240V的偏壓會導致光阻損失過多(比如損失部件93A與93B)。需理解的是,蝕刻製程160較佳採用連續電漿製程,因脈衝型態的蝕刻製程(不連續但常用於許多蝕刻製程中)可能導致不完全或無效的蝕刻。
蝕刻製程160的結果為中間層92圖案化為部件92A與92B。由於部件93A與93B作為蝕刻製程160的遮罩,部件92A與92B分別對準部件93A與93B。此外,塗層180係形成於部件93A、93B、92A、與92B之上表面與側壁表面上。在某些實施例中,塗層180包含高分子材料。塗層180的形成方法至少部份屬於添加氫氣。藉由多種化學反應,可在蝕刻持續進行時連續地沉積塗層180於部件93A、93B、92A、與92B上。換言之,蝕刻中間層92與形成塗層180的步驟實質上同時連續進行。蝕刻製程160的結果為部件93A及塗層180之合計高度185介於約
410Å至約610Å之間。
如前所述,以習知製程蝕刻三層光阻之中間層時,除了其他物質外可能不包含氫氣作為蝕刻劑。如此一來,用以蝕刻中間層的習知製程不會沉積連續性的塗層(或與塗層180類似的層狀物)於光阻遮罩(比如與部件93A與93B相同之部份頂層)上。換言之,習知蝕刻技術不會形成任何保護塗層於光阻遮罩上。缺乏保護層的光阻遮罩通常導致過度蝕刻光阻遮罩,即光阻遮罩損失的高度會超出預期。在某些情況下,部份光阻遮罩可能會被完全移除。在上述狀況中,過度蝕刻的光阻遮罩無法適當地搭配蝕刻中間層的製程,可能造成線路破損的問題。舉例來說,不充足的光阻遮罩會導致蝕刻不應被蝕刻的中間層部件,結果為劣化半導體裝置效能,且裝置失效的狀況增加。
與習知技術相較,本發明實施例可連續沉積塗層180於頂層93之部件93A與93B(比如光阻遮罩)周圍。在蝕刻中間層92時,塗層180可保護部件93A與93B免於過度蝕刻。如此一來,本發明實施例之蝕刻製程160不會導致習知蝕刻製程中常見的線路破損問題。
接著如第6A與6B圖所示,進行另一蝕刻製程190以形成開口於底層91中。換言之,底層91被圖案化成部件91A與91B。在此蝕刻製程190中,圖案化之中間層的部件92A與92B可作為遮罩。進行蝕刻製程190之蝕刻腔室,可與前述進行去渣製程140及蝕刻製程160之蝕刻腔室相同或不同。塗層180可藉由蝕刻製程190移除,亦可在進行蝕刻製程190前即移除。
在此實施例中,蝕刻製程190的蝕刻氣體包含溴化氫、氯氣、氧氣、與氮氣。溴化氫氣體之流速可介於約40sccm至約60sccm之間,比如50sccm。氯氣之流速可介於約5sccm至約40sccm之間,比如約20sccm。氧氣之流速可介於約40sccm至約150sccm之間,比如約90sccm。氮氣之流速可介於約30sccm至約80sccm之間,比如約50sccm。
如第7A至7B圖所示,進行另一蝕刻製程200以圖案化非晶矽層70。換言之,非晶矽層70被圖案化成部件70A與70B。在蝕刻製程200中,圖案化之底層的部件91A與91B作為遮罩。進行蝕刻製程200之蝕刻腔室,可與前述進行去渣製程140、蝕刻製程160、與蝕刻製程190之蝕刻腔室相同或不同。部件92A與92B可藉由蝕刻製程200移除,亦可在進行蝕刻製程200前即移除。
雖然為了簡化說明而未特別圖示或說明,但可採用多種蝕刻製程圖案化多種層狀物40至65的一或多者。上述蝕刻製程的結果,可為形成多種半導體結構如溝槽或島狀物。同樣的,由於中間層的蝕刻製程可持續形成塗層180與池續蝕刻中間層92,之後圖案化的多種半導體結構較不會因習知製程常見之光阻殘渣或破損線路問題,而具有不精準或不適當的圖案。
第8圖係第5B圖中的蝕刻製程160中,對應不同流速之氫氣的三種不同狀態220、221、與222之圖表。在第8圖中,多種蝕刻製程的參數標示於Y軸,而氫氣流速標示於X軸。舉例來說,AMI CD指的是後遮罩偵測的關鍵尺寸,LWR指的是
線寬粗糙度,ML EP指的是中間層終點(中間層92所需的蝕刻時間),BL EP指的是底層終點(底層91所需的蝕刻時間),PREP指的是光阻蝕刻終點(完全移除頂層93所需的蝕刻時間)。在蝕刻製程160時,會發生三種機制:
機制A為氟蝕刻,其包含下述化學反應:e-+CF4 -=>CF3+F+e-,以及Si+4F=>SiF4。
機制B為減少形成氟與形成高分子,其包含下述化學反應:H+F=>HF,以及CF4+H2=>CxHyFz。
機制C為形成氟,其包含下述化學反應:HF+e-=>H+F+e-,以及H+HF*=>H2+F。
在狀態1中,機制B主導。如此一來,AMICD降低,LWR維持於相對定值,ML EP增加,而BL EP亦增加。在狀態2中,機制A、B、與C相對平衡。換言之,沒有一種機制主導狀態2。如此一來,AMI CD為目標值,LWR降低、ML EP降低會維持於相對定值,BL EP亦降低。在狀態3中,機制C主導。如此一來,AMI CD增加,LWR增加,ML EP維持於相對定值,且BL EP降低。
對應上述的三種狀態220、221、與222的現象亦圖示於第8圖中。如圖所示,狀態2可達最佳化的平衡效能,其中氫氣流速的範圍近似於約50sccm至約250sccm之間。換言之,狀態2可連續蝕刻中間層,與連續沉積保護塗層於光阻遮罩上,且上述兩步驟達到平衡。上述狀態不會過度蝕刻光阻遮罩,也不需蝕刻過長時間。因此,狀態2之氫氣流速為最佳化範圍,並可實施於本發明之蝕刻製程160中。
本發明一實施例關於半導體裝置的製作方法,包括:形成材料層於基板上;形成三層光阻於材料層上,三層光阻包括底層、中間層位於底層上、以及光敏層位於中間層上;進行光微影製程圖案化光敏層,以形成具有一或多個開口的遮罩;以第一蝕刻製程移除遮罩不需要的部份;以及之後以第二蝕刻製程圖案化中間層,其中第二蝕刻製程包括在蝕刻中間層時,形成塗層於遮罩周圍。
在某些實施例中,上述方法更包括以第三蝕刻製程圖案化底層,其中第三蝕刻製程一起移除遮罩與塗層;以及搭配圖案化之底層,以圖案化材料層。
在某些實施例中,遮罩不需要的部份包括遮罩向外凸出的光阻殘渣。
在某些實施例中,第一蝕刻製程採用氬氣與四氟化碳,且第一蝕刻製程的壓力為約2毫托。
在某些實施例中,第二蝕刻製程包括電漿蝕刻製程,且電漿蝕刻製程至少採用CxHyFz氣體與氫氣。
在某些實施例中,氫氣係用以在蝕刻中間層時,誘導沉積高分子材料之塗層於遮罩周圍。
在某些實施例中,氫氣流速介於約50sccm至約250sccm之間。
在某些實施例中,電漿蝕刻製程包括連續電漿製程。
在某些實施例中,電漿蝕刻製程之操作偏壓介於約120伏特至約240伏特之間。
在某些實施例中,底層包括第一CxHyOz材料,中間層包括SiCxHyOz材料,且光敏層包括第二CxHyOz材料與光酸起始劑。
本發明另一實施例關於半導體裝置的製作方法,包括:形成材料層於基板上;形成三層光阻於材料層上,三層光阻包括第一層、第二層位於第一層上、以及第三層位於第二層上,其中第三層包括光敏材料;以光微影製程形成圖案化之第三層,且圖案化之第三層包括一或多個開口露出其下方的第二層;以第一蝕刻製程去除圖案化之第三層的殘渣;在去除殘渣之步驟後,以第二蝕刻製程形成圖案化之第二層,其中第二蝕刻製程包括在蝕刻第二層時,連續塗佈高分子層於圖案化之第三層周圍;以第三蝕刻製程形成圖案化之第一層,其中第三蝕刻製程一起移除圖案化之第二層與塗佈其上的高分子層;以及搭配圖案化之第一層,以圖案化材料層。
在某些實施例中,第一層包括第一CxHyOz材料,第二層包括SiCxHyOz材料,且第三層包括第二CxHyOz材料與光酸起始劑。
在某些實施例中,第一蝕刻製程採用氬氣與四氟化碳氣體,且第一蝕刻製程之壓力為約2毫托。
在某些實施例中,第二蝕刻製程包括非脈衝的電漿蝕刻製程,且電漿蝕刻製程至少採用CxHyFz氣體與氫氣。
在某些實施例中,氫氣流速介於約50sccm至約250sccm之間。
在某些實施例中,電漿蝕刻製程包括誘導耦合電
漿製程。
在某些實施例中,電漿蝕刻製程之操作偏壓介於約120伏特至約240伏特之間。
本發明又一實施例關於半導體裝置的製作方法,包括:形成材料層於基板上;形成三層光阻於材料層上,三層光阻包括底層、中間層位於底層上、以及光敏頂層位於中間層上,其中底層包括第一CxHyOz材料,中間層包括一SiCxHyOz材料,且光敏頂層包括第二CxHyOz材料與光敏單元;進行光微影製程以圖案化光敏頂層成遮罩,且遮罩具有一或多個開口,其中遮罩具有殘渣橫向延伸出遮罩外;進行第一蝕刻製程以去除遮罩的殘渣,其中第一蝕刻製程採用氬氣與四氟化碳氣體;接著以第二蝕刻製程圖案化中間層,其中第二蝕刻製程包括在蝕刻中間層時,連續沉積高分子塗層於去除殘渣後的遮罩周圍,且其中第二蝕刻製程至少採用CxHyFz氣體與氫氣;以第三蝕刻製程圖案化底層,其中第三蝕刻製程一起移除遮罩與高分子塗層;以及搭配圖案化之底層,以圖案化材料層。
在某些實施例中,第二蝕刻製程包括誘導耦合電漿製程,其操作偏壓介於約120伏特至約240伏特之間。
在某些實施例中,第二蝕刻製程的氫氣流速介於約50sccm至約250sccm之間。
上述內容已揭露多個實施例之特徵以利本技術領域中具有通常知識者理解細節。本技術領域中具有通常知識者應理解,為達上述實施例之相同目的及/或相同優點,可在本發明基礎下設計或改良其他製程結構。本技術領域中具有通常
知識者亦應理解上述等效置換並未偏離本發明精神與範疇,因此在不偏離本發明精神與範疇的情況下可進行多種變化、置換、與改變。
30‧‧‧半導體裝置
35‧‧‧基板
40‧‧‧矽化物阻擋層
45‧‧‧四乙氧矽烷層
50‧‧‧低介電常數介電層
55‧‧‧抗反射塗層
60‧‧‧氮化鈦層
65‧‧‧四乙氧矽烷層
70‧‧‧非晶矽層
90‧‧‧三層光阻
91‧‧‧底層
92A、92B、93A、93B‧‧‧部件
160‧‧‧蝕刻製程
180‧‧‧塗層
185‧‧‧高度
Claims (10)
- 一種半導體裝置的製作方法,包括:形成一材料層於一基板上;形成一三層光阻於該材料層上,該三層光阻包括一底層、一中間層位於該底層上、以及一光敏層位於該中間層上;進行一光微影製程圖案化該光敏層,以形成具有一或多個開口的一遮罩;以一第一蝕刻製程移除該遮罩不需要的部份;以及之後以一第二蝕刻製程圖案化該中間層,其中該第二蝕刻製程包括在蝕刻該中間層時,形成一塗層於該遮罩與圖案化之該中間層周圍。
- 如申請專利範圍第1項所述之半導體裝置的製作方法,更包括:以一第三蝕刻製程圖案化該底層,其中該第三蝕刻製程一起移除該遮罩與該塗層;以及搭配該圖案化之該底層,以圖案化該材料層。
- 如申請專利範圍第1項所述之半導體裝置的製作方法,其中該遮罩不需要的部份包括自該遮罩向外凸出的光阻殘渣。
- 如申請專利範圍第1項所述之半導體裝置的製作方法,其中該第一蝕刻製程採用氬氣與四氟化碳,且該第一蝕刻製程的壓力為約2毫托;其中該第二蝕刻製程包括一電漿蝕刻製程,且該電漿蝕刻製程至少採用CxHyFz氣體與氫氣,其中該氫氣係用以在蝕刻中間層時,誘導沉積高分子材料之塗層於該遮罩周圍,其 中該氫氣流速介於約50sccm至約250sccm之間,其中該電漿蝕刻製程包括一連續電漿製程,且其中該電漿蝕刻製程之操作偏壓介於約120伏特至約240伏特之間。
- 如申請專利範圍第1項所述之半導體裝置的製作方法,其中該底層包括一第一CxHyOz材料,該中間層包括一SiCxHyOz材料,且該光敏層包括一第二CxHyOz材料與一光酸起始劑。
- 一種半導體裝置的製作方法,包括:形成一材料層於一基板上;形成一三層光阻於該材料層上,該三層光阻包括一第一層、一第二層位於該第一層上、以及一第三層位於該第二層上,其中該第三層包括一光敏材料;以一光微影製程形成一圖案化之第三層,且該圖案化之第三層包括一或多個開口露出其下方的該第二層;以一第一蝕刻製程去除該圖案化之第三層的殘渣;在去除殘渣之步驟後,以一第二蝕刻製程形成一圖案化之第二層,其中該第二蝕刻製程包括在蝕刻該第二層時,連續塗佈一高分子層於該圖案化之第三層與圖案化之該第二層周圍;以一第三蝕刻製程形成一圖案化之第一層,其中該第三蝕刻製程一起移除該圖案化之第二層與塗佈其上的該高分子層;以及搭配該圖案化之第一層,以圖案化該材料層。
- 如申請專利範圍第6項所述之半導體裝置的製作方法,其中該第一層包括一第一CxHyOz材料,該第二層包括一SiCxHyOz 材料,且該第三層包括一第二CxHyOz材料與一光酸起始劑。
- 如申請專利範圍第6項所述之半導體裝置的製作方法,其中該第一蝕刻製程採用氬氣與四氟化碳氣體,且該第一蝕刻製程之壓力為約2毫托;其中該第二蝕刻製程包括一非脈衝的電漿蝕刻製程,且該電漿蝕刻製程至少採用CxHyFz氣體與氫氣,其中該氫氣流速介於約50sccm至約250sccm之間,其中該電漿蝕刻製程包括一誘導耦合電漿製程,且其中該電漿蝕刻製程之操作偏壓介於約120伏特至約240伏特之間。
- 一種半導體裝置的製作方法,包括:形成一材料層於一基板上;形成一三層光阻於該材料層上,該三層光阻包括一底層、一中間層位於該底層上、以及一光敏頂層位於該中間層上,其中該底層包括一第一CxHyOz材料,該中間層包括一SiCxHyOz材料,且該光敏頂層包括一第二CxHyOz材料與一光敏單元;進行一光微影製程以圖案化該光敏頂層成一遮罩,且該遮罩具有一或多個開口,其中該遮罩具有殘渣橫向延伸出該遮罩外;進行一第一蝕刻製程以去除該遮罩的殘渣,其中該第一蝕刻製程採用氬氣與四氟化碳氣體;接著以一第二蝕刻製程圖案化該中間層,其中該第二蝕刻製程包括在蝕刻該中間層時,連續沉積一高分子塗層於去除殘渣後的該遮罩與圖案化之該中間層周圍,且其中該第 二蝕刻製程至少採用CxHyFz氣體與氫氣;以第三蝕刻製程圖案化該底層,其中該第三蝕刻製程一起移除該遮罩與該高分子塗層;以及搭配圖案化之底層,以圖案化該材料層。
- 如申請專利範圍第9項所述之半導體裝置的製作方法,其中該第二蝕刻製程包括一誘導耦合電漿製程,其操作偏壓介於約120伏特至約240伏特之間,其中該第二蝕刻製程的氫氣流速介於約50sccm至約250sccm之間。
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US9583345B2 (en) | 2017-02-28 |
US20150187580A1 (en) | 2015-07-02 |
TW201543546A (zh) | 2015-11-16 |
DE102014118843B4 (de) | 2024-03-14 |
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