TWI525712B - 製造於大塊基板上的隔離三閘極電晶體 - Google Patents
製造於大塊基板上的隔離三閘極電晶體 Download PDFInfo
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description
本發明係關於一種製造於大塊基板上的隔離三閘極電晶體。
在積體電路裝置的製造中，隨著裝置尺寸持續縮小，多閘極電晶體，如三閘極電晶體，已變得越來越普遍。在傳統程序中，三閘極電晶體一般製造於大塊矽基板或絕緣體上覆矽基板上。在這些情形中，由於大塊矽基板成本較低，且比較不需要複雜的三閘極製造程序，因此較受歡迎。在其他情形中，絕緣體上覆矽基板上較受歡迎，因其能改善三閘極電晶體之短通道特性。
在大塊矽基板上，當將金屬閘極電極的底部與在電晶體本體(亦即「鰭片」)底部的源極和汲極延伸尖端對準時，三閘極電晶體的製程會遭遇困難。當在大塊基板上形成三閘極電晶體時，需要適當的對準以達到最佳閘極控制並減少短通道效應。例如，若源極和汲極延伸尖端比金屬閘極電極更深，則會發生貫穿現象(punch through)。相反地，若金屬閘極電極比源極和汲極延伸尖端更深，則可能產生不希望的閘極蓋件寄生。
因此，需要一種三閘極電晶體製程，結合大塊基板提供的製造上之簡單以及絕緣體上覆矽基板提供的改善之短通道效應。
在此描述一種在大塊半導體基板上製造具有改善之短通道效應的三閘極電晶體之系統及方法。在下列說明中，將使用熟悉此項技藝人士傳達其之成果給此技藝中之其他人士之常用的用語來描述例示性實施例的各種態樣。然而，對熟悉此項技藝人士而言很明顯地，本發明可僅以所述態樣的一些加以實行。為了說明，提出特定數字、材料及組態，以提供例示性實施例的詳盡理解。然而，對熟悉此項技藝人士而言很明顯地，可在無這些特定細節的情形下實行本發明。在其他例子中，省略或簡化眾所週知的特徵，以不混淆例示性實施例。
將以最能幫助理解本發明的方式，依序地描述各種操作為多個個別的操作，然而，說明之順序不應視為暗示這些操作有絕對之順序關係。尤其，無需以所呈現之順序執行這些操作。
本發明之實施例提供一種在大塊半導體基板上製造三閘極電晶體的製程，其中三閘極電晶體完全隔離，藉此結合大塊上三閘極之簡單的程序與絕緣體上覆矽上之較佳的三閘極的短通道特性。根據本發明之一實施例，三閘極電晶體的半導體本體係形成自大塊基板。此半導體本體常稱為三閘極電晶體的「鰭片」。接著，使用氧化程序在半導體本體下方製造氧化層。氧化層將半導體本體與大塊基板隔離，減少接面電容。
作為參照用，第1圖描繪傳統三閘極電晶體100。如圖示，三閘極電晶體100係形成在大塊半導體基板102上，如大塊矽基板。三閘極電晶體100包括半導體本體104，亦稱為三閘極電晶體100之鰭形結構。半導體本體104一般由與大塊基板102相同的材料形成。三閘極電晶體100亦包括由導電材料(如多晶矽或金屬)形成的金屬閘極電極106。如所示，金屬閘極電極106與半導體本體104的三個不同的表面相鄰，藉此形成電晶體的三個不同的閘極。
源極區域104A及汲極區域104B形成在半導體本體104中金屬閘極電極106的相對側上。通道區域(未標示)形成在半導體本體104中源極與汲極區域104A/B之間且在金屬閘極電極106下方。如此技藝中已知，可在通道區域中形成源極及汲極尖端延伸(未圖示)。由於半導體本體104未與基板102隔離，在介面108，尖端延伸部之底部與金屬閘極電極106的底部之對準非常重要。若尖端延伸部往下穿透到基板102中，或若尖端延伸部沒有穿透到半導體本體104的底部，會產生短通道效應的問題。
第2圖為根據本發明之一實施例在大塊基板上形成隔離的半導體本體之方法200。第3至10圖描繪當進行方法200時所形成的結構的剖面圖。
方法200首先提供大塊基板，其上將可形成本發明的隔離半導體本體(第2圖之202)。在本發明之一實施例中，可從矽或矽合金形成大塊基板。在其他實施例中，大塊基板可包括材料，如鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵或銻化鎵，上述任一可與矽結合。
大塊基板包括由如氮化矽(如Si3N4)之材料所形成的硬遮罩層。可用傳統程序來在矽大塊基板的上表面上形成氮化矽硬遮罩層，例如化學蒸氣沈積程序。第3圖描繪大塊基板300的剖面圖，其包括形成在其上表面上之氮化矽層302。
可蝕刻硬遮罩層以形成圖案化硬遮罩層(204)。此技藝中已知的傳統程序可用來圖案化硬遮罩層，如傳統的微影製程，如乾蝕刻或在CHF3、CH3F或CF4的電漿中之反應性離子蝕刻。在其他實施例中，可使用其他濕蝕刻或乾蝕刻程序。圖案化的硬遮罩層可接著作為圖案化大塊基板之遮罩，以形成鰭形結構(206)。此技藝中已知的傳統程序可用來圖案化大塊基板，如使用NH4OH的濕蝕刻程序或使用HBrCl的乾蝕刻程序。同樣地，在其他實施例中，可使用其他濕蝕刻或乾蝕刻程序。此鰭形結構可用來形成半導體本體。第4圖描繪在大塊基板300上之圖案化的硬遮罩結構302A的剖面圖。第5圖描繪藉由使用圖案化的硬遮罩結構302A作為遮罩蝕刻大塊基板300所形成之鰭形結構500的剖面圖。
接著，在鰭形結構周圍沈積淺溝槽隔離(STI)材料(208)。在本發明的各種實施例中，STI材料可為絕緣材料，如介電質材料或另一氧化材料。在一些實施例中，可用二氧化矽或SiOF作為STI材料。可用傳統沈積程序沈積STI材料，如化學蒸氣沈積(CVD)、物理蒸氣沈積(PVD)及原子層沈積(ALD)。第6圖描繪沈積在鰭形結構500旁之STI材料600的剖面圖。
接著在STI材料中形成凹部，以暴露鰭形結構的一部份(210)。鰭形結構之暴露的部份最終將變成用於三閘極裝置中之隔離半導體本體。因此，STI材料凹陷及鰭形結構暴露出來之程度或深度對應於欲形成之隔離半導體本體之希望的厚度或高度。可用傳統程序來凹陷或蝕刻STI材料，包括但不限於使用氟化氫(HF)之濕蝕刻程序或使用CHF3、CH3F或CF4的乾蝕刻程序。在其他實施例中，可使用其他濕蝕刻或乾蝕刻程序。第7圖描繪STI材料600已凹陷的剖面圖，藉此暴露出鰭形結構500的一部份。
接著，在鰭形結構500暴露的部份上形成保護氮化物蓋件(212)。先前鰭形結構暴露的部份現以包含在氮化物蓋件中並受到保護不被氧化。可由與硬遮罩材料相同的材料形成氮化物蓋件，如氮化矽(如Si3N4)，並可用傳統程序加以形成。可使用具有如矽烷或氨的先質之如CVD、PVD或ALD的沈積程序，在STI材料與鰭形結構上形成氮化物層。接著可使用諸如上述的蝕刻程序蝕刻氮化物層，以在鰭形結構上形成氮化物蓋件。第8圖描繪形成在鰭形結構500上之氮化物蓋件800的剖面圖。
根據本發明之實施例，茲進行熱氧化程序，以氧化氮化物蓋件正下方但未被其包含之鰭形結構的一部份(214)。換言之，氧化程序消耗掉在氮化物蓋件的底部邊緣下方之矽鰭片之未受保護的部份，藉此將矽轉變成氧化矽材料。受到氮化物蓋件保護之鰭形結構的部份茲藉由此新形成的氧化矽與大塊基板隔離。在本發明之實施例中，藉由在約900℃及約1100℃之間的溫度退火基板約0.5小時及約3小時之間或更長的時期來進行熱氧化程序。熱氧化可發生在含有O2、H2O、蒸氣及HCl之一或多者的大氣中。
第9圖描繪在藉由熱氧化程序消耗掉矽之一部份後的鰭形結構500之剖面圖。如所示，受到氮化物蓋件800保護之鰭形結構500的部份茲形成隔離的半導體本體900。在隔離的半導體本體900正下方的材料為氧化層，一般為二氧化矽層，其係在熱氧化程序期間形成。
在熱氧化程序之後可自隔離的半導體本體移除氮化物蓋件(216)。可使用傳統自矽移除氮化物之程序，如上述之傳統的濕或乾蝕刻程序。在一些實施例中，可使用利用磷酸之濕蝕刻程序，因其對氧化物及矽具有高選擇性。隔離的半導體本體900茲可用來形成相較於形成在大塊基板上之三閘極電晶體有改善之短通道效應的三閘極電晶體。
第10圖描繪在移除氮化物蓋件800後隔離的半導體本體900。半導體本體900係與大塊基板300隔離，茲用為三閘極電晶體的半導體本體。此後可使用傳統三閘極製程。
第11圖為根據本發明之一實施例的形成隔離半導體本體之一替代方法1100。方法1100與方法200有相同的程序，直到形成氮化物蓋件(亦即方法1100包括第2圖之程序202到212)。
一旦形成氮化物蓋件，執行STI材料之第二凹陷(方法1100的1102)。在此實施例中，第二次在STI材料中形成凹部，以暴露出在氮化物蓋件下方將會轉變成氧化物之鰭形結構的一部份。因此，STI材料凹陷的程度將取決於形成來隔離半導體本體之氧化層所希望的厚度。可使用利用氫氟酸的濕蝕刻程序或可使用緩衝的氧化物濕蝕刻來在STI材料中形成凹部。第12圖描繪在經過第二次凹陷後之STI材料600的剖面圖，藉此暴露出氮化物蓋件800下方的鰭形結構500之一部份。
根據本發明之實施例，茲進行熱氧化程序，以氧化在第二STI凹陷期間暴露出來的鰭形結構之部份(1104)。氧化程序消耗掉在暴露出來未受氮化物蓋件保護的矽，藉此將矽轉變成氧化矽材料。在此，熱氧化程序對矽具有較快速的氧化速率，因為矽暴露出來，產生較薄且較佳控制的氧化物。受到氮化物蓋件保護之鰭形結構的部份茲藉由此新形成的氧化矽與大塊基板隔離。如前述，藉由在約900℃及約1100℃之間的溫度退火基板約0.5小時及約3小時之間或更長的時期來進行熱氧化程序。熱氧化可發生在含有O2、H2O、蒸氣及HCl之一或多者的大氣中。
第13圖描繪在藉由熱氧化程序消耗掉矽之暴露的部份之後形成氧化層1300之鰭形結構500的剖面圖。如所示，受到氮化物蓋件800保護的鰭形結構500之部份茲形成隔離的半導體本體900。在隔離的半導體本體900正下方的材料為氧化層1300，一般為二氧化矽層，其係在熱氧化程序期間形成。
在熱氧化程序之後可自隔離的半導體本體移除氮化物蓋件(1106)。可使用傳統自矽移除氮化物之程序，如上述。隔離的半導體本體900茲可用來形成相較於形成在大塊基板上之三閘極電晶體有改善之短通道效應的三閘極電晶體。第14圖描繪在移除氮化物蓋件800後隔離的半導體本體900。同樣地，此後可使用傳統之三閘極製程。
因此，已描述在大塊基板上形成隔離半導體本體之方法。根據本發明之實施例，在半導體本體下方形成氧化層提供閘極與源極/汲極的尖端延伸部之自行對準，以達到最佳閘極控制。額外的優點包括源極與汲極尖端延伸部所需之工程的簡化、源極與汲極接面電容之減少及在主動三閘極裝置下較薄之隔離層的產生，其提供比使用較厚的隔離層之標準絕緣體上覆矽裝置有更好的短通道免除性。此外，本發明之完全隔離的半導體本體可致能其他絕緣體上覆矽類型的應用，如具有浮體之單一裝置記憶體，即使起始晶圓為大塊矽。
上述本發明之例示性實施例的說明，包括發明摘要的部份，並非意圖為窮舉或限制本發明於所揭露的精確形式。雖為了說明而在此描述本發明之特定實施例及範例，可有落入本發明之範疇的熟悉此項技藝人士所知之各種等效變更。
可在閱讀上述詳細說明後對本發明做出這些變更。在所附之申請專利範圍中所用的用詞不應視為將本發明限制於說明書及申請專利範圍中所揭露的特定實施例。確切而言，本發明之範疇將完全由所附之申請專利範圍而定，其應依照既定之申請專利範圍釋義原則加以解釋。
100．．．三閘極電晶體
102．．．大塊半導體基板
104．．．半導體本體
104A．．．源極區域
104B．．．汲極區域
106．．．金屬閘極電極
108．．．介面
300．．．大塊基板
302．．．氮化矽層
302A．．．硬遮罩結構
500．．．鰭形結構
600．．．淺溝槽隔離材料
800．．．氮化物蓋件
900．．．隔離的半導體本體
1300．．．氧化層
第1圖描繪傳統三閘極裝置。
第2圖為根據本發明之一實施例的之形成隔離之半導體本體的方法。
第3至10圖描繪當進行第2圖的程序時所形成的結構。
第11圖為根據本發明之另一實施例的形成隔離之半導體本體的方法。
第12至14圖描繪當進行第11圖的程序時所形成的結構。
Claims (2)
- 一種三閘極電晶體，包含：大塊基板；鰭形結構，其與該大塊基板直接接觸且自該大塊基板延伸；氧化層，其形成在該鰭形結構頂上；以及半導體本體，其形成於該氧化層頂上，其中該氧化層係以熱氧化程序形成，熱氧化程序消耗掉該鰭形結構的一部分，且其中在該大塊基板上之該氧化層的一部份朝該大塊基板相對於在該鰭形結構與該半導體本體之間直接沈積的該氧化層的一部份凹陷。
- 如申請專利範圍第1項之三閘極電晶體，其中該鰭形結構包含矽，該大塊基板包含矽，該半導體本體包含矽，以及該氧化層包含氧化矽。
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| US20090020792A1 (en) | 2009-01-22 |
| KR20100022526A (ko) | 2010-03-02 |
| TW200919589A (en) | 2009-05-01 |
| DE112008001835T5 (de) | 2010-07-22 |
| JP2010533978A (ja) | 2010-10-28 |
| CN105938853A (zh) | 2016-09-14 |
| GB2464061A (en) | 2010-04-07 |
| CN102683415B (zh) | 2016-01-27 |
| TW201236087A (en) | 2012-09-01 |
| KR101208781B1 (ko) | 2012-12-05 |
| JP5746238B2 (ja) | 2015-07-08 |
| WO2009012053A2 (en) | 2009-01-22 |
| US20100059821A1 (en) | 2010-03-11 |
| KR20110131322A (ko) | 2011-12-06 |
| CN102683415A (zh) | 2012-09-19 |
| TWI438848B (zh) | 2014-05-21 |
| WO2009012053A3 (en) | 2009-03-12 |
| JP2013140999A (ja) | 2013-07-18 |
| BRPI0814114A2 (pt) | 2015-02-03 |
| GB201001820D0 (en) | 2010-03-24 |
| US7973389B2 (en) | 2011-07-05 |
| CN101755327A (zh) | 2010-06-23 |
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