US20090020792A1 - Isolated tri-gate transistor fabricated on bulk substrate - Google Patents

Isolated tri-gate transistor fabricated on bulk substrate Download PDF

Info

Publication number
US20090020792A1
US20090020792A1 US11/779,284 US77928407A US2009020792A1 US 20090020792 A1 US20090020792 A1 US 20090020792A1 US 77928407 A US77928407 A US 77928407A US 2009020792 A1 US2009020792 A1 US 2009020792A1
Authority
US
United States
Prior art keywords
fin structure
around
semiconductor body
bulk substrate
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/779,284
Other languages
English (en)
Inventor
Rafael Rios
Jack Kavalieros
Stephen M. Cea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US11/779,284 priority Critical patent/US20090020792A1/en
Priority to GB1001820A priority patent/GB2464061A/en
Priority to KR1020117028038A priority patent/KR101208781B1/ko
Priority to PCT/US2008/068855 priority patent/WO2009012053A2/en
Priority to CN201210137882.7A priority patent/CN102683415B/zh
Priority to BRPI0814114-2A2A priority patent/BRPI0814114A2/pt
Priority to CN200880025190A priority patent/CN101755327A/zh
Priority to DE112008001835T priority patent/DE112008001835T5/de
Priority to KR1020107001149A priority patent/KR20100022526A/ko
Priority to JP2010517060A priority patent/JP2010533978A/ja
Priority to CN201610262388.1A priority patent/CN105938853A/zh
Priority to TW101115144A priority patent/TWI525712B/zh
Priority to TW097124714A priority patent/TWI438848B/zh
Publication of US20090020792A1 publication Critical patent/US20090020792A1/en
Priority to US12/590,562 priority patent/US7973389B2/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CEA, STEPHEN M, KAVALIEROS, JACK, RIOS, RAFAEL
Priority to JP2013025282A priority patent/JP5746238B2/ja
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

Definitions

  • tri-gate transistors In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down.
  • tri-gate transistors In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In other instances, silicon-on-insulator substrates are preferred because of the improved short-channel behavior of tri-gate transistors.
  • the fabrication process for tri-gate transistors often encounters problems when aligning the bottom of the metal gate electrode with the source and drain extension tips at the bottom of the transistor body (i.e., the “fin”).
  • the tri-gate transistor is formed on a bulk substrate, proper alignment is needed for optimal gate control and to reduce short-channel effects. For instance, if the source and drain extension tips are deeper than the metal gate electrode, punch-through may occur. Alternately, if the metal gate electrode is deeper than the source and drain extension tips, the result may be an unwanted gate cap parasitic.
  • FIG. 1 illustrates a conventional tri-gate device.
  • FIG. 2 is a method of forming an isolated semiconductor body in accordance with an implementation of the invention.
  • FIGS. 3 to 10 illustrate structures formed when the process of FIG. 2 is carried out.
  • FIG. 11 is a method of forming an isolated semiconductor body in accordance with another implementation of the invention.
  • FIGS. 12 to 14 illustrate structures formed when the process of FIG. 11 is carried out.
  • Described herein are systems and methods of fabricating a tri-gate transistor on a bulk semiconductor substrate with improved short channel effects.
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • Implementations of the invention provide a fabrication process for a tri-gate transistor on a bulk semiconductor substrate where the tri-gate transistor is fully isolated, thereby combining the simple tri-gate on bulk process with the better short-channel behavior of tri-gate on silicon-on-insulator.
  • a semiconductor body for the tri-gate transistor is formed out of the bulk substrate. This semiconductor body is often referred to as the “fin” of a tri-gate transistor.
  • an oxide layer is fabricated beneath the semiconductor body using an oxidation process. The oxide layer isolates the semiconductor body from the bulk substrate and reduces junction capacitance.
  • FIG. 1 illustrates a conventional tri-gate transistor 100 .
  • the tri-gate transistor 100 is formed on a bulk semiconductor substrate 102 , such as a bulk silicon substrate.
  • the tri-gate transistor 100 includes a semiconductor body 104 , also known as the fin structure of the tri-gate transistor 100 .
  • the semiconductor body 104 is generally formed from the same material as the bulk substrate 102 .
  • the tri-gate transistor 100 also includes a metal gate electrode 106 formed from a conductive material such as polysilicon or a metal. As shown, the metal gate electrode 106 is adjacent to three separate surfaces of the semiconductor body 104 , thereby forming three separate gates for the transistor.
  • a source region 104 A and a drain region 104 B are formed in the semiconductor body 104 on opposite sides of the metal gate electrode 106 .
  • a channel region (not labeled) is formed in the semiconductor body 104 between the source and drain regions 104 A/B and below the metal gate electrode 106 .
  • source and drain tip extensions may be formed in the channel region. Since the semiconductor body 104 is not isolated from the substrate 102 , at interface 108 , alignment of the bottom of the tip extensions with the bottom of the metal gate electrode 106 is critical. If the tip extensions penetrate down into the substrate 102 , or if the tip extensions do not penetrate to the bottom of the semiconductor body 104 , short-channel effect issues may arise.
  • FIG. 2 is a method 200 of forming an isolated semiconductor body on a bulk substrate in accordance with an implementation of the invention.
  • FIGS. 3 through 10 illustrate cross-sections of structures that are formed when the method 200 is carried out.
  • the method 200 begins by providing a bulk substrate upon which the isolated semiconductor body of the invention may be formed ( 202 of FIG. 2 ).
  • the bulk substrate may be formed from silicon or a silicon alloy.
  • the bulk substrate may include materials such as germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, any of which may be combined with silicon.
  • the bulk substrate includes a hard mask layer formed from a material such as silicon nitride (e.g., Si 3 N 4 ).
  • the silicon nitride hard mask layer may be formed using conventional processes, such as a chemical vapor deposition process on a top surface of the silicon bulk substrate.
  • FIG. 3 illustrates a cross-section of a bulk substrate 300 that includes a silicon nitride layer 302 formed on its top surface.
  • the hard mask layer may be etched to form a patterned hard mask layer ( 204 ).
  • Conventional processes known in the art may be used to pattern the hard mask layer, such as conventional lithography processes using a dry etch or a reactive ion etch in plasmas of CHF 3 , CH 3 F, or CF 4 . In further implementations, other wet or dry etching processes may be used.
  • the patterned hard mask layer may then be used as a mask to pattern the bulk substrate to form a fin structure ( 206 ). Conventional processes known in the art may be used to pattern the bulk substrate, such as a wet etching process using NH 4 OH or a dry etching process using HBrCl.
  • FIG. 4 illustrates a cross-section of a patterned hard mask structure 302 A on the bulk substrate 300 .
  • FIG. 5 illustrates a cross-section of a fin structure 500 that has been formed by etching the bulk substrate 300 using the patterned hard mask structure 302 A as a mask.
  • a shallow trench isolation (STI) material is deposited around the fin structure ( 208 ).
  • the STI material may be an insulating material, such as a dielectric material or another oxide material.
  • silicon dioxide or SiOF may be used as the STI material.
  • the STI material may be deposited using conventional deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).
  • FIG. 6 illustrates a cross-section of an STI material 600 that has been deposited adjacent to the fin structure 500 .
  • the STI material is then recessed to expose a portion of the fin structure ( 210 ).
  • the exposed portion of the fin structure will eventually become an isolated semiconductor body for use in a tri-gate device. Accordingly, the degree or depth to which the STI material is recessed and the fin structure is exposed corresponds to a desired thickness or height of the isolated semiconductor body being formed.
  • Conventional processes may be used to recess or etch the STI material, including but not limited to wet etching processes using hydrogen fluoride (HF) or dry etching processes using CHF 3 , CH 3 F, or CF 4 . In further implementations, other wet or dry etching processes may be used.
  • FIG. 7 illustrates a cross-section of the STI material 600 after it has been recessed, thereby exposing a portion of the fin structure 500 .
  • a protective nitride cap is formed over the exposed portion of the fin structure 500 ( 212 ).
  • the previously exposed portions of the fin structure are now contained within the nitride cap and protected from oxidation.
  • the nitride cap may be formed of the same material as the hard mask material, such as silicon nitride (e.g., Si 3 N 4 ), and may be formed using conventional processes. For instance, a deposition process such as CVD, PVD, or ALD may be used with precursors such as silane and ammonia to form a nitride layer over the STI material and the fin structure.
  • FIG. 8 illustrates a cross-section of a nitride cap 800 formed on the fin structure 500 .
  • a thermal oxidation process is now carried out to oxidize a portion of the fin structure that is just below but not contained within the nitride cap ( 214 ).
  • the oxidation process consumes an unprotected portion of the silicon fin that is below the bottom edge of the nitride cap, thereby converting the silicon into a silicon oxide material.
  • the portion of the fin structure protected by the nitride cap now becomes isolated from the bulk substrate by this newly formed silicon oxide.
  • the thermal oxidation process may be carried out by annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours or more.
  • the thermal oxidation may take place in an atmosphere that contains one or more of O 2 , H 2 O, steam, and HCl.
  • FIG. 9 illustrates a cross-section of the fin structure 500 after a portion of the silicon has been consumed by the thermal oxidation process. As shown, the portion of the fin structure 500 protected by the nitride cap 800 now forms an isolated semiconductor body 900 .
  • the material directly below the isolated semiconductor body 900 is an oxide layer, generally a silicon dioxide layer, formed during the thermal oxidation process.
  • the nitride cap may be removed from the isolated semiconductor body after the thermal oxidation process ( 216 ).
  • Conventional processes for removing a nitride from silicon may be used, such as the conventional wet or dry etching processes detailed above.
  • a wet etch process using phosphoric acid may be used since it has a high selectivity to both oxides and silicon.
  • the isolated semiconductor body 900 may now be used to form a tri-gate transistor with improved short-channel effects relative to conventional tri-gate transistors formed on bulk silicon.
  • FIG. 10 illustrates isolated semiconductor body 900 after the nitride cap 800 is removed.
  • the semiconductor body 900 is isolated from the bulk substrate 300 and may now be used as a semiconductor body for a tri-gate transistor. Conventional tri-gate fabrication processes may be used from this point forward.
  • FIG. 11 is an alternate method 1100 of forming an isolated semiconductor body in accordance with an implementation of the invention.
  • the method 1100 follows the same process as the method 200 until the nitride cap is formed (i.e., the method 1100 includes the processes 202 through 212 of FIG. 2 ).
  • a second recess of the STI material is performed ( 1102 of method 1100 ).
  • the STI material is recessed a second time to expose a portion of the fin structure below the nitride cap that will be converted into an oxide.
  • the degree to which the STI material is recessed here will depend on the desired thickness of oxide layer being formed to isolate the semiconductor body.
  • a wet etch process using hydrofluoric acid or a buffered oxide wet etch may be used to recess the STI material.
  • FIG. 12 illustrates a cross-section of the STI material 600 after it has been recessed second time, thereby exposing a portion of the fin structure 500 below the nitride cap 800 .
  • a thermal oxidation process is now carried out to oxidize the portion of the fin structure that was exposed during the second STI recess ( 1104 ).
  • the oxidation process consumes the silicon that is exposed and not protected by the nitride cap, converting the silicon into a silicon oxide material.
  • the thermal oxidation process has a faster oxidation rate on the silicon because the silicon is exposed, yielding a relatively thinner and better controlled oxide.
  • the portion of the fin structure protected by the nitride cap now becomes isolated from the bulk substrate by this newly formed silicon oxide.
  • the thermal oxidation process may be carried out by annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours or more.
  • the thermal oxidation may take place in an atmosphere that contains one or more of O 2 , H 2 O, steam, and HCl.
  • FIG. 13 illustrates a cross-section of the fin structure 500 after the exposed portion of the silicon has been consumed by the thermal oxidation process to form an oxide layer 1300 .
  • the portion of the fin structure 500 protected by the nitride cap 800 now forms an isolated semiconductor body 900 .
  • the material directly below the isolated semiconductor body 900 is the oxide layer 1300 , generally a silicon dioxide layer, formed during the thermal oxidation process.
  • the nitride cap may now be removed from the isolated semiconductor body after the thermal oxidation process ( 1106 ).
  • Conventional processes for removing a nitride from silicon may be used, as described above.
  • the isolated semiconductor body 900 may now be used to form a tri-gate transistor with improved short-channel effects relative to conventional tri-gate transistors formed on bulk silicon.
  • FIG. 14 illustrates the isolated semiconductor body 900 after the nitride cap 800 is removed.
  • conventional tri-gate fabrication processes may be used from this point forward.
  • an isolated semiconductor body on a bulk substrate provides self alignment of the gate and source/drain tip extensions for optimal gate control. Additional benefits include a simplification of engineering required for the source and drain tip extensions, a reduction of source and drain junction capacitance, and the creation of a relatively thin isolation layer under the active tri-gate device, which provides improved short-channel immunity relative to standard silicon-on-insulator devices that use a relatively thick isolation layer.
  • the fully isolated semiconductor body of the invention enables other silicon-on-insulator type applications, such as a single device memory with a floating body, even though the starting wafer is bulk silicon.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US11/779,284 2007-07-18 2007-07-18 Isolated tri-gate transistor fabricated on bulk substrate Abandoned US20090020792A1 (en)

Priority Applications (15)

Application Number Priority Date Filing Date Title
US11/779,284 US20090020792A1 (en) 2007-07-18 2007-07-18 Isolated tri-gate transistor fabricated on bulk substrate
DE112008001835T DE112008001835T5 (de) 2007-07-18 2008-06-30 Auf einem Bulk-Substrat hergestellter isolierter Tri-Gate-Transistor
CN201610262388.1A CN105938853A (zh) 2007-07-18 2008-06-30 体衬底上制造的被隔离的三栅极晶体管
PCT/US2008/068855 WO2009012053A2 (en) 2007-07-18 2008-06-30 Isolated tri-gate transistor fabricated on bulk substrate
CN201210137882.7A CN102683415B (zh) 2007-07-18 2008-06-30 体衬底上制造的被隔离的三栅极晶体管
BRPI0814114-2A2A BRPI0814114A2 (pt) 2007-07-18 2008-06-30 Transistor de tríplices saídas isolado fabricado sobre substrato volumoso
CN200880025190A CN101755327A (zh) 2007-07-18 2008-06-30 体衬底上制造的被隔离的三栅极晶体管
GB1001820A GB2464061A (en) 2007-07-18 2008-06-30 Isolated tri-gate transistor fabricated on bulk substrate
KR1020107001149A KR20100022526A (ko) 2007-07-18 2008-06-30 벌크 기판 상에 제조되는 분리된 트라이-게이트 트랜지스터
JP2010517060A JP2010533978A (ja) 2007-07-18 2008-06-30 バルク基板上に作製される分離トライゲートトランジスタ
KR1020117028038A KR101208781B1 (ko) 2007-07-18 2008-06-30 벌크 기판 상에 제조되는 분리된 트라이-게이트 트랜지스터
TW101115144A TWI525712B (zh) 2007-07-18 2008-07-01 製造於大塊基板上的隔離三閘極電晶體
TW097124714A TWI438848B (zh) 2007-07-18 2008-07-01 製造於大塊基板上的隔離三閘極電晶體
US12/590,562 US7973389B2 (en) 2007-07-18 2009-11-10 Isolated tri-gate transistor fabricated on bulk substrate
JP2013025282A JP5746238B2 (ja) 2007-07-18 2013-02-13 バルク基板上に作製される分離トライゲートトランジスタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/779,284 US20090020792A1 (en) 2007-07-18 2007-07-18 Isolated tri-gate transistor fabricated on bulk substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/590,562 Division US7973389B2 (en) 2007-07-18 2009-11-10 Isolated tri-gate transistor fabricated on bulk substrate

Publications (1)

Publication Number Publication Date
US20090020792A1 true US20090020792A1 (en) 2009-01-22

Family

ID=40260297

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/779,284 Abandoned US20090020792A1 (en) 2007-07-18 2007-07-18 Isolated tri-gate transistor fabricated on bulk substrate
US12/590,562 Expired - Fee Related US7973389B2 (en) 2007-07-18 2009-11-10 Isolated tri-gate transistor fabricated on bulk substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/590,562 Expired - Fee Related US7973389B2 (en) 2007-07-18 2009-11-10 Isolated tri-gate transistor fabricated on bulk substrate

Country Status (9)

Country Link
US (2) US20090020792A1 (zh)
JP (2) JP2010533978A (zh)
KR (2) KR20100022526A (zh)
CN (3) CN105938853A (zh)
BR (1) BRPI0814114A2 (zh)
DE (1) DE112008001835T5 (zh)
GB (1) GB2464061A (zh)
TW (2) TWI525712B (zh)
WO (1) WO2009012053A2 (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130020640A1 (en) * 2011-07-18 2013-01-24 Chen John Y Semiconductor device structure insulated from a bulk silicon substrate and method of forming the same
US8609480B2 (en) 2011-12-21 2013-12-17 Globalfoundries Inc. Methods of forming isolation structures on FinFET semiconductor devices
WO2014004049A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Isolated and bulk semiconductor devices formed on a same bulk substrate
US20140015056A1 (en) * 2012-07-10 2014-01-16 Ssu-I Fu Multi-gate mosfet and process thereof
US20140239393A1 (en) * 2013-02-22 2014-08-28 Taiwan Semiconuductor Manufacturing Company, Ltd. Finfet device and method of manufacturing same
CN104124168A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US20150262861A1 (en) * 2008-12-31 2015-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights
US9722025B2 (en) 2008-05-06 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US11114563B2 (en) 2009-02-24 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with low junction capacitances and methods of fabrication thereof

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090020792A1 (en) 2007-07-18 2009-01-22 Rafael Rios Isolated tri-gate transistor fabricated on bulk substrate
US9076873B2 (en) 2011-01-07 2015-07-07 International Business Machines Corporation Graphene devices with local dual gates
US8987835B2 (en) * 2012-03-27 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with a buried semiconductor material between two fins
US9035430B2 (en) 2012-08-29 2015-05-19 International Business Machines Corporation Semiconductor fin on local oxide
US9041106B2 (en) * 2012-09-27 2015-05-26 Intel Corporation Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates
US9287178B2 (en) 2012-10-01 2016-03-15 Globalfoundries Inc. Multi-gate field effect transistor (FET) including isolated fin body
US8759874B1 (en) 2012-11-30 2014-06-24 Stmicroelectronics, Inc. FinFET device with isolated channel
US8956942B2 (en) 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US10438856B2 (en) 2013-04-03 2019-10-08 Stmicroelectronics, Inc. Methods and devices for enhancing mobility of charge carriers
US9257327B2 (en) 2013-04-09 2016-02-09 Samsung Electronics Co., Ltd. Methods of forming a Field Effect Transistor, including forming a region providing enhanced oxidation
US9947772B2 (en) 2014-03-31 2018-04-17 Stmicroelectronics, Inc. SOI FinFET transistor with strained channel
US9209185B2 (en) * 2014-04-16 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET device
US9502518B2 (en) 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
US9224736B1 (en) * 2014-06-27 2015-12-29 Taiwan Semicondcutor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device
CN106688102B (zh) * 2014-08-05 2021-05-25 英特尔公司 用于通过催化剂氧化物形成而创建微电子器件隔离的设备和方法
CN104299914B (zh) * 2014-08-08 2018-06-01 武汉新芯集成电路制造有限公司 FinFET的制造方法
KR102150254B1 (ko) 2014-09-15 2020-09-02 삼성전자주식회사 반도체 소자의 제조 방법
KR102287398B1 (ko) * 2015-01-14 2021-08-06 삼성전자주식회사 반도체 장치
KR102251061B1 (ko) 2015-05-04 2021-05-14 삼성전자주식회사 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법
US9520500B1 (en) 2015-12-07 2016-12-13 International Business Machines Corporation Self heating reduction for analog radio frequency (RF) device
US9748404B1 (en) 2016-02-29 2017-08-29 International Business Machines Corporation Method for fabricating a semiconductor device including gate-to-bulk substrate isolation
US10930793B2 (en) 2017-04-21 2021-02-23 International Business Machines Corporation Bottom channel isolation in nanosheet transistors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001234A1 (en) * 2006-06-30 2008-01-03 Kangguo Cheng Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3219307B2 (ja) * 1991-08-28 2001-10-15 シャープ株式会社 半導体装置の構造および製造方法
JPH06342911A (ja) * 1993-06-01 1994-12-13 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH0786595A (ja) * 1993-09-14 1995-03-31 Fujitsu Ltd 半導体装置とその製造方法
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7728360B2 (en) * 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
JP4911976B2 (ja) * 2003-12-08 2012-04-04 インターナショナル・ビジネス・マシーンズ・コーポレーション ノード・キャパシタンスを増加した半導体メモリ・デバイス
US7005700B2 (en) * 2004-01-06 2006-02-28 Jong Ho Lee Double-gate flash memory device
JP2006086188A (ja) * 2004-09-14 2006-03-30 Seiko Epson Corp 半導体装置および半導体装置の製造方法
US7229889B2 (en) * 2005-03-10 2007-06-12 International Business Machines Corporation Methods for metal plating of gate conductors and semiconductors formed thereby
KR20060124904A (ko) * 2005-06-01 2006-12-06 매그나칩 반도체 유한회사 핀 전계효과 트랜지스터의 제조방법
KR100645065B1 (ko) * 2005-06-23 2006-11-10 삼성전자주식회사 핀 전계 효과 트랜지스터와 이를 구비하는 비휘발성 메모리장치 및 그 형성 방법
US8779495B2 (en) * 2007-04-19 2014-07-15 Qimonda Ag Stacked SONOS memory
US20090020792A1 (en) 2007-07-18 2009-01-22 Rafael Rios Isolated tri-gate transistor fabricated on bulk substrate
JP5032418B2 (ja) * 2008-08-22 2012-09-26 株式会社東芝 電界効果トランジスタ、集積回路素子、及びそれらの製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001234A1 (en) * 2006-06-30 2008-01-03 Kangguo Cheng Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11133387B2 (en) 2008-05-06 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US10312327B2 (en) 2008-05-06 2019-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US9722025B2 (en) 2008-05-06 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US20150262861A1 (en) * 2008-12-31 2015-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights
US9735042B2 (en) * 2008-12-31 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual Fin heights
US11114563B2 (en) 2009-02-24 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with low junction capacitances and methods of fabrication thereof
US20130020640A1 (en) * 2011-07-18 2013-01-24 Chen John Y Semiconductor device structure insulated from a bulk silicon substrate and method of forming the same
US8692316B2 (en) 2011-12-21 2014-04-08 Globalfoundries Inc. Isolation structures for FinFET semiconductor devices
US8609480B2 (en) 2011-12-21 2013-12-17 Globalfoundries Inc. Methods of forming isolation structures on FinFET semiconductor devices
US9425212B2 (en) 2012-06-29 2016-08-23 Intel Corporation Isolated and bulk semiconductor devices formed on a same bulk substrate
US9978636B2 (en) 2012-06-29 2018-05-22 Intel Corporation Isolated and bulk semiconductor devices formed on a same bulk substrate
WO2014004049A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Isolated and bulk semiconductor devices formed on a same bulk substrate
US9269791B2 (en) * 2012-07-10 2016-02-23 United Microelectronics Corp. Multi-gate MOSFET with embedded isolation structures
US20140015056A1 (en) * 2012-07-10 2014-01-16 Ssu-I Fu Multi-gate mosfet and process thereof
US9166053B2 (en) * 2013-02-22 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device including a stepped profile structure
US9514991B2 (en) 2013-02-22 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a FinFET device having a stepped profile
US20140239393A1 (en) * 2013-02-22 2014-08-28 Taiwan Semiconuductor Manufacturing Company, Ltd. Finfet device and method of manufacturing same
CN104124168A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Also Published As

Publication number Publication date
CN101755327A (zh) 2010-06-23
DE112008001835T5 (de) 2010-07-22
GB201001820D0 (en) 2010-03-24
TW200919589A (en) 2009-05-01
BRPI0814114A2 (pt) 2015-02-03
JP5746238B2 (ja) 2015-07-08
TW201236087A (en) 2012-09-01
CN102683415A (zh) 2012-09-19
KR20100022526A (ko) 2010-03-02
WO2009012053A3 (en) 2009-03-12
CN102683415B (zh) 2016-01-27
JP2013140999A (ja) 2013-07-18
KR20110131322A (ko) 2011-12-06
WO2009012053A2 (en) 2009-01-22
KR101208781B1 (ko) 2012-12-05
US20100059821A1 (en) 2010-03-11
JP2010533978A (ja) 2010-10-28
CN105938853A (zh) 2016-09-14
US7973389B2 (en) 2011-07-05
GB2464061A (en) 2010-04-07
TWI438848B (zh) 2014-05-21
TWI525712B (zh) 2016-03-11

Similar Documents

Publication Publication Date Title
US7973389B2 (en) Isolated tri-gate transistor fabricated on bulk substrate
KR101729439B1 (ko) 매립된 절연체층을 가진 finfet 및 그 형성 방법
US10991795B2 (en) Semiconductor device and manufacturing method thereof
CN100524653C (zh) 各向异性湿蚀刻的器件制造方法及对应器件
CN102074461B (zh) 半导体装置及其制造方法
CN101183664B (zh) 半导体结构及制造多个鳍片场效应晶体管的方法
TWI450341B (zh) 具有自校準的外延源極和汲極之多閘極半導體裝置
US8455859B2 (en) Strained structure of semiconductor device
US20060115949A1 (en) Semiconductor fabrication process including source/drain recessing and filling
CN104752503A (zh) 用于形成具有不同鳍高度的finfet的方法
US20130313655A1 (en) Semiconductor device and a method for manufacturing the same
US9660030B2 (en) Replacement gate electrode with a self-aligned dielectric spacer
US8629028B2 (en) Metal oxide semiconductor field effect transistor (MOSFET) gate termination
CN102117773A (zh) 半导体器件和使用应力记忆技术工艺制造半导体器件的方法
KR100540339B1 (ko) 반도체 제조 공정에 있어서의 게이트 구조 형성 방법

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RIOS, RAFAEL;KAVALIEROS, JACK;CEA, STEPHEN M;REEL/FRAME:026013/0469

Effective date: 20070710