CN100524653C - 各向异性湿蚀刻的器件制造方法及对应器件 - Google Patents
各向异性湿蚀刻的器件制造方法及对应器件 Download PDFInfo
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Abstract
本发明提供了一种各向异性湿蚀刻的器件制造方法及对应器件，具体地，提供了一种减小源极/漏极电容并且允许器件体接触的方法和场效应器件结构。制造Si基材料基底，其上表面和侧壁在一定程度上取向为与基底和支撑部件的选择晶面基本平行。用含氢氧化铵的各向异性溶液湿蚀刻基底。基底的侧壁变为刻面，在基底中形成具有减小的截面的片段。选择在减小的截面片段中的掺杂剂浓度足够高，以提供穿过基底的电连续。
Description
技术领域
本发明涉及在集成电路中使用的器件及它们的制造。更具体地说，本发明涉及提高器件性能的场效应器件制造工艺，并且涉及所得的器件结构。
背景技术
现在的集成电路包括大量的器件。更小的器件和缩减的基本规则是增强性能并提高可靠性的关键。当FET(场效应晶体管)器件减小时，技术变得更复杂，并且需要器件结构的改变和新的制造方法以保持从一代器件到下一代的期望的性能增强。微电子的支柱材料是硅(Si)或者更广义的说是硅基材料。对微电子，重要的一种这样的Si基材料是硅锗(SiGe)合金。
在深亚微米时代的器件中保持性能的提高很困难。随着器件尺寸的持续降低，各种有害的器件效应变的更严重。例如，随着栅极长度缩短，称为短沟道效应，最显著的“漏极引起势垒降低”引起小型化的严重障碍。如源极和漏极电容的寄生电容也妨碍器件的性能。技术上已经发现了几种方法用于保持器件性能的稳定提高。一种处理有害的器件电容的方法是利用称作绝缘体上半导体(SOI)的技术，通常Si在绝缘体上。优选，在绝缘体层上的薄半导体层中制造SOI器件。更优选，绝缘层是在Si衬底上所谓的掩埋氧化物层。
通常，与在体衬底上形成的器件相比，在SOI技术中形成的FET器件具有降低的源极/漏极电容的优点。当SOI场效应器件尺寸减小时，为了具有更好的阈值电压(Vt)的短沟道控制，优选也减小SOI Si层的厚度。最后，SOI Si层厚度的减小导致FET具有浮置体。浮置器件体意味着器件体电势不受通过体接触提供的电压的约束。在这样的情况下，器件的阈值电压，Vt，控制更难。在体Si衬底上形成的场效应器件可以具有体接触，但是具有较高的源极/漏极电容。期望拥有结合低源极/漏极电容和体接触能力的器件。
发明内容
考虑到所讨论的问题，本发明公开了一种减小源极/漏极电容并且还允许器件体接触的制造方法和场效应器件结构。该方法包括优选通过在单晶Si基材料部件中形成沟槽，制造Si基材料基底。该基底的上表面和侧壁取向为与Si基材料部件的选择晶面基本平行。该方法还包括用含氢氧化铵(NH4OH)的溶液湿蚀刻Si基材料基底。因为Si基材料晶面在NH4OH溶液中的蚀刻速率不同，侧壁变为刻面(faceted)，从而底切Si基材料基底的第一片段并且形成在第一片段下的第二片段。第二片段具有比第一片段更小的截面。在第二片段中，为了导电掺杂剂的浓度足够高，从而允许Si基材料部件和通过Si基材料基底的第一片段寄宿的场效应器件之间的体接触。场效应器件具有降低的源极/漏极电容，因为第一片段的底切使器件的源极/漏极类似于SOI器件的源极/漏极。
附图说明
从随后的细节描述和附图，本发明的这些和其它特征将更明显，其中：
图1示出了在Si基材料部件中制造基底的初始阶段的截面示意图；
图2示出了在Si基材料部件中制造基底的截面示意图，其中提供了保护层并且限定了沟槽位置；
图3示出了在Si基材料部件中制造基底的截面示意图，其中制备结构用于形成沟槽；
图4示出了在Si基材料部件中制造基底的截面示意图，其中已经形成沟槽，限定基底；
图5示出了在Si基材料部件中制造基底的截面示意图，其中已经进行湿各向异性蚀刻；
图6示出了刻面底切基底的截面示意图；以及
图7示出了由刻面底切基底寄宿的场效应器件的截面示意图。
具体实施方式
图1示出了制造基底的初始阶段的截面示意图，基底包括绝缘体上半导体(SOI)，通常为绝缘体上Si晶片。应该明白，制造基底的描述的许多方面指代表性实施例，不应该理解为限制方式，作为本领域的技术人员将认识到制造的可选途径。
提供晶片是器件制造工艺的起点。晶片可以是体Si晶片，在表面上具有Si基材料层的Si晶片，或绝缘体上半导体(SOI)晶片。附图描述了一个使用SOI晶片的示意性实施例，应该明白等同于示出了体晶片。在图1中，Si基材料部件10是在掩埋绝缘层90上面的SOI晶片层。在部件10是体晶片的可选实施例中，不存在绝缘层90。对SOI晶片，优选Si基材料部件10足够厚以寄宿部分耗尽的FET。在所有的优选实施例中，在将要设置基底的区域中的Si基材料部件10是单晶材料类型，如通常在Si基微电子技术中的一样。在此公开的各种实施例中，Si基材料可以是基本纯Si，或者它可以是具有Ge浓度高达约60％的SiGe合金。
在本发明的代表性实施例中，通过热氧化或化学气相沉积(CVD)在部件10上形成薄介质层50，优选约2nm到约20nm厚的衬垫氧化物。在氧化物50的顶部，使用CVD沉积工艺沉积优选为衬垫氮化物的另一介质60。在优选实施例中，衬垫氮化物60的厚度在20nm到200nm的范围内。氧化物50和氮化物60层用作以后限定有源器件区域和隔离区域，并且在随后的工艺期间保护表面。本领域的技术人员将认识到，可以通过除了氧化物和氮化物层以外的其它方式达到这样的目标。
图2示出了在Si基材料部件中制造基底的截面示意图，其中提供了保护层并且限定了沟槽位置。通过光刻工艺分离有源FET器件区域和沟槽隔离区域，并且优选使用反应离子蚀刻(RIE)工艺除去部分Si基材料到约20nm到60nm的深度。在可选的实施例中，可以省略浅Si基材料的去除。
图3示出了在Si基材料部件中制造基底的截面示意图，其中制备结构用于形成沟槽。通过技术上公知的工艺，延伸氮化物层60以保护先前浅Si基材料的去除中暴露的侧壁。
图4示出了在Si基材料部件中制造基底的截面示意图，其中已经形成浅沟槽，限定基底。通过在单晶部件10中的沟槽15限定Si基材料基底12。在代表性实施例中，使用RIE进行沟槽蚀刻。在此RIE工艺后，基于对器件区域的隔离要求选择沟槽15的深度，如技术上已公知的，小于将在随后的湿蚀刻工艺中除去的Si基材料的量。侧壁32已经在基底12上暴露。这样取向基底31的上表面和多个侧壁32，以便基本与Si基材料部件10的晶面基本平行。在代表性实施例中，基底12上的上表面31基本平行于Si基材料部件10的{100}晶面。为了说明目的，附图示出了具有不同尺寸的两个基底12的截面图。
在可选实施例中，基底12可以不通过在部件10中形成的沟槽来限定，而是使用例如选择外延生长到Si基材料部件10上。基底12可以是Si，或具有Ge浓度高达约60％的如SiGe的Si基材料。图4示出了各种可能的实施例的结果，其中基底12位于单晶Si基材料部件10上。
图5示出了在部件10中制造基底12’的截面示意图，其中进行湿各向异性蚀刻，以及图6示出了刻面底切基底12’的截面示意图。在图中使用标号12’以表示对基底进行了各向异性湿蚀刻工艺。在图4中示意性示出的结构暴露于湿蚀刻以导致图5中示意性示出的结构。湿蚀刻溶液包括氢氧化铵(NH4OH)。已经对NH4OH的各向异性Si基材料蚀刻特性进行了研究，如S.Kudelka的题目为“Etch selectivity inversion for etching alongcrystallographic directions in silicon”的美国专利No.6,566,273中所说的，在此通过参考引入其内容。
在优选实施例中，湿蚀刻溶液为水和氢氧化铵的混合物。因为在此溶液中硅基材料晶面的各向异性蚀刻速率，侧壁32变为刻面33。
在溶液中，水和氢氧化铵(NH4OH)以约15:1和200:1之间的比率混合。对本发明的优选实施例，优选水和NH4OH的比率约为160:1。在湿蚀刻溶液中使用的水优选为去离子水(DI)。另外，在代表性实施例中，湿蚀刻溶液的水还要除气(除去溶解气体，尤其是氧)。这样的氢氧化铵/水溶液还是暴露半导体表面的极好的清洁剂。
在用水和NH4OH的各向异性蚀刻期间，在示意性实施例中湿蚀刻溶液的温度选择在25℃和70℃之间。在水-NH4OH混合液中，{111}Si基材料晶面的蚀刻速率比{100}或{110}面的典型地慢约两个数量级。
刻面33和上表面31与Si基材料部件10的晶面基本平行。刻面33在Si基材料基底12’上形成了缩小截面的第二片段20。第二片段20在第一片段30下。在图5中示出的在第一片段30的上表面31上通过介质层50和60的保护导致这样的刻面的形成，即第二片段20具有比第一片段30小的截面。这导致这样的结构，其中在第一片段30中或上寄宿的FET晶体管，由于底切刻面33，在下面没有深Si基材料。
在缩小的截面片段20中，选择掺杂剂浓度，以便此片段20导电。在此方式中，在第一片段30，寄宿FET器件和Si基材料部件10之间允许电连续。
第一片段30的底切和到Si基材料部件10的电连接有利于FET的操作。减少在此工艺中稍后形成的FET的源极和漏极的结区域，从而还减小结电容，导致更高的器件性能。另外，FET的阈值电压Vt仍可以通过使用Si基材料部件10向FET的体施加电压得到控制并且通过减小截面的第二片段20传到FET。
作为在侧壁上延伸的介质层60的结果，如首先在图3中示出的，防止沿带41湿蚀刻多个侧壁32，其中带与上表面31相接。带41的宽度由正在制造的FET器件的具体需要决定。在一些实施例中，此带41可以从制造中省略，在此情况中，刻面33和上表面31相接，或互相交叉。
如在图6中所示，未保护部件10的各向异性湿蚀刻导致在第二片段20下的基底12’上的第三片段40，第三片段40具有比第二片段20更大的截面。根据将要制造的FET的具体需要，可以省略此第三片段40，例如通过在各向异性湿蚀刻前的合适保护部件10。即使对这样的实施例，当省略第三片段40并且因为各种原因完全保护部分侧壁32不被各向异性湿蚀刻时，优选多个侧壁32的至少一个具有至少两个刻面33。
图7示出了由刻面底切基底12’寄宿的场效应器件的截面示意图。在制造刻面基底12’后，沿技术上公知的线完成器件的制造，该器件具有至少一个与基底12’相关联的FET。为了说明目的，图7示出了在先前的图中示出的两个截面，其中制造的FET器件相互垂直取向。在一个器件中，电流101的方向在截面平面内，在另一个器件中，电流102的方向垂直于截面平面。
如在图7中所示，用优选为氧化物的介质70填充沟槽15。形成栅极介质71，优选为氧化物或氧氮化物并且提供栅极导体72。还可以通过技术上公知的方法制造到源极和漏极的接触73。在完成FET的制造期间，部分部件10可以转变为如硅化物的较好的导体材料。
在电流101的方向在截面平面内的FET器件中，FET的沟道从上表面31延伸到基底12’。电流102的方向垂直于截面平面的FET器件，寄宿在与上表面31接合的半导体层79中。示出此用于说明低电容的有用性，并且通过氢氧化铵各向异性蚀刻提供的体接触包括FET的更广阔的类型。在优选实施例中，可以在工艺的某些阶段外延生长接合到上表面31的半导体层79。半导体层79本身可以是Ge层，SiGe层或III-V半导体或向整个器件结构提供一些操作优势的任何其它材料。在本发明的一些实施例中的任何基底12’第一片段30或任何附加半导体层79可以寄宿多于一个FET器件。独立地，无论FET沟道从上表面31直接延伸进入基底12’，或者FET器件寄宿在与上表面31接合的半导体层79中，FET器件都与上表面31耦合。
通过上述教导，可以进行许多本发明的修改和变化，并且对本领域的技术人员是很明显的。本发明的范围由附加权利要求限定。
Claims (20)
1.一种用于制造场效应器件的方法，包括如下步骤：
通过在单晶Si基材料部件中形成沟槽制造基底，所述基底具有上表面和多个侧壁，其中所述上表面和所述多个侧壁取向为与所述Si基材料部件的晶面平行；
用包括氢氧化铵的溶液湿蚀刻所述基底，其中因为在所述溶液中晶面的蚀刻速率不同，所述多个侧壁变为刻面，其中所述刻面在所述基底上形成减小的截面片段；以及
在所述减小的截面片段中，选择掺杂剂浓度，以使所述减小的截面片段导电，其中允许在所述场效应器件和所述Si基材料部件之间电连续，其中所述场效应器件与所述上表面耦合。
2.根据权利要求1的方法，其中所述溶液选自水和氢氧化铵的混合液。
3.根据权利要求2的方法，其中在所述混合液中，选择水和氢氧化铵的比率在15:1和200:1之间。
4.根据权利要求3的方法，其中在所述混合液中，选择水和氢氧化铵的比率为160:1。
5.根据权利要求2的方法，其中选择所述溶液的温度范围在25℃和70℃之间。
6.根据权利要求1的方法，其中所述方法还包括取向所述上表面以与所述Si基材料部件的{100}晶面平行。
7.根据权利要求1的方法，其中所述方法还包括通过用介质层覆盖所述上表面防止湿蚀刻所述上表面。
8.根据权利要求1的方法，其中所述方法还包括通过用介质层覆盖所述多个侧壁的与所述上表面相接的带以防止沿所述带湿蚀刻所述多个侧壁。
9.根据权利要求1的方法，其中所述方法还包括选择所述Si基材料部件为体晶片。
10.根据权利要求1的方法，其中所述方法还包括选择所述Si基材料部件为SOI晶片层。
11.根据权利要求1的方法，其中选择所述Si基材料部件为纯Si。
12.根据权利要求1的方法，其中所述方法还包括完成所述场效应器件的制造。
13.一种器件，包括：
单晶Si基材料的基底，所述基底包括具有上表面的第一片段，在所述第一片段下的第二片段，和多个侧壁，其中所述多个侧壁的至少一个包括至少两个刻面，其中所述刻面的每一个和所述上表面与所述基底的晶面平行，所述刻面底切所述第一片段，其中所述第二片段具有比所述第一片段小的截面，其中所述第二片段导电；
场效应器件，与所述上表面耦合；
部件，其中所述基底位于所述部件上，其中所述第二片段与所述部件和所述场效应器件电连接。
14.根据权利要求13的器件，其中所述基底还包括在所述第二片段下的第三片段，其中所述第三片段具有比所述第二片段大的截面。
15.根据权利要求13的器件，还包括与所述上表面接合的半导体层，其中所述半导体层寄宿至少一个场效应器件。
16.根据权利要求13的器件，其中所述部件是体Si晶片。
17.根据权利要求13的器件，其中所述部件是SOI晶片的Si层。
18.根据权利要求13的器件，其中通过在所述部件中形成的沟槽限定所述基底。
19.根据权利要求13的器件，其中所述上表面取向为与所述基底的{100}晶面平行。
20.根据权利要求13的器件，其中所述Si基材料为纯Si。
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