CN104752503A - 用于形成具有不同鳍高度的finfet的方法 - Google Patents
用于形成具有不同鳍高度的finfet的方法 Download PDFInfo
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- CN104752503A CN104752503A CN201410099929.4A CN201410099929A CN104752503A CN 104752503 A CN104752503 A CN 104752503A CN 201410099929 A CN201410099929 A CN 201410099929A CN 104752503 A CN104752503 A CN 104752503A
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- isolation structure
- fin
- dopant
- semiconductor device
- injection technology
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Abstract
本发明提供了用于形成半导体器件的方法的实施例。该半导体器件包括:通过第一隔离结构部分地环绕的第一鳍,并且该第一鳍伸出穿过第一隔离结构的顶面。半导体器件还包括:被通过第二隔离结构部分地环绕的第二鳍,并且该第二鳍伸出穿过第二隔离结构的顶面。第一隔离结构的顶面高于第二隔离结构的顶面,从而使第二鳍的高度高于第一鳍的高度。第二隔离结构的掺杂剂浓度大于第一隔离结构的掺杂剂浓度。本发明还提供了用于形成具有不同鳍高度的FINFET的方法。
Description
技术领域
本发明总体涉及半导体技术领域,更具体的,涉及用于形成具有不同鳍高度的FINFET的方法。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成度的不断提高,半导体产业已经历了快速的发展。在大多数情况下,这种集成度的提高源自最小部件尺寸的不断减小,这允许更多的组件被集成在给定的区域内。然而,更小的部件尺寸可以导致更多的漏电流。近来,由于对更小电子器件需求的增长,因此需要降低半导体器件中的漏电流。
所谓的鳍式场效应晶体管(FinFET)器件变得日益流行。利用称为“鳍”的较薄的鳍状结构(从衬底延伸出)制造FinFET器件,并且在鳍上方(例如,环绕)提供栅极。鳍结构由半导体材料(通常为硅)制成,并且如果用作晶体管,则鳍结构具有形成在其内部的电流沟道。因为栅极在三侧上环绕沟道区,所以FinFET提供了具有较小临界尺寸的优异的沟道控制。
发明内容
为解决现有技术中的问题,本发明提供了一种半导体器件,包括:第一鳍,由第一隔离结构部分地环绕,并且伸出穿过所述第一隔离结构的顶面;以及第二鳍,由第二隔离结构部分地环绕,并且伸出穿过所述第二隔离结构的顶面,其中,所述第一隔离结构的顶面高于所述第二隔离结构的顶面,从而使所述第二鳍的高度高于所述第一鳍的高度,并且所述第二隔离结构的掺杂剂浓度大于所述第一隔离结构的掺杂剂浓度。
在上述半导体器件中,其中,所述第二隔离结构包括至少一种掺杂剂,所述至少一种掺杂剂不包括在所述第一隔离结构中。
在上述半导体器件中,其中,所述第二隔离结构包括至少一种掺杂剂,所述至少一种掺杂剂不包括在所述第一隔离结构中;所述至少一种掺杂剂包括As、P、B、BF2、Ar、Sb、Ge、Se、N、C、H或它们的组合。
在上述半导体器件中,其中,所述第一鳍和所述第二鳍分别伸出穿过所述第一隔离结构和所述第二隔离结构的顶面,并且第一鳍和所述第二鳍的高度的差值在约5nm至约50nm的范围内。
在上述半导体器件中,其中,所述第一隔离结构与所述第二隔离结构包括相同的掺杂剂。
在上述半导体器件中,其中,所述第一隔离结构与所述第二隔离结构包括相同的掺杂剂;还包括:横跨所述第一鳍和所述第二鳍的栅极结构。
根据本发明的另一个方面,提供了一种用于形成半导体器件的方法,包括:在衬底中形成多个隔离结构,其中:通过第一隔离结构部分地环绕第一鳍;以及通过第二隔离结构部分地环绕第二鳍;对所述第二隔离结构实施第一注入工艺;对所述第一隔离结构和所述第二隔离结构实施第二注入工艺;以及对所述第一隔离结构和所述第二隔离结构实施凹槽形成工艺。
在上述方法中,其中,所述第一注入工艺包括掺杂第一掺杂剂,所述第一掺杂剂选自As、P、B、BF2、Ar、Sb、Ge、Se、N、C、H和它们的组合。
在上述方法中,其中,所述第二注入工艺包括掺杂第二掺杂剂,所述第二掺杂剂选自B、BF2、Ge、P、As、N和它们的组合。
在上述方法中,其中,所述第二注入工艺包括掺杂第二掺杂剂,所述第二掺杂剂选自B、BF2、Ge、P、As、N和它们的组合;所述第一掺杂剂与所述第二掺杂剂不同。
在上述方法中,其中,所述第一注入工艺包括以介于2E13cm-2至约1E14cm-2范围内的剂量注入第一掺杂剂。
在上述方法中,还包括:在实施所述第一注入工艺之前,形成覆盖所述第一隔离结构的图案化的光敏层。
在上述方法中,还包括:在实施所述第二注入工艺之前,去除所述图案化的光敏层。
在上述方法中,还包括:在实施所述第一注入工艺之前,形成覆盖所述第一鳍和所述第二鳍的硬掩模。
在上述方法中,还包括:在实施所述第一注入工艺之前,形成覆盖所述第一鳍和所述第二鳍的硬掩模;还包括:在实施所述第二注入工艺之前,去除所述硬掩模。
根据本发明的又一个方面,提供了一种用于形成半导体器件的方法,包括:获取其上具有多个第一鳍结构和多个第二鳍结构的衬底;形成环绕所述多个第一鳍结构的多个第一隔离结构和环绕所述多个第二鳍结构的多个第二隔离结构;在所述衬底上方形成图案化的掩模层,其中,所述图案化的掩模层覆盖所述多个第一隔离结构且露出所述多个第二隔离结构;穿过所述图案化的掩模层实施第一注入工艺,以将第一掺杂剂注入所述多个第二隔离结构;去除所述图案化的掩模层;实施第二注入工艺以将第二掺杂剂注入所述多个第一隔离结构和所述多个第二隔离结构;对所述多个第一隔离结构和所述多个第二隔离结构实施凹槽形成工艺,以露出所述多个第一鳍结构和所述多个第二鳍结构的一部分。
在上述方法中,还包括:在实施所述第一注入工艺之前,形成覆盖所述多个第一鳍结构和所述多个第二鳍结构的另一个图案化的掩模层。
在上述方法中,还包括:在实施所述第一注入工艺之后,实施退火工艺。
在上述方法中,其中,所述凹槽形成工艺包括化学氧化物去除。
在上述方法中,其中,在所述凹槽形成工艺期间,所述多个第二隔离结构的蚀刻速率高于所述多个第一隔离结构的蚀刻速率。
附图说明
为了更完全地理解本发明及其优势,现结合附图来参考以下描述,其中:
图1是根据一些实施例的示出了用于形成FinFET器件的方法的流程图。
图2A至图11A和图2B至图11B分别是根据各个实施例的在制造FinFET器件的中间阶段的透视图和截面图。
图12和图13是根据一些实施例的在制造FinFET器件的中间阶段的截面图。
具体实施方式
以下详细论述了本发明实施例的制造和使用。然而,应该理解,实施例可以体现在各种具体环境中。所论述的具体实施例仅是说明性的,且不用于限制本发明的范围。
应当理解,为了实施本发明的不同特征,以下公开内容提供了许多不同的实施例或实例。在下面描述部件和布置的特定实例以简化本发明。当然这些仅仅是实例且并不用于限定。此外,在下面的描述中,在第二工艺之前实施第一工艺可以包括在第一工艺之后直接实施第二工艺的实施例,并且也可以包括可以在第一工艺和第二工艺之间实施额外工艺的实施例。为了简明和清楚,可以以不同比例任意绘制各个部件。此外,在说明书中,在第二部件上方或上形成第一部件可以包括其中第一部件和第二部件以直接或间接接触的方式形成的实施例。
本文描述了实施例的一些变化例。在各个视图和示例性实施例中,相似的参考标号用于表示相似的元件。应当理解,可以在方法之前、期间、和之后提供额外的步骤,并且对于方法的其他实施例,可以代替或删除所描述的一些步骤。
本文提供了用于形成半导体器件的方法的实施例。还应当注意的是,本发明呈现了多栅极晶体管或鳍式多栅极晶体管(本文中称为FinFET器件)的形式的实施例。FinFET器件可以是双栅极器件、三栅极器件和/或其他配置。FinFET器件可以包括在诸如微处理机、存储器件和/或其他IC的IC中。
图1是根据一些实施例的示出了用于形成半导体器件的方法100的流程图。方法100开始于操作102,其中,提供了具有第一鳍结构和第二鳍结构的衬底。方法100继续至操作104,其中,在衬底上方形成第一隔离结构和第二隔离结构。由第一隔离结构部分地环绕第一鳍结构,并且由第二隔离结构部分地环绕第二鳍结构。方法100继续至操作106,其中,对第二隔离结构施加第一注入工艺。方法100继续至操作108,其中,对第一隔离结构和第二隔离结构均施加第二注入工艺。方法100继续至操作110,对第一隔离结构和第二隔离结构施加凹槽形成工艺,从而使第一鳍结构和第二鳍结构分别伸出穿过第一隔离结构和第二隔离结构的顶面。
应当注意的是,图1的方法不能生产完整的FinFET器件。可以使用互补金属氧化物半导体(CMOS)技术工艺制造完整的FinFET器件。因此,可以在图1的方法100之前、期间和之后提供额外的工艺,并且本文中仅简要描述了一些其他工艺。同样,简化图1至图11B以更好地理解本发明的构思。
图2A至图10A和图2B至图10B分别是根据一些实施例的FinFET器件200在中间制造阶段的透视图和截面图。在图2A至图10B中,沿着以标号“A”结尾的视图中示出的截面线a-a来截取以标号“B”结尾的视图。此外,沿着图11A中示出的截面线b-b来截取图11B。
在图2A和图2B示出的中间制造阶段中,在衬底204上形成诸如光刻胶等的图案化的光敏层202。图案化的光敏层202形成在硬掩模206的顶部上,而硬掩模206又位于焊盘氧化物208的顶部,焊盘氧化物208又位于衬底204的顶部。硬掩模206可以是氮化硅、氮氧化硅等。焊盘氧化物208可以是氧化硅等。
衬底204可以是诸如块状硅晶圆的块状衬底。可选地,衬底204可以简单地为化合物晶圆的顶部半导体层,诸如绝缘体上硅衬底。在又一些其他实施例中,衬底204可以是块状衬底或化合物晶圆的顶层。化合物晶圆可以包括Ge、SiGe、SiC、Ⅲ-Ⅴ族材料(诸如GaAs、InAs、GaP、InP或InSb)、Ⅱ-Ⅵ族材料(诸如ZeSe或ZnS)等。据了解,Ⅲ-Ⅴ族或Ⅱ-Ⅵ族族材料可能特别有利于形成所示的器件,这是因为通过使用Ⅲ-Ⅴ族或Ⅱ-Ⅵ族材料可以得到有益的应变特性。衬底204可以具有第一区域204a和第二区域204b,其中,将在第一区域204a中形成标准阈值电压的FinFET,并且在随后的工艺中,将在第二区域中形成低阈值电压的FinFET。
如图3A和3B所示(其中,图3A是图2A的透视图的继续且图3B是图2B的截面图的继续),通过使用任何合适的蚀刻工艺,将图案化的光敏层202的图案转印到硬掩模206、焊盘氧化物208和衬底204内。在这个图案转印工艺期间,如图3A和图3B所示,可以完全消耗掉图案化的光敏层202。在一些实施例中,未完全消耗掉图案化的光敏层202,并通过例如氧等离子体或所谓的灰化工艺去除图案化的光敏层202的剩余部分。
产生的结构包括形成在衬底204中的一些鳍结构。例如,在第一区域204a中形成第一鳍结构210a,并且在第二区域中形成第二鳍结构210b。在一些实施例中,鳍结构210a和210b的每个鳍均具有侧壁,侧壁的一部分基本上垂直于衬底204的主表面204s。在一些实施例中,侧壁的下部不与衬底204的主表面204s垂直。在一些实施例中,将衬底204蚀刻至深度D,深度D是指从鳍结构210a和210b的顶面至衬底204的主表面204s的距离,深度D为从约40nm至约80nm。应当注意的是,说明书中的视图示出了FinFET器件200仅包括4个鳍,这只是一个实例。可以有许多修改、替代、和变化。例如,根据不同的应用和需要,FinFET器件200可以容纳任意数量的鳍。
图4A和图4B根据一些实施例示出了制造工艺中的下一个阶段,在衬底204中和衬底204上沉积隔离结构。例如,隔离结构可以包括第一区域204a中的第一隔离结构212a和第二区域204b中的第二隔离结构212b。在一些实施例中,第一隔离结构212a和第二隔离结构212b中的每个的顶面均低于硬掩模206的顶部。在一些实施例中,将第一隔离结构212a和第二隔离结构212b称为浅沟槽隔离件(STI)。第一隔离结构212a和第二隔离结构212b可由诸如氧化硅、高密度等离子体(HDP)氧化物、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃、低k介电材料、和/或其他合适的绝缘材料的介电材料制成。可以通过诸如CVD、亚大气压CVD、高密度等离子体CVD(HDPCVD)、旋涂玻璃法等的合适的沉积技术来沉积第一隔离结构212a和第二隔离结构212b。可选择地且在形成隔离结构212a和212b之前,可以对鳍结构210a和210b进行热氧化以修复蚀刻步骤期间发生的任何对侧壁的损害(如图3A和图3B中所示)。在一些实施例中,施加化学机械抛光(CMP)工艺来将第一隔离结构212a和第二隔离结构212b削薄至硬掩模206的顶部的水平,并且选择性地施加蚀刻工艺以进一步将第一隔离结构212a和第二隔离结构212b削薄至低于硬掩模206的顶部的点。
接下来,如图5A和图5B所示,根据一些实施例,在衬底204的第一区域204a上方形成诸如光刻胶的图案化的掩模层214。在一些实施例中,掩模层214至少覆盖第一鳍结构210a。在一些实施例中,掩模层214覆盖第一隔离结构212a和第一鳍结构210a。仍然暴露第二隔离结构212b。图案化的掩模层214可以由诸如聚苯并恶唑(PBO)、SU-8-光敏环氧化物、薄膜型高分子材料等的合适的光刻胶材料形成。
接下来,如图6A和图6B所示,根据一些实施例,对第二隔离结构212b施加第一注入工艺216。第一注入工艺216可以包括实施一次或多次注入以将第一掺杂剂掺杂至第二隔离结构212b内。在一些实施例中,第一注入工艺216包括仅实施一次注入。在一些实施例中,第一注入工艺216包括仅实施两次注入(利用不同的掺杂剂)。可选地,第一注入工艺216包括实施三次或多次注入(利用不同的掺杂剂)。第一掺杂剂可以包括一种或多种掺杂剂,诸如As、P、B、BF2、Ar、Sb、Ge、Se、N、C、H、或它们的组合。在第一注入工艺216期间,由图案化的掩模层214保护第一隔离结构212a,并且由硬掩模206保护第一鳍结构210a和第二鳍结构210b。第一注入工艺216的剂量可以在从约2E13cm-2至约1E14cm-2的范围内。可以在从约3kV至约10kV的能量水平范围内实施第一注入工艺216。在一些实施例中,在第一注入工艺216之后,通过诸如灰化工艺的合适的技术去除图案化的掩模层214。
接下来,参考图7A和图7B,根据一些实施例去除硬掩模206和焊盘氧化物208。通过合适的蚀刻工艺和CMP工艺去除硬掩模206和焊盘氧化物208。可以实施CMP工艺直到暴露出第一鳍结构210a和第二鳍结构210b。
接下来,参考图8A和图8B,根据一些实施例,对第一区域204a和第二区域204b均施加第二注入工艺218。第二注入工艺218可以包括将第二掺杂剂掺杂至第一隔离结构212a和第二隔离结构212b以及鳍结构210a和210b内。当FinFET器件200的鳍结构210a和210b中需要P阱(未示出)时,第二掺杂剂可以包括诸如B、BF2、Ge等的p型掺杂剂。可选地,当FinFET器件200的鳍结构210a和210b中需要N阱时,第二掺杂剂可以包括诸如P、As、N等的n型杂质。根据不同的设计需求和应用,可以改变第二掺杂剂。在一些实施例中,第二掺杂剂与第一掺杂剂相同或不同。第二注入工艺218的剂量可以在从2E13cm-2至约1E14cm-2的范围内。在一些实施例中,可以在从约3kV至约10kV的能量水平范围内实施第二注入工艺218。第二注入工艺218可以包括实施用于将第二掺杂剂掺杂至第一隔离结构212a和第二隔离结构212b内的一次或多次注入。在一些实施例中,第二注入工艺218包括仅实施一次注入。在一些实施例中,第二注入工艺218包括仅实施两次注入(利用不同的掺杂剂)。在一些实施例中,第二注入工艺218包括实施三次或多次注入(利用不同的掺杂剂)。
在产生的结构中,仅通过第二注入工艺218注入第一隔离结构212a,而通过第一注入工艺216及第二注入工艺218注入第二隔离结构212b。第二隔离结构212b具有比第一隔离结构212a更高的掺杂剂浓度。在一些实施例中,第二隔离结构212b包括第一掺杂剂,而第一掺杂剂不包括在第一隔离结构212a中。因此,第一隔离结构212a和第二隔离结构212b的蚀刻速率不同。在一些实施例中,由于存在第一掺杂剂,因此第二隔离结构212b的蚀刻速率高于第一隔离结构212a的蚀刻速率。在单独的凹槽形成工艺期间,这种蚀刻速率的差异有助于实现不同的鳍高度。
尽管前文描述了通过将第一掺杂剂注入第二隔离结构212b来实现蚀刻速率的差异,但是也可以通过其他方式来实现蚀刻速率的差异。例如,根据实施例,也可以通过在第一注入工艺216中将能够降低蚀刻速率的其他掺杂剂注入第一隔离结构212a来实现蚀刻速率的差异。
在如图8A和图8B所示的注入工艺之后,可以实施退火工艺以增加第二掺杂剂的注入深度。退火工艺可以是快速热退火(RTA)工艺、毫秒退火(MSA)工艺、激光退火工艺等。在一些实施例中,退火温度为从约600摄氏度至约1300摄氏度的范围内。
接下来,参考图9A和图9B,根据一些实施例,在第一隔离结构212a和第二隔离结构202b上实施凹槽形成工艺以进一步削薄它们。因此,第一区域204a中的第一鳍结构210a伸出穿过第一隔离结构212a的顶面,并且,第二区域204b中的第二鳍结构210b伸出穿过第二隔离结构212b的顶面。可以以多种方式削薄第一隔离结构212a和第二隔离结构212b。在一些实施例中,使用东京电子CERTAS、应用材料SICONI工具等,通过化学氧化物去除来削薄第一隔离结构212a和第二隔离结构212b。可选地,在合适的时间内,通过稀氢氟酸(DHF)处理或蒸汽氢氟酸(VHF)处理来削薄第一隔离结构212a和第二隔离结构212b。在一些实施例中,稀HF酸是HF与水的混合物(1:100)。
应该注意的是,由于蚀刻速率的差异,第一隔离结构212a和第二隔离结构212b的凹槽深度不同,这导致了第一鳍结构210a和第二鳍结构210b的伸出部分的高度不同。如图9A和图9B所示,每个第一鳍结构210a具有从第一鳍结构210a的顶面至第一隔离结构212a的顶面测量的鳍高度H1,鳍高度H1为从约30nm至约50nm的范围内或约36nm。每个第二鳍结构210b具有从第二鳍结构210b的顶面至第二隔离结构212b的顶面测量的鳍高度H2、鳍高度H2为从约35nm至约100nm的范围内。在一些实施例中,鳍高度H1与鳍高度H2之间的差值为约5nm至约50nm的范围内。
沟道宽度(指鳍高度的两倍加上鳍结构的顶面的厚度T)影响器件性能,诸如影响产生的FinFET的阈值电压和驱动电流。换言之,通过调节鳍高度可以调整阈值电压和驱动电流。与包括第一鳍结构210a的FinFET相比,产生的包括第二鳍结构210b的FinFET可以具有更低的阈值电压和更大的驱动电流。
此外,根据前文的描述,通过单独的蚀刻步骤(诸如图9A和图9B所示的凹槽形成工艺)可以实现鳍高度的差异。这种用于实现不同鳍高度的单独的蚀刻步骤有助于进一步降低制造FinFET器件的成本。
接下来,参考图10A和图10B,根据一些实施例,在第一鳍结构210a和第二鳍结构210b上方形成栅极结构220。栅极结构220可以包括栅极介电层222、栅电极层224、和/或一个或多个附加层。在一些实施例中,栅极结构220是牺牲栅极结构,诸如在替代栅极工艺中形成的以用于形成金属栅极结构。在一些实施例中,栅极结构220包括多晶硅层(诸如栅电极层224)。
栅极介电层222可包括二氧化硅。可以通过合适的氧化和/或沉积方法形成二氧化硅。可选地,栅极介电层222可以包括高k介电层,诸如氧化铪(HfO2)。可选地,高k介电层可以可选择地包括其他高k电介质,诸如LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3、BaTiO3、BaZrO、HfZrO、HfLaO、HfTaO、HfSiO、HfSiON、HfTiO、LaSiO、AlSiO、(Ba,Sr)TiO3、Al2O3、或其他合适的高k介电材料、它们的组合、或其它合适的材料。可以通过原子层沉积(ALD)、CVD、金属有机化学汽相沉积(MOCVD)、物理汽相沉积(PVD)、等离子体增强化学汽相沉积(PECVD)、等离子体增强原子层沉积(PEALD)、它们的组合、和其他合适的技术形成高k介电层。
接下来,参考图11A和图11B,根据一些实施例,形成轻掺杂的漏极/源极(LDD/S)区域226、口袋区域228、栅极间隔件230和源极/漏极(S/D)区域232。在一些实施例中,还形成密封层234。在一些实施例中,通过LDD注入和口袋注入分别形成LDD/S区域226和口袋区域228。在靠近鳍结构210a和210b的顶面以及靠近栅电极层224的位置形成LDD/S区域226,并且口袋区域比LDD/S区域226更深。可以朝着鳍结构210a和210b的侧壁倾斜并实施LDD/S注入和口袋注入。在一些实施例中,LDD/S注入和口袋注入掺杂不同类型的掺杂剂。口袋区域也可以帮助调整阈值电压和驱动电流。
相比于LDD/S注入,口袋注入需要更大的倾斜角度,但是有时通过鳍结构的鳍高度或整体高度以及光刻胶(如果需要光刻胶)对其进行遮蔽(shadowed)。在一些实施例中,由于已经可以通过改变鳍高度来调整阈值电压和驱动电流,因此不形成口袋区域。
在一些实施例中,在形成LDD/S区域226之后,形成密封层234、栅极间隔件230和重掺杂区域232。在一些实施例中,密封层234覆盖栅电极层224的侧壁和LDD/S区域226。在一些实施例中,栅极间隔件230覆盖密封层234。接下来,将栅极间隔件230用作掩模,通过对鳍结构210a和210b实施比LDD/S注入更重且更深的注入来形成重掺杂区域232。
在11A和图11B中,第一区域204a和第二区域204b之间的分割边界位于鳍结构210a和鳍结构210b之间,然而,这仅仅是一个实例。例如,根据一些实施例,图12和13分别示出了FinFET器件200的中间制造阶段的截面图。在图12中,第一区域204a和第二区域204b之间的分割边界与鳍结构210a对准或对齐,并且通过鳍结构210a分离第一隔离结构212a和第二隔离结构212b。在图13中,第一区域204a和第二区域204b之间的分割边界与鳍结构210b对准或对齐,并且通过鳍结构210b分离第一隔离结构212a和第二隔离结构212b。在一些实施例中,第一区域204a和第二区域204b之间的分割边界与鳍结构210a或210b的侧壁或侧面对准或对齐。
本文提供了用于形成FinFET器件的方法的实施例。通过调整掺杂剂浓度和/或掺杂剂类型可以使隔离结构具有不同的蚀刻速率。因此可以通过单独的凹槽形成工艺实现不同的鳍高度。通过调整鳍高度,FinFET在每个特定区域中可以具有期望的阈值电压和驱动电流。从而提高了器件性能。
在一些实施例中,提供了一种半导体器件。该半导体器件包括:通过第一隔离结构部分地环绕的第一鳍,并且该第一鳍伸出穿过第一隔离结构的顶面。半导体器件还包括:通过第二隔离结构部分地环绕的第二鳍,并且该第二鳍伸出穿过第二隔离结构的顶面。第一隔离结构的顶面高于第二隔离结构的顶面,从而使第二鳍的高度高于第一鳍的高度。第二隔离结构的掺杂剂浓度大于第一隔离结构的掺杂剂浓度。
在一些实施例中,提供了一种用于形成半导体器件的方法。该方法包括:在衬底中形成多个隔离结构。通过第一隔离结构部分地环绕第一鳍;以及通过第二隔离结构部分地环绕第二鳍。该方法也包括:对第二隔离结构施加第一注入工艺。该方法还包括:对第一隔离结构和第二隔离结构实施第二注入工艺。此外,该方法包括:对第一隔离结构和第二隔离结构实施凹槽形成工艺。
在一些实施例中,提供了一种用于形成半导体器件的方法。该方法包括:在衬底中形成多个隔离结构。通过第一隔离结构部分地环绕第一鳍;以及通过第二隔离结构部分地环绕第二鳍。该方法也包括:对第二隔离结构实施第一注入工艺。该方法还包括:对第一隔离结构和第二隔离结构实施第二注入工艺。此外,该方法包括:对第一隔离结构和第二隔离结构实施凹槽形成工艺。
在一些实施例中,提供了一种用于形成半导体器件的方法。该方法包括:提供其上具有多个第一鳍结构和多个第二鳍结构的衬底。该方法也包括:形成环绕多个第一鳍结构的多个第一隔离结构和环绕多个第二鳍结构的多个第二隔离结构。该方法还包括:在衬底上方形成图案化的掩模层。图案化的掩模层覆盖多个第一隔离结构且暴露多个第二隔离结构。此外,该方法包括:穿过图案化的掩模层实施第一注入工艺以将第一掺杂剂掺杂至多个第二隔离结构。而且,该方法包括:去除图案化的掩模层。该方法还包括:实施第二注入工艺以将第二掺杂剂掺杂至多个第一隔离结构和多个第二隔离结构。该方法还包括:分别对多个第一隔离结构和多个第二隔离结构施加凹槽形成工艺以暴露多个第一鳍结构和多个第二鳍结构的一部分。
尽管已经详细地描述了本发明的实施例及其优势,但应该理解,在不背离所附权利要求所限定的本发明的精神和范围的情况下,可做出各种改变、替代和变化。例如,本领域普通技术人员将容易理解,可以改变本文所述的多个特征、功能、工艺和材料而仍然保持在本发明的范围内。而且,本申请的范围不旨在限于本说明书中所述的工艺、机器、制造、物质组成、工具、方法和步骤的具体实施例。本领域的技术人员将容易从本发明理解,根据本发明,可以利用现有的或今后将开发的、与本发明所述相应实施例实施基本相同的功能或者实现基本相同的结果的工艺、机器、制造、物质组成、工具、方法或步骤。因此,所附权利要求旨在将这些工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。
Claims (10)
1.一种半导体器件,包括:
第一鳍,由第一隔离结构部分地环绕,并且伸出穿过所述第一隔离结构的顶面;以及
第二鳍,由第二隔离结构部分地环绕,并且伸出穿过所述第二隔离结构的顶面,其中,所述第一隔离结构的顶面高于所述第二隔离结构的顶面,从而使所述第二鳍的高度高于所述第一鳍的高度,并且所述第二隔离结构的掺杂剂浓度大于所述第一隔离结构的掺杂剂浓度。
2.根据权利要求1所述的半导体器件,其中,所述第二隔离结构包括至少一种掺杂剂,所述至少一种掺杂剂不包括在所述第一隔离结构中。
3.根据权利要求2所述的半导体器件,其中,所述至少一种掺杂剂包括As、P、B、BF2、Ar、Sb、Ge、Se、N、C、H或它们的组合。
4.根据权利要求1所述的半导体器件,其中,所述第一鳍和所述第二鳍分别伸出穿过所述第一隔离结构和所述第二隔离结构的顶面,并且第一鳍和所述第二鳍的高度的差值在约5nm至约50nm的范围内。
5.根据权利要求1所述的半导体器件,其中,所述第一隔离结构与所述第二隔离结构包括相同的掺杂剂。
6.根据权利要求5所述的半导体器件,还包括:横跨所述第一鳍和所述第二鳍的栅极结构。
7.一种用于形成半导体器件的方法,包括:
在衬底中形成多个隔离结构,其中:
通过第一隔离结构部分地环绕第一鳍;以及
通过第二隔离结构部分地环绕第二鳍;
对所述第二隔离结构实施第一注入工艺;
对所述第一隔离结构和所述第二隔离结构实施第二注入工艺;以及
对所述第一隔离结构和所述第二隔离结构实施凹槽形成工艺。
8.根据权利要求7所述的方法,其中,所述第一注入工艺包括掺杂第一掺杂剂,所述第一掺杂剂选自As、P、B、BF2、Ar、Sb、Ge、Se、N、C、H和它们的组合。
9.根据权利要求8所述的方法,其中,所述第二注入工艺包括掺杂第二掺杂剂,所述第二掺杂剂选自B、BF2、Ge、P、As、N和它们的组合。
10.一种用于形成半导体器件的方法,包括:
获取其上具有多个第一鳍结构和多个第二鳍结构的衬底;
形成环绕所述多个第一鳍结构的多个第一隔离结构和环绕所述多个第二鳍结构的多个第二隔离结构;
在所述衬底上方形成图案化的掩模层,其中,所述图案化的掩模层覆盖所述多个第一隔离结构且露出所述多个第二隔离结构;
穿过所述图案化的掩模层实施第一注入工艺,以将第一掺杂剂注入所述多个第二隔离结构;
去除所述图案化的掩模层;
实施第二注入工艺以将第二掺杂剂注入所述多个第一隔离结构和所述多个第二隔离结构;
对所述多个第一隔离结构和所述多个第二隔离结构实施凹槽形成工艺,以露出所述多个第一鳍结构和所述多个第二鳍结构的一部分。
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US9184087B2 (en) | 2015-11-10 |
TW201539746A (zh) | 2015-10-16 |
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KR20150077366A (ko) | 2015-07-07 |
DE102014118863B4 (de) | 2018-05-09 |
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US9559011B2 (en) | 2017-01-31 |
TWI543365B (zh) | 2016-07-21 |
US20170140980A1 (en) | 2017-05-18 |
DE102014118863A1 (de) | 2015-07-02 |
US9842761B2 (en) | 2017-12-12 |
US20180102278A1 (en) | 2018-04-12 |
CN104752503B (zh) | 2018-01-26 |
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