CN103208517B - 控制FinFET结构中的鳍状件高度 - Google Patents

控制FinFET结构中的鳍状件高度 Download PDF

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CN103208517B
CN103208517B CN201210546428.7A CN201210546428A CN103208517B CN 103208517 B CN103208517 B CN 103208517B CN 201210546428 A CN201210546428 A CN 201210546428A CN 103208517 B CN103208517 B CN 103208517B
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semiconductor fin
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CN103208517A (zh
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莫亦先
陈筱筑
江木吉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种器件，该器件包括衬底、在所述衬底的顶面的隔离区，以及在所述隔离区上方的半导体鳍状件。半导体鳍状件具有小于大约的鳍状件高度，其中鳍状件高度从半导体鳍状件的顶面到隔离区的顶面测量得到。本发明还公开了控制FinFET结构中的鳍状件高度。

Description

控制FinFET结构中的鳍状件高度
技术领域
本发明涉及半导体技术领域，更具体地，涉及控制FinFET结构中的鳍状件高度。
背景技术
随着日益缩减的集成电路尺寸以及日益增长的对集成电路速度的需求，晶体管需要具有较小的尺寸并且具有较高的驱动电流。因此开发了鳍式场效应晶体管(FinFET)。FinFET晶体管具有增大的沟道宽度。通过形成包括鳍状件侧壁上的部分和鳍状件顶面上的部分的沟道实现沟道宽度的增大。由于晶体管的驱动电流与沟道宽度成比例，因此增大了FinFET的驱动电流。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种器件，包括：
衬底；
在所述衬底的顶面的隔离区；以及
在所述隔离区上方的第一半导体鳍状件，其中所述第一半导体鳍状件具有小于约的鳍状件高度，并且其中所述鳍状件高度从所述第一半导体鳍状件的顶面到所述隔离区的顶面测量得到。
在可选实施方式中，所述器件进一步包括与所述第一半导体鳍状件间隔开的第二半导体鳍状件，所述隔离区在所述第一半导体鳍状件和所述第二半导体鳍状件之间，其中所述第一半导体鳍状件的边缘和所述第二半导体鳍状件的边缘与所述隔离区的相对边缘大体对准。
在可选实施方式中，所述第一半导体鳍状件和所述第二半导体鳍状件具有小于约的距离。
在可选实施方式中，所述鳍状件高度与所述距离的比值小于约13。
在可选实施方式中，所述器件进一步包括：第一栅极介电层；在所述第一栅极介电层上方的第一金属层；以及在所述第一金属层上方的第一多晶硅层，其中所述第一栅极介电层、所述第一金属层以及所述第一多晶硅层在所述第一半导体鳍状件的顶面和侧壁上延伸。
在可选实施方式中，所述器件进一步包括：第二栅极介电层；在所述第二栅极介电层上方的第二金属层；以及在所述第二金属层上方的第二多晶硅层，其中所述第二栅极介电层、所述第二金属层以及所述第二多晶硅层与所述第一半导体鳍状件间隔开，并且在所述隔离区的部分上方而且覆盖所述隔离区的所述部分。
在可选实施方式中，所述隔离区和所述第二多晶硅层的最近边缘的多晶硅至OD间距大于约
在可选实施方式中，所述器件进一步包括在所述第一半导体鳍状件下方并且连接所述第一半导体鳍状件的半导体带，其中所述半导体带的边缘接触所述隔离区的边缘，并且其中所述半导体带和所述第一半导体鳍状件由相同的半导体材料形成。
根据本发明的另一个方面，还提供了一种器件，包括：
半导体衬底；
与所述半导体衬底的表面邻接的浅沟槽隔离(STI)区；
第一半导体带和第二半导体带，所述第一半导体带和所述第二半导体带包括接触所述STI区的相对侧壁的侧壁；
第一半导体鳍状件和第二半导体鳍状件，分别在所述第一半导体带和所述第二半导体带上方并且邻接所述第一半导体带和所述第二半导体带，其中所述第一半导体鳍状件和所述第二半导体鳍状件的鳍状件高度小于约
在可选实施方式中，所述第一半导体鳍状件和所述第二半导体鳍状件具有小于约的距离。
在可选实施方式中，所述器件进一步包括：第一栅极介电层；在所述第一栅极介电层上方的第一金属层；以及在所述第一金属层上方的第一多晶硅层，其中所述第一栅极介电层、所述第一金属层以及所述第一多晶硅层在所述第一半导体鳍状件的顶面和侧壁上延伸。
在可选实施方式中，所述器件进一步包括：在所述STI区上方的第二栅极介电层；在所述第二栅极介电层上方的第二金属层；以及在所述第二金属层上方的第二多晶硅层，其中所述第二栅极介电层、所述第二金属层以及所述第二多晶硅层在所述第一半导体鳍状件和所述第二半导体鳍状件之间并且与所述第一半导体鳍状件和所述第二半导体鳍状件间隔开。
在可选实施方式中，所述第一半导体带和所述第二半导体带以及所述第一半导体鳍状件和所述第二半导体鳍状件由相同的半导体材料形成。
根据本发明实施例的又一个方面，还提供了一种方法，包括：
在半导体衬底中形成浅沟槽隔离(STI)区，其中在所述STI区的相对侧的所述半导体衬底的部分形成半导体带；以及
对所述STI区开槽以形成凹槽，其中所述半导体带的上端部分形成第一半导体鳍状件和第二半导体鳍状件，所述第一半导体鳍状件和所述第二半导体鳍状件具有小于约的鳍状件高度，并且其中所述鳍状件高度从所述第一半导体鳍状件和所述第二半导体鳍状件的顶面到所述STI区的顶面测量得到。
在可选实施方式中，所述方法进一步包括：在所述STI区以及所述第一半导体鳍状件和所述第二半导体鳍状件上方形成栅极介电层；在所述栅极介电层上方形成金属层；在所述金属层上方形成多晶硅层；以及图案化所述多晶硅层、所述金属层以及所述栅极介电层以形成在所述第一半导体鳍状件的顶面和侧壁上的第一堆叠件以及在所述STI区的部分上方并且覆盖所述STI区的所述部分的第二堆叠件。
在可选实施方式中，在所述图案化步骤之后，没有所述多晶硅层、所述金属层和所述栅极介电层的残留物残存在所述STI区上方，并且其中所述多晶硅层、所述金属层和所述栅极介电层的相对应边缘彼此对准。
在可选实施方式中，所述第二堆叠件不接触所述第一半导体鳍状件和所述第二半导体鳍状件。
在可选实施方式中，所述第一鳍状件和所述第二鳍状件具有小于约的距离。
在可选实施方式中，所述鳍状件高度与所述距离的比值小于约13。
在可选实施方式中，所述方法进一步包括形成包括所述第一半导体鳍状件的鳍式场效应晶体管(FinFET)。
附图说明
为更完整地理解实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1至图7是根据各种示例性实施方式的在制造鳍式场效应晶体管(FinFET)相关结构过程中的中间阶段的剖视图和透视图。
图8和图9示出了实验结果。
具体实施方式
下面详细讨论了公开的实施方式的制造和使用。然而，应当理解所述实施方式提供了可体现在各种各样具体情形中的很多可应用的发明概念。所讨论的具体实施方式仅是示例说明，并不限制本发明的范围。
根据各种实施方式提供了鳍式场效应晶体管(FinFET)相关结构及其形成方法。示例了形成FinFET的中间阶段。讨论了实施方式的变形。贯穿各视图和示例性实施方式，相似的标号被用于指代相似元件。
图1至图7是根据一些示例性实施方式的在制造FinFET相关结构过程中的中间阶段的剖视图和透视图。图1示出了初始结构的透视图。初始结构包括衬底20。衬底20可以为半导体衬底，半导体衬底可以进一步为硅衬底，硅锗衬底，硅碳衬底或者由其他半导体材料形成的衬底。衬底20可以掺杂p型或者n型杂质。隔离区，诸如浅沟槽隔离(STI)区22可以形成在衬底20中。STI区22的宽度W可以小于大约并且可以小于大约相邻STI区22之间的衬底20部分形成半导体带21。
参照图2，通过蚀刻步骤对STI区22开槽。因而，部分半导体带21在剩余的STI区22的顶面上方。此后，在剩余的STI区22的顶面上方的半导体带21的部分称为半导体鳍状件。因此，半导体鳍状件24在其之间具有STI区22，并且半导体鳍状件24的边缘大体上与相对应的STI区22的边缘对准。在一些实施方式中，鳍状件24的高度H小于约并且可以小于约在半导体鳍状件24下的半导体带21部分具有接触STI区22边缘的边缘。此外，半导体带21和半导体鳍状件24可以由相同的半导体材料形成。
参照图3A和图3B，介电层28形成在鳍状件24的顶面和侧壁上。图3A示出了透视图。图3B示出了沿图3A中剖面线3B-3B获得的剖视图。根据一些实施方式，介电层28包括氧化硅，氮化硅，或者它们的多层。在可选的实施方式中，介电层28由高k介电材料形成，因此在整个说明书中可选地称为高k介电层28。高k介电层28可以具有大于大约7.0的k值，并且可包括Hf，Al，Zr，La，Mg，Ba，Ti，Pb的氧化物或者硅化物，以及它们的组合。高k介电层28的示例性材料包括MgOx，BaTixOy，BaSrxTiyOz，PbTixOy，PbZrxTiyOz等等，其中值x，y和z在0和1之间。然而，本领域技术人员将会意识到整个说明书详述的尺寸仅是例子，并且可以变为不同的值。介电层28的形成方法可包括分子束沉积(MBD)，原子层沉积(ALD)，物理气相沉积(PVD)等等。
在介电层28上方形成覆盖层30。在一些实施方式中，覆盖层30可以为含金属的层，并因此可以有时称为金属层30。根据一些实施方式，覆盖层30可以含有氮化钛(TiN)。在可选的实施方式中，覆盖层30的示例性材料包括含钽材料和/或含钛材料，例如，TaC，TaN，TaAlN，TaSiN，TiN，TiAl，Ru，以及它们的组合。
图4A和图4B分别示出了多晶硅层32和硬掩模层34形成的透视图和剖视图。图4B中示出的剖视图沿图4A中剖面线4B-4B获得。首先，沉积多晶硅层32，接着进行化学机械抛光(CMP)以将多晶硅层32的顶面变平。然后，在多晶硅层32上方形成硬掩模层34。硬掩模层34可以由诸如氮化硅形成，然而也可以使用其他材料，例如氧化硅。
在图5中，硬掩模层34被图案化，并且硬掩模层34的剩余部分包括硬掩模图案34A和34B。为了图案化硬掩模层34，首先可以形成并且图案化光刻胶36；然后图案化的光刻胶36被用作蚀刻掩模以图案化硬掩模层34。然后去除图案化光刻胶36。硬掩模图案34A在部分鳍状件24上方，并且硬掩模图案34B在部分STI区22上。
接着，如图6A中所示，硬掩模图案34A和34B被用作蚀刻掩模以蚀刻下面的多晶硅层32，覆盖层30以及介电层28。结果，在鳍状件24上方形成栅堆叠件40，并且在STI区22上方形成堆叠层42。栅堆叠件40包括多晶硅层32A，金属层30A以及介电层28A。堆叠层42包括多晶硅层32B，金属层30B以及介电层28B。栅堆叠件40还可形成在鳍状件24的侧壁上，如由虚线指示的。在一些实施方式中，在堆叠层42的侧壁上基本上没有留下介电层28，金属层30，以及多晶硅层30B的残留物，因此多晶硅层32B、金属层30B以及介电层28B的边缘可以大体为平直和垂直的，并且可以大体彼此对准。然而，在一些情况下，栅极介电层28、金属层30以及多晶硅层28的残留物可能不期望地留在了STI区22上方。图6B中示出了最后得到的结构。发现是否形成有残留物可受鳍状件24的鳍状件高度H影响。当鳍状件高度H小于约时，不形成残留物。然而，当鳍状件高度H大于约时，残留物开始形成，并且鳍状件高度H越大，可以发现越多的残留物。残留物在6B中示意性地示出为29。根据一些实施方式，为了形成无残留物的结构，鳍状件高度H可以小于约并且可进一步小于约在这些实施方式中，通过将鳍状件高度控制为小于临界值栅极介电层28、金属层30以及多晶硅层32的残留物基本上可从STI区22上方消除。
实验结果指示出鳍状件高度H对残存在沟槽45中的残留物的量具有显著影响。图8示出了从样本晶圆获得的实验结果，其中在沟槽45中残留物的高度H’(图6)示出为鳍状件高度H的函数。沟槽45是在被开槽的STI区22上方并且在相邻鳍状件24之间的空间部分。实验结果是出人意料的，因为当鳍状件高度小于大约时，残留物的高度H’基本上等于并且基本上没有残留物留下。然而，当鳍状件高度大于大约时，残留物的高度H’很快增长。
实验结果还指示出poly至OD的间距S1(图6B)也对残存在沟槽45中的残留物的量有影响。图9示出了从样本晶圆获得的实验结果，并且绘制了拟合线(fitline)，其中沟槽45中的残留物的高度H’(图6)示出为鳍状件高度H的函数。实验结果指示当poly至OD的间距S1大于约时，残留物的高度H’基本上等于并且基本上没有残留物留下。因此，根据实施方式，poly至OD的间距S1大于大约
应当进一步理解，STI区22的宽度W也对是否会形成残留物有影响。值得注意的是宽度W也是相邻鳍状件24之间的间距，根据一些实施方式，STI区22的宽度W可以小于约沟槽45的H/W纵宽比可以小于约13，并且还可以小于约5。
图6C示出了图6A中示出的结构的透视图。为了清楚示出多晶硅带32B后面的结构，多晶硅带32B示出为透明的。图6C示出了栅堆叠件40在鳍状件24上方并且横跨鳍状件24。堆叠层42在相邻鳍状件24之间并且与鳍状件24间隔开。
在后续步骤中，如图7所示，硬掩模图案34A和34B被去除。在后续步骤中，还如图7所示，形成了FinFET60，其中栅堆叠件40用作FinFET60的栅堆叠件。堆叠层42可用作伪图案，并且其是电浮置的。可选地，堆叠层42可在器件之间起电连接作用。例如，堆叠层42可在两个FinFET(未示出)的栅极之间起电连接作用。
FinFET60可包括栅极间隔件62，源极和漏极区64，硅化物区66，接触塞68以及层间电介质(ILD)70。在一些实施方式中，源极和漏极区64的形成还可包括蚀刻鳍状件24的没有被栅堆叠件40覆盖的部分，并且进行外延以生长应激物(stresstor)(未示出，应激物可以为硅锗或者硅碳)。然后，应激物被注入以形成源极和漏极区64。在可选的实施方式中，鳍状件24没有被开槽，并且可实施外延以在鳍状件24上生长外延区以扩大源极和漏极区64。在通过注入形成源极和漏极区64时，堆叠层42也可以被注入以降低阻抗。
根据实施方式，一种器件包括衬底，在衬底的顶面的隔离区，以及在隔离区上方的半导体鳍状件。半导体鳍状件具有小于约的鳍状件高度，其中鳍状件高度从半导体鳍状件的顶面到隔离区的顶面测量得到。
根据其他实施方式，一种器件包括半导体衬底，与半导体衬底的表面邻接的STI区，以及包括与STI区侧壁相对接触的侧壁的第一半导体带和第二半导体带。器件还包括在第一半导体带和第二半导体带上方并且分别连接第一半导体带和第二半导体带的第一半导体鳍状件和第二半导体鳍状件。第一半导体鳍状件和第二半导体鳍状件的鳍状件高度小于约
根据又一些其他实施方式，一种方法包括在半导体衬底中形成STI区，其中STI区相对侧的半导体衬底的部分形成半导体带。方法还包括对STI区开槽以形成凹槽。半导体带的上端部分形成第一和第二半导体鳍状件，所述第一和第二半导体鳍状件具有小于约的鳍状件高度，其中鳍状件高度从第一半导体鳍状件和第二半导体鳍状件的顶面到STI区的顶面测量得到。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员通过本公开内容将容易理解，现有的或今后开发的用于实现与在此描述的相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在它们的范围内。此外，每项权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (20)

1.一种半导体器件，包括：
衬底；
在所述衬底的顶面的隔离区；以及
在所述隔离区上方的第一半导体鳍状件，其中所述第一半导体鳍状件具有小于的鳍状件高度，并且其中所述鳍状件高度从所述第一半导体鳍状件的顶面到所述隔离区的顶面测量得到；
堆叠层，所述堆叠层覆盖在所述隔离区上，并且与所述第一半导体鳍状件间隔开。
2.如权利要求1所述的器件，进一步包括与所述第一半导体鳍状件间隔开的第二半导体鳍状件，所述隔离区在所述第一半导体鳍状件和所述第二半导体鳍状件之间，其中所述第一半导体鳍状件的边缘和所述第二半导体鳍状件的边缘与所述隔离区的相对边缘大体对准。
3.如权利要求2所述的器件，其中所述第一半导体鳍状件和所述第二半导体鳍状件具有小于的距离。
4.如权利要求3所述的器件，其中所述鳍状件高度与所述距离的比值小于13。
5.如权利要求1所述的器件，进一步包括：
第一栅极介电层；
在所述第一栅极介电层上方的第一金属层；以及
在所述第一金属层上方的第一多晶硅层，其中所述第一栅极介电层、所述第一金属层以及所述第一多晶硅层在所述第一半导体鳍状件的顶面和侧壁上延伸。
6.如权利要求5所述的器件，进一步包括：
第二栅极介电层；
在所述第二栅极介电层上方的第二金属层；以及
在所述第二金属层上方的第二多晶硅层，其中所述第二栅极介电层、所述第二金属层以及所述第二多晶硅层与所述第一半导体鳍状件间隔开，并且在所述隔离区的部分上方而且覆盖所述隔离区的所述部分。
7.如权利要求6所述的器件，其中所述隔离区和所述第二多晶硅层的最近边缘的多晶硅至OD间距大于
8.如权利要求1所述的器件，进一步包括在所述第一半导体鳍状件下方并且连接所述第一半导体鳍状件的半导体带，其中所述半导体带的边缘接触所述隔离区的边缘，并且其中所述半导体带和所述第一半导体鳍状件由相同的半导体材料形成。
9.一种半导体器件，包括：
半导体衬底；
与所述半导体衬底的表面邻接的浅沟槽隔离(STI)区；
第一半导体带和第二半导体带，所述第一半导体带和所述第二半导体带包括接触所述浅沟槽隔离区的相对侧壁的侧壁；
第一半导体鳍状件和第二半导体鳍状件，分别在所述第一半导体带和所述第二半导体带上方并且邻接所述第一半导体带和所述第二半导体带，其中所述第一半导体鳍状件和所述第二半导体鳍状件的鳍状件高度小于
堆叠层，所述堆叠层覆盖在所述浅沟槽隔离区上，并且位于所述第一半导体鳍状件和所述第二半导体鳍状件之间以及与所述第一半导体鳍状件和所述第二半导体鳍状件间隔开。
10.如权利要求9所述的器件，其中所述第一半导体鳍状件和所述第二半导体鳍状件具有小于的距离。
11.如权利要求9所述的器件，进一步包括：
第一栅极介电层；
在所述第一栅极介电层上方的第一金属层；以及
在所述第一金属层上方的第一多晶硅层，其中所述第一栅极介电层、所述第一金属层以及所述第一多晶硅层在所述第一半导体鳍状件的顶面和侧壁上延伸。
12.如权利要求9所述的器件，进一步包括：
在所述浅沟槽隔离区上方的第二栅极介电层；
在所述第二栅极介电层上方的第二金属层；以及
在所述第二金属层上方的第二多晶硅层，其中所述第二栅极介电层、所述第二金属层以及所述第二多晶硅层在所述第一半导体鳍状件和所述第二半导体鳍状件之间并且与所述第一半导体鳍状件和所述第二半导体鳍状件间隔开。
13.如权利要求9所述的器件，其中所述第一半导体带和所述第二半导体带以及所述第一半导体鳍状件和所述第二半导体鳍状件由相同的半导体材料形成。
14.一种形成半导体器件的方法，包括：
在半导体衬底中形成浅沟槽隔离(STI)区，其中在所述浅沟槽隔离区的相对侧之间的所述半导体衬底的部分形成半导体带；以及
对所述浅沟槽隔离区开槽以形成凹槽，其中所述半导体带的上端部分形成第一半导体鳍状件和第二半导体鳍状件，所述第一半导体鳍状件和所述第二半导体鳍状件具有小于的鳍状件高度，并且其中所述鳍状件高度从所述第一半导体鳍状件和所述第二半导体鳍状件的顶面到所述浅沟槽隔离区的顶面测量得到；
在所述浅沟槽隔离区上方覆盖堆叠层，所述堆叠层位于所述第一半导体鳍状件和所述第二半导体鳍状件之间并且与所述第一半导体鳍状件和所述第二半导体鳍状件间隔开。
15.如权利要求14所述的方法，进一步包括：
在所述浅沟槽隔离区以及所述第一半导体鳍状件和所述第二半导体鳍状件上方形成栅极介电层；
在所述栅极介电层上方形成金属层；
在所述金属层上方形成多晶硅层；以及
图案化所述多晶硅层、所述金属层以及所述栅极介电层以形成在所述第一半导体鳍状件的顶面和侧壁上的第一堆叠件以及在所述浅沟槽隔离区的部分上方并且覆盖所述浅沟槽隔离区的所述部分的第二堆叠件。
16.如权利要求15所述的方法，其中在所述图案化步骤之后，没有所述多晶硅层、所述金属层和所述栅极介电层的残留物残存在所述浅沟槽隔离区上方，并且其中所述多晶硅层、所述金属层和所述栅极介电层的相对应边缘彼此对准。
17.如权利要求15所述的方法，其中所述第二堆叠件不接触所述第一半导体鳍状件和所述第二半导体鳍状件。
18.如权利要求15所述的方法，其中所述第一半导体鳍状件和所述第二半导体鳍状件具有小于的距离。
19.如权利要求18所述的方法，其中所述鳍状件高度与所述距离的比值小于13。
20.如权利要求15所述的方法，进一步包括形成包括所述第一半导体鳍状件的鳍式场效应晶体管(FinFET)。
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