WO2015149705A1 - 一种鳍型半导体结构及其成型方法 - Google Patents

一种鳍型半导体结构及其成型方法 Download PDF

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WO2015149705A1
WO2015149705A1 PCT/CN2015/075721 CN2015075721W WO2015149705A1 WO 2015149705 A1 WO2015149705 A1 WO 2015149705A1 CN 2015075721 W CN2015075721 W CN 2015075721W WO 2015149705 A1 WO2015149705 A1 WO 2015149705A1
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fin portion
region
sacrificial
fin
substrate
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PCT/CN2015/075721
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English (en)
French (fr)
Inventor
李迪
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唐棕
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Priority claimed from CN201410135439.5A external-priority patent/CN103928521B/zh
Priority claimed from CN201410135438.0A external-priority patent/CN103915504B/zh
Priority claimed from CN201410135448.4A external-priority patent/CN103904122B/zh
Priority claimed from CN201420163556.8U external-priority patent/CN203895466U/zh
Application filed by 唐棕 filed Critical 唐棕
Priority to US15/301,464 priority Critical patent/US20170179275A1/en
Publication of WO2015149705A1 publication Critical patent/WO2015149705A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Definitions

  • the present invention relates to the field of semiconductor design and its manufacturing technology, and in particular to a fin-type semiconductor structure and a molding method thereof.
  • the FinFET is called a Fin Field-Effect Transistor FinFET and is a new complementary metal oxide semiconductor (CMOS) transistor. Fin is the meaning of fins.
  • CMOS complementary metal oxide semiconductor
  • FinFET is named according to the shape of the transistor and the fin similarity. Other similar names include Tri-gate MOS.
  • FinFET is an innovative design derived from the current standard field-effect transistor (Field-Effect Transistor FET). Gates that control the passage of current in a conventional transistor structure can only control the turn-on and turn-off of the circuit on one side of the gate, which is a planar architecture. In the FinFET architecture, the gates form a fork-like 3D architecture resembling a fin, which controls the switching on and off of the circuit on both sides of the circuit. This design improves circuit control and significantly reduces transistor gate length compared to conventional transistors.
  • Field-Effect Transistor FET Field-Effect Transistor FET
  • the present invention proposes a fin-type semiconductor structure and a method of fabricating the same.
  • the fin-type semiconductor structure provided by the invention can further reduce the leakage current between the source and drain regions, enhance the control capability of the gate electrode, effectively improve the performance of the semiconductor device, and prolong the life.
  • the fin-type semiconductor structure includes: a fin substrate having a lower substrate and a fin portion; formed on the fin a source region and a drain region on the sheet portion; a gate structure formed on the fin portion between the source region and the drain region, and a fin portion under the gate structure is a channel; formed on the fin Shallow trench isolation on both sides of the sheet; and one or more isolation regions formed in the fin portion between the channel and the lower substrate.
  • the cross section of the fin portion may be a rectangle or a triangle, and the top surface of the fin portion may be a smooth curved surface.
  • the fin-type semiconductor structure may include an interlayer dielectric layer on both sides of the gate structure, the interlayer dielectric layer having a height flush with the gate structure.
  • the isolation region may be located below the source region and/or the drain region, or may be located below the gate structure, equal to or less than the length of the gate structure.
  • the semiconductor structure includes a sacrificial region formed in a fin portion, the isolation region being formed in the sacrificial region, the sacrificial region being exposed from both sides of the fin portion.
  • the sacrificial region may be a sacrificial layer extending through the fin portion or may be one or more sacrificial blocks.
  • the fin portion includes an upper fin portion, a sacrificial region, and a lower fin portion.
  • the material of the upper fin portion may be Si, and the surface of the fin portion may have a SiGe epitaxial layer.
  • the material of the upper fin portion may be SiGe, and the surface of the fin portion has a Si epitaxial layer.
  • there may be a Si epitaxial layer.
  • Both sides of the isolation region may have a back-cut region, and the back-cut region is retracted with respect to both sides of the fin portion by a distance less than a quarter of the width of the fin portion.
  • the present invention also provides a method of forming a fin-type semiconductor structure, comprising:
  • Step A providing a substrate to form a fin substrate having a lower substrate and a fin portion, the fin portion including a sacrificial region;
  • Step B etching part or all of the sacrificial regions to form a cavity, and filling the cavity with an insulating material to form an isolation region;
  • Step C forming a dummy gate structure spanning the fin portion and forming sidewall spacers on both sides of the dummy gate structure, and forming source and drain regions on the fin portions on both sides of the dummy gate structure;
  • Step D replacing the dummy gate structure with a gate replacement process to form a metal gate structure.
  • the step A may include: providing a substrate having a sacrificial region in the substrate, the sacrificial region being a sacrificial layer extending through the entire substrate;
  • a substrate performing ion implantation on the substrate to form a sacrificial region, wherein the sacrificial region is one or more sacrificial blocks;
  • Forming an etch barrier layer on the substrate forming a mask on the etch barrier layer, etching the etch barrier layer to expose a portion of the substrate, etching the substrate to form a fin portion, and the fin portion has an upper portion a fin portion, a sacrificial layer, and a lower fin portion.
  • the step A may include: etching to form a fin portion, a cross section of the fin portion at both ends is a rectangle, or a cross section of the fin portion at both ends is a triangle.
  • the method may further include etching a cavity in the fin portion below the drain region and/or the source region; or etching all or a portion of the sacrificial region below the gate structure to form a cavity.
  • a step of epitaxially growing a SiGe epitaxial layer on the surface of the fin portion and the cavity, or epitaxially growing a Si epitaxial layer on the surface of the fin portion and the cavity may be included. And, it may further include epitaxially growing the Si epitaxial layer outside the SiGe epitaxial layer.
  • the isolation region is subjected to a back-cut process to form a back-cut region, and the dummy gate structure formed in the step C covers the surface of the back-cut region and surrounds the inside of the fin portion. .
  • FIGS. 1 to 11 are schematic diagrams showing intermediate steps of a method of fabricating a fin-type semiconductor device according to an embodiment of the present invention
  • FIG. 11 is a schematic structural view of a semiconductor device formed in an embodiment of the present invention.
  • FIG. 12 is a schematic structural view of another fin substrate in an embodiment of the present invention.
  • Figure 13 is a schematic structural view showing another cavity forming layout in the embodiment of the present invention.
  • Figure 14 is a schematic structural view of a back-cut area in an embodiment of the present invention.
  • 15 is a schematic structural view showing formation of a SiGe layer and a Si layer on a fin portion and a cavity surface in an embodiment of the present invention
  • FIG. 16 is a schematic structural view of a semiconductor device in which sidewall spacers are formed in Embodiment 3 of the present invention.
  • FIG. 17 is a schematic structural view of a semiconductor device in which an interlayer dielectric layer is formed in Embodiment 3 of the present invention.
  • FIG. 18 is a schematic view showing a semiconductor structure in which a dummy gate structure is removed in Embodiment 3 of the present invention.
  • FIG. 19 is a schematic view showing a semiconductor structure in which an isolation region and a gate structure are formed in Embodiment 3 of the present invention.
  • the orientation of the device of the present invention is defined such that the direction in which the fin portion protrudes from the substrate is the z direction, the direction perpendicular to the z direction and parallel to the top end of the fin portion is the x direction, perpendicular to x, The direction of the z direction is the y direction.
  • FIGS. 1-11 are schematic diagrams of intermediate steps of the method.
  • FIGS. 1-11 are schematic diagrams of intermediate steps of the method.
  • Step A providing a substrate 100 including a sacrificial region on which a fin substrate 100 having a lower substrate 180 and a fin portion 110 is formed, the sacrificial region 113 being in the fin portion, referring to FIG. Shown.
  • a substrate 100 is provided.
  • the substrate 100 includes a first substrate 101, which may be made of silicon, and then epitaxially grown on the first substrate.
  • 101 A sacrificial region 113 is formed thereon.
  • the sacrificial region 113 is a sacrificial layer 113 extending through the entire substrate.
  • the material of the sacrificial layer 113 is preferably SiGe, n-type doped silicon or the like, and the thickness is preferably 5 to 50 nm.
  • the growth continues on the sacrificial layer 113, for example, epitaxially growing the second substrate 102, which becomes the basis of the upper fin portion 114 of the fin portion 110 formed in the subsequent processing step, thereby forming A substrate 100 including a sacrificial region 113.
  • the material of the sacrificial layer 113 may be SiGe having a Ge content of 40%
  • the material of the second substrate 102 may be Si
  • the second substrate 102 is SiGe having a Ge content slightly lower than that of the sacrificial layer, preferably It is SiGe with a Ge content lower than 10% lower than the sacrificial layer.
  • the second substrate 102 can be formed using different materials depending on the performance requirements of the formed device.
  • the second substrate 102 can be silicon; for PMOS, the second substrate 102 is preferably silicon germanium, wherein the Ge content can be 30%.
  • the structure in which the second substrate is formed of a SiGe material can improve the mobility of carrier holes in the PMOS device, improve channel performance, and enhance gate control.
  • an etch stop layer 900 is formed on the surface of the substrate 100.
  • the etch stop layer 900 can have various options.
  • an oxide layer 901 can be deposited, for example, 10-200 nm, and a nitride layer 902 is formed on the oxide layer 901, for example, 10 At -200 nm, an etch stop layer 900 is formed. Referring to FIG.
  • a mask having a width in the y direction is formed on the etch barrier layer 900 to protect a portion of the etch barrier layer 900, the certain width being determined by the width of the top surface of the fin portion in the y direction, for example, preferably.
  • the etch layer 900 of the nitride layer 902 and the oxide layer 901 is selectively etched to form a structure as shown in FIG. 4, exposing a portion of the upper surface of the substrate 100.
  • the substrate 100 is etched by etching the barrier layer 900 as a barrier to form the fin portion 110 as shown in FIG.
  • the fin portion 110 has an upper fin portion 114, a sacrificial layer 113 and a lower fin portion 112 penetrating the fin portion, as shown in FIG.
  • the second substrate 102 forms the upper fin portion 114
  • a portion of the first substrate 101 forms the lower fin portion 112.
  • the lower substrate 180 and the fin portion 110 constitute a fin substrate 100.
  • the shape of the fin portion 110 can be selected as needed, and controlled by an etching process and parameters, for example, a fin portion 110 having a rectangular cross section at both ends can be formed, as shown in FIG. It is also possible to form the fin portion 210 having a triangular cross section at both ends, as shown in FIG.
  • the material of the upper fin portion 114 and the material of the lower fin portion 112 may be the material Si, or the material of the upper fin portion 114 may be With SiGe preferably having a Ge content of 30%, the material of the lower fin portion 112 is Si.
  • the upper fin portion 114 and the lower fin portion 112 may be formed of other materials depending on the performance requirements of the device to be formed, and those skilled in the art may select and change these materials as needed, which are all protected by the present invention. Within the scope.
  • the fin portion top surface 111 may be rounded so that the fin portion top surface 111 has a rounded curved surface as shown in FIG. Its function is that it can reduce the local electric field strength of the device and enhance the reliability of the device.
  • the smoothing method can be performed by isotropic etching or annealing at 700 degrees Celsius or more in a hydrogen atmosphere.
  • step B etching a portion of the sacrificial layer 113 to form the cavity 200, and filling the cavity 200 with an insulating material to form the isolation region 300 and the shallow trench isolation 105.
  • a photoresist is uniformly coated on the surface of the fin portion 110, and the sacrificial layer 113 and the fin portion 110 to be retained are masked with a mask to expose the sacrificial layer 113 where the cavity 200 needs to be formed.
  • the exposed portion of the photoresist is exposed, and after the exposed photoresist is washed away, the exposed sacrificial layer 113 is etched.
  • a cavity 200 penetrating the y-axis direction is formed between the upper fin portion 114 and the lower fin portion 112 as shown in FIG.
  • the height of the cavity 200 in the z direction may be 5-50 nm.
  • the material of the sacrificial layer 113 is composed of silicon germanium, if the cavity 200 is too high, that is, the sacrificial layer 113 is too thick, defects such as dislocations may be generated in the silicon germanium sacrificial layer 113, and the defect is likely to extend. And enter the upper channel region, so that the performance of the device is deteriorated. Therefore, the height of the cavity 200 is preferably 5-20 nm.
  • dry and/or wet mixed etches can be used to etch cavity 200.
  • the dry etching can better control the shape and size of the cavity to form a relatively small cavity 200.
  • the last etching process for etching the cavity 200 should be wet etching.
  • the photoresist on the surface of the fin portion 110 is removed.
  • one or more cavities 200 of different lengths may be formed at different positions in the x direction, as shown in FIG. 13, forming the first cavity 2001 and the second space. Cavity 2002.
  • the number, location, and size of the cavities 200 can be selected based on the performance requirements of forming the device.
  • the device When the cavity 200 is located only inside the fin portion under the source region 6002 or the drain region 6001, the device has a good isolation effect, and the thermal conductivity and mechanical strength of the device structure on the side where the cavity 200 is not formed is better because the upper fin
  • the slice portion 114 is connected by the sacrificial layer 113 and the lower fin portion 112, sacrificing
  • the layer 113 such as silicon germanium, has a higher thermal conductivity than the isolation region 300 filled in the cavity, such as silicon oxide; and its mechanical strength is higher than that of forming the cavity 200 and then backfilling the isolation region 300. Since the sacrificial layer 113 and the upper fin portion 114 and the lower fin portion 112 are integrally formed, the bonding is tight.
  • a cavity 200 having a relatively short length in the x direction may be formed when a device having higher mechanical strength and better thermal conductivity is formed, and a plurality of voids may be formed in the sacrificial layer when it is desired to obtain a device having better isolation effect. Cavity 200.
  • the mechanical properties of the device may decrease.
  • the length of the short cavity 200 in the x direction should be less than 4 times the width of the fin portion 110 in the y direction.
  • the different locations of the cavities in the device can have different effects on the performance of the device, including the following:
  • the cavity 200 is etched into the fin portion below the location where the drain region 6001 is located.
  • the sacrificial layer 113 is still present in the source region 6002 and the fin portion under the dummy gate structure, and the sacrificial layer 113 is connected to the upper fin portion 114 and the lower fin portion 112.
  • the structure has better thermal conductivity and higher mechanical strength.
  • the leakage current of the drain region 6001 is reduced due to the isolation between the drain region 6001 and the substrate.
  • the cavity 200 is etched into the fin portion under the drain region 6001 and a portion of the dummy gate structure. This structure can reduce the parasitic capacitance between the gate and the substrate under the fin while reducing the leakage current of the drain region 6001.
  • the length of the cavity in the x direction can be equal to the length of the dummy gate structure.
  • the length of the cavity in the x direction is smaller than the length of the gate structure. This structure has an excellent short channel effect and can effectively reduce leakage current between the source region 6002 and the drain region 6001 through the dummy gate structure.
  • the edge of the cavity 200 and the edge of the top surface 111 of the fin portion are rounded, and the method of smoothing may be isotropic etching or An annealing method of 700 degrees Celsius or more in a hydrogen atmosphere.
  • This step causes the top portion 111 of the upper fin portion 114 to have a rounded surface as shown in FIG.
  • the lower surface of the upper fin portion 114 can also be processed into a rounded curved surface.
  • the effect of the smoothing process is that it can reduce the local electric field strength of the device and enhance the reliability of the device.
  • the upper fin portion 114 may form a substantially rectangular parallelepiped structure or a cylinder having rounded corners by rounding the edge of the cavity 200. Shape structure. If the degree of the smoothing process is small, the upper fin portion 114 forms a substantially rectangular parallelepiped structure having rounded corners, and if the degree of the rounding treatment is large, the upper fin portion 114 forms a substantially cylindrical structure.
  • the cavity 200 is filled with an insulating material to form an isolation region 300.
  • the insulating material may be SiO 2 , HfO 2 or the like.
  • the insulating material should continue to be filled to form a shallow trench isolation (STI) 105, as shown in FIG.
  • the upper surface of the shallow trench isolation 105 is higher than the top end 111 of the fin portion.
  • chemical mechanical planarization is performed to expose the upper surface of the fin portion.
  • the shallow trench isolation is etched to expose the fin portion 110, and the etching stops at the upper surface of the isolation region 300. A portion of the isolation region 300 can be exposed, as shown in FIG.
  • the fin portion 110 may be thermally oxidized prior to filling the insulating material.
  • the surface of the fin portion is SiO 2 formed by thermal oxidation treatment, thereby narrowing or even closing the cavity 200.
  • the remaining cavity and fin portion 110 should be filled with an insulating material to form a complete isolation region 300 and shallow trench isolation 105.
  • Thermal oxidation can provide a good surface quality to the lower surface of the upper fin portion so as not to affect the mobility of carriers in the fin.
  • the isolation region 300 should be exposed from both sides of the fin portion 110 in the y direction, as shown in FIG. Thereafter, the isolation region 300 can be subjected to a back-cutting process.
  • the isolation region is a silicon dioxide material
  • wet etching is performed with hydrofluoric acid to etch a portion of the isolation region 300
  • an undercut region 301 is formed on both sides of the isolation region along the y direction, as shown in FIG. Show.
  • the retraction zone 301 is retracted in the y direction relative to both sides of the fin portion by a distance less than a quarter of the width of the fin portion 110 in the y direction, thus maintaining the mechanical stability of the fin.
  • the gate structure may cover the surface of the back-cut region 301 and surround the inside of the fin portion in the y direction, covering the lower end of the upper fin portion 114. Part of the surface. This structure can enhance the gate control, reduce the short channel effect, effectively enhance the gate control strength, and greatly improve the device. performance.
  • the SiGe layer and the Si layer may be formed by epitaxial growth on the fin portion 110 after the sacrificial layer is formed into the cavity 200.
  • the SiGe epitaxial layer may be epitaxially grown on the surface of the fin portion 110 and the cavity 200, and the Si epitaxial layer may be epitaxially grown on the SiGe epitaxial layer, as shown in FIG. Show.
  • a Si epitaxial layer (not shown) may be epitaxially grown on the surface of the fin portion 110 and the cavity 200.
  • the thickness of the Si epitaxial layer is less than 5 nm, it is more suitable for fabricating a PMOS semiconductor device.
  • the thin Si epitaxial layer can form compressive stress on the underlying SiGe epitaxial layer or the SiGe upper fin portion, thereby improving the hole mobility of the SiGe and improving the channel performance in the PMOS device.
  • the thickness of the Si epitaxial layer is thicker, it is more suitable for fabricating an NMOS device, and the Si epitaxial layer has a better surface state, and the electrons therein are carriers in the NMOS device.
  • the fins be silicon and have good etch selectivity when the silicon germanium is a sacrificial layer. Epitaxial growth of silicon germanium and silicon may be sequentially performed in the region of the PMOS fin after the cavity is formed.
  • the shallow trench isolation (STI) 105 may be formed by filling an insulating material, and then chemical mechanical planarization is performed to expose the upper surface of the fin portion.
  • the shallow trench isolation is then etched to expose the fin portion 110, and the etch stops at a position where a portion of the sacrificial region 200 is exposed. Thereafter, an etching and filling step is performed from the exposed sacrificial region 200 to form an isolation region 300.
  • step C forming a dummy gate structure spanning over the fin portion 110, the fin portion under the dummy gate structure is a channel 106, and is formed on the fin portions 110 on both sides of the dummy gate structure 400 in the y direction. Source and drain areas.
  • high-k dielectric materials such as yttrium oxide, nitride, and the like may be deposited on the fin portion 110, and a dummy gate spanning over the fin portion is formed over the shallow trench isolation 105.
  • the excess high-k dielectric material is etched to form a dummy gate structure 400, as shown in FIG.
  • the spacer 500 is formed, and a nitride is deposited on the fin portion 110 and the dummy gate structure 400 to form a nitride layer.
  • the nitride layer on the fin portion 110 and the top of the dummy gate structure 400 is etched to form sidewall spacers 500 on both sides of the dummy gate structure 400 along the x-direction, as shown in FIG.
  • ion implantation is performed on the fin portions on both sides of the dummy gate structure 400 in the x direction, thereby forming a source region. 6002 and drain region 6001, as shown in FIG. Further, before the formation of the source region and the drain region, a step of performing ion implantation to form a source-drain extension region may be further included.
  • Step D forming a gate structure by replacing the dummy gate structure with a gate replacement process.
  • the substrate 100 in order to facilitate mass production in a factory, generally has a relatively large length in the x direction, that is, a long substrate is provided. Therefore, preferably, the structural characteristics of a single device, the length in the x direction, and the number, position, and size of the isolation regions 300 can be pre-designed, and the steps A and B are completed on the substrate 100 having a large length.
  • the device that has formed isolation region 300 and shallow trench isolation 105 is then truncated in the x direction according to a pre-designed device length to form a separate device. Then, the processing of steps C and D is performed. The step of cutting off is independent of the steps of forming the cavity and the isolation zone.
  • Step A Providing a substrate 100 including a sacrificial region 113 on which a fin substrate 100 having a lower substrate 180 and a fin portion 110 is formed, the sacrificial region 113 being inside the fin portion.
  • the sacrificial region 113 is not a sacrificial layer penetrating the fin portion but appears as one or more sacrificial blocks 113.
  • the manner in which the sacrificial block 113 is formed may be performed in a process of preparing the substrate 100.
  • a substrate 100 is provided, and a mask is formed at a position where the surface of the substrate 100 needs to be protected, thereby exposing the need to form the sacrificial block 113.
  • a region having a certain concentration is formed in the substrate 100, that is, the sacrificial region 113 is formed.
  • a fin portion 110 is formed, which is a sacrificial block 113 distributed over one or more regions in the substrate.
  • the sacrificial region is one or more regions located in the fin portion 110.
  • Step B Etching part or all of the sacrificial regions to form a cavity, and filling the cavity with an insulating material to form an isolation region and shallow trench isolation.
  • the edge of the formed cavity 200 may be rounded according to the performance requirements of the device to etch part or all of the sacrificial block 113, and the SiGe epitaxial layer and/or Si epitaxial layer may be epitaxially grown on the surface of the fin portion 110 and the cavity 200.
  • the cavity 200 is filled with silicon dioxide or other insulating material to form isolation regions 300 and shallow trench isolations 105.
  • Step C forming a dummy gate structure 400 over the fin portion over the shallow trench isolation 105, and the fin portion under the dummy gate structure is a channel 106 formed on the fin portions on both sides of the dummy gate structure 400 A source region 6002 and a drain region 6001.
  • Step D forming a gate structure by replacing the dummy gate structure with a gate replacement process.
  • the step of etching the portion of the sacrificial region 113 to form the cavity 200 is immediately after the step of providing the sinker 100, that is, the etching step is the step B.
  • the present invention also provides a processing method for etching the sacrificial region 113 after removing the dummy gate structure. Specifically, after performing step A, perform the following steps:
  • Step B filling the fin portion 110 with an isolation material to form a shallow trench isolation (STI) 105, and the insulating material may be SiO 2 , HfO 2 , or the like.
  • the upper surface of the shallow trench isolation 105 is higher than the top surface 111 of the fin portion.
  • chemical mechanical planarization is performed to expose the upper surface of the fin portion.
  • the shallow trench isolation is then etched to expose the fin portion 110 and a portion of the sacrificial region 200 therein.
  • Step C forming a dummy gate structure spanning over the fin portion 110, the fin portion under the dummy gate structure is a channel, and source regions and drains are formed on the fin portions 110 on both sides of the dummy gate structure 400 in the y direction. Area.
  • spacers 500 are formed on both sides of the dummy gate structure 400 along the x direction, over the fin portions 110, as shown in FIG.
  • An interlayer dielectric layer 600 is formed on both sides of the side wall 500 in the x direction.
  • the interlayer dielectric layer 600 completely covers the fin portions 110 that are not covered by the dummy gate structure 400 and the sidewall spacers 500.
  • the height of the interlayer dielectric layer 600 may be flush with the height of the dummy gate structure 400, as shown in FIG.
  • the material of the interlayer dielectric layer may be SiO 2 .
  • step D as shown in FIG. 18, first, selectively etching the dummy gate structure 400
  • the entire dummy gate structure 400 is etched away to expose the fin portion 110 and the sacrificial region 113 which are originally covered by the dummy gate structure and inside the side wall 500.
  • the shallow trench isolation 105 on the inner side of the side wall 500 may be etched such that the shallow trench isolation 105 etches down a small portion in the z direction to expose the sacrificial region 113.
  • the exposed sacrificial region 113 is etched away by an etching technique.
  • a portion of the sacrificial region directly under the pseudo gate structure can be etched, or the inner side of the etched sidewall and all the sacrificial directly below the dummy gate structure can be etched.
  • the region forms a cavity 200.
  • the sacrificial area 113 exposed in this manner is located between the side walls 500, so that the cavity 200 formed after etching the exposed sacrificial area 113 is located between the side walls 500. Thereafter, the cavity 200 is filled with an insulating material to form an isolation region 300.
  • step E is performed to form a gate structure 410 inside the side walls 500, as shown in FIG.
  • the sacrificial region is a sacrificial layer extending through the entire fin portion, all of the sacrificial regions in the fin portion 110 may be etched away, and the cavity extends through the entire fin portion.
  • An advantage of the method of the third embodiment is the self-alignment of the isolation regions.
  • Those skilled in the art can form the isolation region just below the gate structure without performing special positioning and alignment steps.
  • This structure has an excellent short channel effect and can effectively reduce leakage current between the source region and the drain region through the gate structure.
  • the entire sacrificial region can be etched by the method of the third embodiment without causing the problem that the upper fin portion collapses and falls off. Because the interlayer dielectric layer has been formed above the upper fin portion before etching the sacrificial region, the bonding force between the interlayer dielectric layer and the upper fin portion can provide sufficient for the upper fin portion.
  • Stability even if all of the sacrificial or sacrificial layers under the upper fin portion are etched, can remain at the original position.
  • those skilled in the art can use a substrate having a sacrificial layer and employ the molding method of the third embodiment.
  • the present invention also proposes a fin-type semiconductor device structure.
  • the device has a fin substrate 100 including a lower substrate 180 and a fin portion 110, and a source region 6002 on the fin portion 110.
  • the drain region 6001, the source region 6002 and the drain region 6001 span the gate structure on the fin portion 110.
  • the mark 400 is a dummy gate structure, and after the gate replacement process is completed, the gate structure will replace the position of the dummy gate structure 400.
  • the fin portion under the gate structure is a channel, a shallow trench isolation 105 on both sides of the fin portion 110 in the y direction and below the gate structure, side walls 500 on both sides of the gate structure along the x direction, and formation An isolation region between the channel and the lower substrate in the fin portion 110 300.
  • the fin-type semiconductor device may further include an interlayer dielectric layer on both sides of the side wall 500 in the x direction.
  • the fin portion 110 may include an upper fin portion 114, a sacrificial region 113, and a lower fin portion 112.
  • the top surface of the fin portion 110 preferably has a width of 1-10 nm, and the cross-section of the fin portion may be a rectangle, as shown in FIG. 6, or a triangle. As shown in FIG. 12, the top surface may be a smooth curved surface.
  • the fin portion having a triangular cross section at both ends has better mechanical stability, and the fin portion having a rectangular cross section at both ends forms a device and the grid control is better.
  • the upper fin portion 114 may be a rectangular parallelepiped structure or a cylindrical structure having rounded corners. If the degree of the smoothing process is small, the upper fin portion 114 forms a substantially rectangular parallelepiped structure having rounded corners, and if the degree of the rounding treatment is large, the upper fin portion 114 forms a substantially cylindrical structure.
  • the height of the isolation region is preferably 5-20 nm, and the material of the isolation region may be SiO 2 and/or HfO 2 .
  • the upper surface of the shallow trench isolation 105 may be lower than the upper surface of the isolation region 300. When the upper surface of the shallow trench isolation 105 is lower than the upper surface of the isolation region 300, the gate structure can be covered more in the z direction, which can reduce leakage current, enhance driving current and enhance gate control.
  • the sacrificial region 113 is exposed from both sides of the fin portion 110 in the y direction.
  • the isolation region 300 is formed in the sacrificial region 113.
  • the sacrificial region 113 may be a sacrificial layer that penetrates the fin portion 110 or is one or more sacrificial blocks.
  • the material of the lower fin portion 112 may be Si, the material of the sacrificial region 113 is SiGe, and the material of the upper fin portion 114 is Si.
  • the material of the lower fin portion 112 may be Si, the material of the sacrificial region 113 is SiGe, and the material of the upper fin portion 114 is SiGe having a Ge content 10% lower than that of the sacrificial region 113.
  • the material of the sacrificial region 113 may be SiGe having a Ge content of 40%, and the material of the upper fin portion 114 is SiGe having a Ge content of 30%.
  • the structure in which the upper fin portion is formed of a SiGe material can fabricate a PMOS device, and the SiGe can improve the mobility of carrier holes in the PMOS device, improve channel performance, and enhance gate control.
  • the surface of the fin portion 110 may have a SiGe epitaxial layer, and may further have a Si epitaxial layer outside the SiGe epitaxial layer.
  • the surface of the fin portion 110 may have a Si epitaxial layer. If the thickness of the Si epitaxial layer is less than 5 nm, it is more suitable for fabricating a PMOS semiconductor device. The thin Si epitaxial layer can form compressive stress on the underlying SiGe epitaxial layer or the SiGe upper fin portion, thereby improving the hole mobility of the SiGe and improving the channel performance in the PMOS device. If the thickness of the Si epitaxial layer is higher Thicker is more suitable for making NMOS devices. The Si epitaxial layer has a better surface state, and the electrons are carriers in the NMOS device.
  • isolation regions 300 may be present in the device at different locations along the x-direction.
  • the isolation region 300 is located substantially below the source region 6002; and/or substantially below the drain region 6001; and/or substantially below the gate structure.
  • the number, location, and size of the isolation regions 300 can be selected based on the performance requirements of forming the device.
  • the isolation region 300 When the isolation region 300 is located only inside the source portion 6002 or the fin portion 110 below the drain region 6001, the isolation region 300 has a better isolation effect, and the device structure on the side where the isolation region 300 is not formed is better in mechanical strength and thermal conductivity. . Since the upper fin portion 114 is connected to the lower fin portion 112 through the sacrificial layer, the thermal conductivity of the sacrificial layer 113 is better than that of the isolation region 300, and it is combined with the upper fin portion 114 and the lower fin portion 112. Compact and mechanically strong. When the length of the isolation region 300 in the x direction is relatively short, the thermal conductivity and mechanical strength of the device are better.
  • the isolation effect of the device is better.
  • the sacrificial layer 113 has one or more short isolation regions 300 having a short length in the x direction. This structure can reduce the leakage current between the source and the drain and maintain good Mechanical strength.
  • the length of the short isolation region 300 in the x direction should be less than four times the length of the fin portion 110 in the y direction.
  • the location of the isolation region 300 in the device will have different effects on the performance of the device, including the following:
  • the isolation zone 300 exists only below the drain zone 6001.
  • the sacrificial layer 113 is still present in the source region 6002 and the fin portion 110 under the gate structure, and the sacrificial layer 113 connects the upper fin portion 114 and the lower fin portion 112.
  • the structure has better thermal conductivity and higher mechanical strength.
  • the drain region 6001 is isolated from the lower substrate 180, the leakage current of the drain region 6001 is reduced.
  • the isolation region 300 is present under the drain region 6001 and a portion of the gate structure. This structure can reduce the parasitic capacitance between the gate structure and the lower fin portion 112 while reducing the leakage current of the drain region 6001.
  • the isolation region 300 is present below the gate structure, and the length of the isolation region in the x direction may be equal to the length of the gate structure in the x direction.
  • the length of the isolation region in the x direction is smaller than the length of the gate structure. This structure has an excellent short channel effect and can effectively reduce leakage current between the source region 6002 and the drain region 6001 through the gate structure.
  • the isolation region 300 exists directly under the gate structure 410, and the isolation region is equal to or smaller than the length of the gate structure 410 in the x direction.
  • This structure can effectively reduce the leakage current between the source region 6002 and the drain region 6001 through the gate structure 410.
  • the isolation zone can also extend through the entire fin section.
  • the material of the interlayer dielectric layer 600 may be SiO 2 , and the height of the interlayer dielectric layer may be flush with the height of the gate structure 410.
  • the isolation region 300 has a back-cut region 301 on both sides in the y direction, and the back-cut region 301 is retracted in the y direction with respect to both sides of the fin portion by a distance smaller than a quarter of the width of the fin portion 110 in the y direction. .
  • the position where the cutout region 301 is in contact with the lower fin portion 112 has a rounded curved surface as shown in FIG.
  • the gate structure may cover the surface of the back-cut region 301 and surround the inside of the fin portion in the y direction, covering the lower end of the upper fin portion 114. Part of the surface. This structure can effectively enhance the gate control strength and greatly improve the performance of the device.
  • the present invention also provides an integrated chip in combination with actual needs and production conditions.
  • Such chips are formed by integration of semiconductor devices.
  • the semiconductor device integrated in the chip includes a fin-type semiconductor structure having an isolation region formed in the present embodiment, and a non-isolated region fin-type semiconductor structure.
  • the non-isolated region fin-type semiconductor structure is fabricated in the same production line as the fin-type semiconductor structure in the present embodiment, so that there may be a sacrificial region therein. However, depending on the required performance of the device, no isolation region is formed in the partial fin-type semiconductor structure, that is, the non-isolated region fin-type semiconductor structure.

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Abstract

本发明提供一种能够有效控制源漏区之间漏电流、提高栅极控制能力的鳍型半导体结构。所述鳍型半导体结构包括：具有下部衬底和鳍片部的鳍型衬底，形成在鳍片部上的源区和漏区，形成在所述源漏区之间横跨在鳍片部上的栅极结构，形成在所述鳍片部两侧且位于栅极结构下方的浅沟道隔离，以及形成在所述鳍片部中的隔离区。隔离区可以基本位于源区下方；和/或基本位于漏区下方；和/或基本位于栅极结构下方。本发明还提出了一种上述半导体结构的成型方法。

Description

一种鳍型半导体结构及其成型方法 技术领域
本发明涉及半导体设计及其制造技术领域，具体来说，涉及一种鳍型半导体结构及其成型方法。
背景技术
FinFET称为鳍式场效晶体管(Fin Field-Effect TransistorFinFET)，是一种新的互补式金氧半导体(CMOS)晶体管。Fin是鱼鳍的意思，FinFET命名根据晶体管的形状与鱼鳍相似性，其他类似的名称包括Tri-gate MOS等。
FinFET是源自于目前传统标准的场效晶体管(Field-Effect TransistorFET)的一项创新设计。在传统晶体管结构中控制电流通过的闸门只能在闸门的一侧控制电路的接通与断开，属于平面的架构。在FinFET的架构中，闸门成类似鱼鳍的叉状3D架构，可于电路的两侧控制电路的接通与断开。和传统晶体管相比，这种设计可以改善电路控制也可以大幅缩短晶体管的闸长。
然而，常规FinFET由于衬底结构自身的特点，其源区漏区之间存在漏电流会通过衬底传导的问题，由于闸长较短，有时会产生较大的漏电流。另外，源漏和衬底之间也存在电容较高的问题。
所以，需要提出一种能够减小源漏区之间的漏电流，进一步改善栅极控制能力的鳍式场效晶体管。
发明内容
本发明为了至少解决上述存在的技术缺陷之一，提出了一种鳍型半导体结构以及制造这种半导体结构的方法。本发明提供的鳍型半导体结构能够进一步减少源漏区之间的漏电流，并增强栅极的控制能力，有效提高半导体器件的性能、延长寿命。
所述鳍型半导体结构包括：具有下部衬底和鳍片部的鳍型衬底；形成在鳍 片部上的源区和漏区；形成在所述源区和漏区之间横跨在鳍片部上的栅极结构，栅极结构下方的鳍片部为沟道；形成在所述鳍片部两侧的浅沟道隔离；以及形成在所述鳍片部中的位于沟道和下部衬底之间的一个或多个隔离区。
所述鳍片部两端的截面可以为长方形或者三角形，所述鳍片部的顶面可以是圆滑的曲面。
所述鳍型半导体结构可以包括位于所述栅极结构两侧的层间介质层，所述层间介质层的高度与所述栅极结构齐平。
所述隔离区可以位于所述源区和/或漏区下方，也可以位于所述栅极结构的下方，与栅极结构的长度相等或小于栅极结构的长度。
所述半导体结构包括形成于鳍片部内的牺牲区，所述隔离区形成在所述牺牲区中，所述牺牲区从鳍片部的两侧露出。所述牺牲区可以为贯穿鳍片部的牺牲层，也可以为一个或多个牺牲块。
所述鳍片部包括上鳍片部、牺牲区和下鳍片部。所述上鳍片部的材料可以是Si，鳍片部的表面可以具有一SiGe外延层。或者，所述上鳍片部的材料还可以是SiGe，鳍片部的表面具有Si外延层。在所述SiGe外延层外，还可以具有Si外延层。
所述隔离区的两侧可以具有回切区，所述回切区相对于鳍片部两侧面缩进的距离小于鳍片部宽度的四分之一。
另一方面，本发明还提供了一种形成鳍型半导体结构的方法，包括：
步骤A、提供一衬底，形成具有下部衬底和鳍片部的鳍型衬底，所述鳍片部包含牺牲区；
步骤B、刻蚀部分或者全部牺牲区以形成空腔，并在空腔中填充绝缘材料形成隔离区；
继续填充绝缘材料，形成浅沟道隔离；
进行化学机械平坦，露出鳍片部的上表面，刻蚀浅沟道隔离，暴露出鳍片部；
步骤C、形成横跨在鳍片部上的伪栅结构并在伪栅结构两侧形成侧墙，在伪栅结构两侧的鳍片部上形成源区和漏区；
步骤D、利用栅替代工艺替代伪栅结构形成金属栅结构。
所述步骤A可以包括：提供一衬底，衬底中具有牺牲区，所述牺牲区为贯穿整个衬底的牺牲层；
或者，提供一衬底，对所述衬底进行离子注入形成牺牲区，所述牺牲区为一个或多个牺牲块；
在衬底上形成刻蚀阻挡层，在刻蚀阻挡层上形成掩膜，刻蚀所述刻蚀阻挡层以暴露部分衬底，刻蚀所述衬底形成鳍片部，鳍片部具有上鳍片部、牺牲层和下鳍片部。
所述步骤A可以包括：刻蚀形成鳍片部，所述鳍片部两端的截面为长方形或所述鳍片部两端的截面为三角形。
所述方法还可以包括在漏区和/或源区所在位置下方的鳍片部内刻蚀形成空腔；或者刻蚀栅极结构所在位置下方的全部或部分牺牲区，形成空腔。
在所述步骤B之后，可以包括在所述鳍片部和空腔的表面外延生长SiGe外延层，或者在所述鳍片部和空腔的表面外延生长Si外延层的步骤。以及，还可以包括在所述SiGe外延层外外延生长Si外延层。
在进行步骤C形成伪栅结构之前，对隔离区进行回切处理，形成回切区，所述步骤C形成的伪栅结构覆盖所述回切区的表面，并向所述鳍片部内侧包围。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1至图11是根据本发明实施例鳍型半导体器件制造方法的中间步骤示意图；
图11是本发明实施例中形成的半导体器件的结构示意图；
图12是本发明实施例中另一种鳍型衬底的结构示意图；
图13是本发明实施例中另一种空腔形成布局的结构示意图；
图14是本发明实施例中回切区的结构示意图；
图15是本发明实施例中在鳍片部和空腔表面上形成SiGe层和Si层的结构示意图；
图16是本发明实施例三中形成侧墙的半导体器件结构示意图；
图17是本发明实施例三中形成层间介质层的半导体器件结构示意图；
图18是本发明实施例三中去除伪栅结构的半导体结构示意图；
图19是本发明实施例三中形成隔离区和栅极结构的半导体结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。它们的目的并不在于限制本发明，仅作为示例。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。
在说明实施例之前对本发明器件的方向做出定义，令鳍片部从衬底上突起的方向为z方向，与z方向垂直且平行于鳍片部顶端的方向为x方向，垂直于x、z方向的方向为y方向。
实施例一
本发明提出一种半导体的结构及其制造方法，如图1-11所示，为该方法的中间步骤示意图。以下，将参照这些附图来对本发明实施例的各个步骤予以详细说明。
步骤A：提供一包含牺牲区的衬底100，在所述衬底上形成具有下部衬底180和鳍片部110的鳍型衬底100，所述牺牲区113在鳍片部内，参考图6所示。
在准备衬底的工艺中，如图1所示，提供一衬底100，衬底100包括第一衬底101，其材料可以为硅，然后用外延生长(epitaxy)的方法在第一衬底101 上形成一层牺牲区113，在本实施例中，所述牺牲区113为贯穿整个衬底的牺牲层113。牺牲层113的材料优选为SiGe、n型掺杂(n-type doped)硅等，厚度优选为5-50nm。再于牺牲层113上继续生长，例如外延生长第二衬底102，所述第二衬底102即成为后续加工步骤中所形成的鳍片部110的上鳍片部114的基础，由此形成包含牺牲区113的衬底100。特别地，所述牺牲层113的材料可以是Ge含量40％的SiGe，第二衬底102的材料可以是Si，或者所述第二衬底102是Ge含量比牺牲层略低的SiGe，优选为Ge含量比牺牲层低10％以上的SiGe。根据形成的器件对性能的要求不同，可以使用不同材料形成第二衬底102。例如：对于NMOS来讲，第二衬底102可选为硅；对于PMOS来讲，第二衬底102优选为硅锗，其中Ge含量可以是30％。这种第二衬底由SiGe材料形成的结构能够提高PMOS器件中载流子空穴的迁移率，提高沟道的性能，增强栅控。
形成包含牺牲层的衬底100之后，即需要加工鳍片部，如图2所示，在衬底100的表面形成刻蚀阻挡层900。刻蚀阻挡层900可以有多种选择，在本实施例中，具体地，可以沉积一层氧化物层901，例如10-200nm，在氧化物层901上形成一层氮化物层902，例如10-200nm，形成刻蚀阻挡层900。参考图3，在刻蚀阻挡层900上形成沿y方向一定宽度的掩膜以保护部分刻蚀阻挡层900，所述一定宽度由鳍片部的顶面沿y方向的宽度所决定，例如优选为1-10纳米，而后对氮化物层902和氧化物层901刻蚀阻挡层900进行选择性刻蚀，形成如图4所示的结构，暴露部分衬底100的上表面。
然后，以刻蚀阻挡层900作为阻挡，对衬底100进行刻蚀，形成鳍片部110，如图5所示。鳍片部110具有上鳍片部114、贯穿鳍片部的牺牲层113和下鳍片部112，如图6所示。其中，第二衬底102形成上鳍片部114，部分第一衬底101形成下鳍片部112。下部衬底180和鳍片部110组成鳍型衬底100。鳍片部110的形状可以根据需要进行选择，并由刻蚀工艺和参数进行控制，例如可以形成两端截面为长方形的鳍片部110，如图6所示。也可以形成两端截面为三角形的鳍片部210，如图12所示。
根据位于第一衬底101与第二衬底102的材料是否相同，上鳍片部114的材料和下鳍片部112的材料可以均为材料Si，或者，上鳍片部114的材料可 以优选为Ge含量30％的SiGe，下鳍片部112的材料为Si。根据所要形成的器件性能要求的不同，可以用其它材料形成上鳍片部114和下鳍片部112，本领域的技术人员可以根据需要进行这些材料的选择和变化，这些均在本发明的保护范围之内。
可选择地，可以对鳍片部顶面111进行圆滑(rounding)处理，使鳍片部顶面111具有圆滑的曲面，如图7所示。其作用在于，它可以减小器件的局部电场强度，增强器件的可靠性。圆滑处理的方法可以采用各向同性刻蚀或者氢气环境下700摄氏度以上的退火等方法。
而后，进入步骤B：刻蚀部分牺牲层113以形成空腔200，并在空腔200中填充绝缘材料，形成隔离区300和浅沟道隔离105。
首先，在鳍型部110表面均匀涂覆光刻胶，并用掩膜遮挡要保留的牺牲层113以及鳍片部110，暴露需要形成空腔200的牺牲层113。对被暴露部分的光刻胶进行曝光，洗掉曝光的光刻胶之后，刻蚀该部被暴露的牺牲层113。在上鳍片部114和下鳍片部112之间形成贯穿y轴方向的空腔200，如图7所示。所述空腔200在z方向上的高度可以是5-50nm。由于牺牲层113的材料是由硅锗构成，如果空腔200太高的话，也就是牺牲层113太厚，会在硅锗牺牲层113中产生位错等缺陷(defect)，该缺陷很可能延伸、并进入上面的沟道区，使器件的性能变差。所以，空腔200的高度优选为5-20纳米。
刻蚀空腔200时可以使用多次干法和/或湿法混合刻蚀，包括等离子刻蚀。其中，干法刻蚀能够更好的控制空腔的形状和尺寸，形成相对较小的空腔200。特别的，为了减小刻蚀对表面损伤，减少表面缺陷，刻蚀空腔200的最后一次刻蚀工艺应为湿法刻蚀。
空腔200刻蚀完成后，去除鳍片部110表面的光刻胶。
另外，作为另一种刻蚀形成空腔200的例子，可以沿x方向的不同位置形成不同长度的一个或多个空腔200，如图13所示，形成第一空腔2001和第二空腔2002。空腔200的数量、位置、尺寸可以根据形成所述器件对性能要求的不同进行选择。当空腔200只位于源区6002或漏区6001下方的鳍片部内部时，器件具有较好的隔离效果，未形成空腔200一侧的器件结构的导热性和机械强度更好，因为上鳍片部114通过牺牲层113和下鳍片部112相连接，牺牲 层113，如硅锗，的导热性比空腔里填充的隔离区300,如氧化硅，的导热性好；而且它的机械强度比有形成空腔200然后回填隔离区300的结构要高，因为牺牲层113和上鳍片部114和下鳍片部112是一整体形成的，之间结合紧密。例如当为了获得更高机械强度和更好导热性的器件时可以形成沿x方向相对长度较短的空腔200，而当需要获得隔离效果较好的器件时可以在牺牲层中形成多个空腔200。为了维持器件的机械强度，保留部分牺牲层113是必要的。对于栅长比较长的器件，例如沿x方向伪栅结构长度大于120纳米，如果空腔200沿x方向过宽的话，器件的机械性能会下降。可以通过形成1个或者多个沿x方向宽度较短的短空腔200，以实现减少源漏之间的漏电流，同时维持良好的机械性能和强度的目的。短空腔200沿x方向的长度应小于鳍片部110沿y方向宽度的4倍。
空腔在器件中的位置不同，会对器件的性能产生不同的影响，包括以下几点：
1.在漏区6001所在位置下方的鳍片部内刻蚀形成空腔200。在这种结构中，源区6002以及伪栅结构下方的鳍片部仍然存在牺牲层113，牺牲层113连接上鳍片部114和下鳍片部112。该结构具有较好的导热性和更高机械强度。同时，由于漏区6001与衬底之间隔离，减小了漏区6001的节漏电流。
2.在漏区6001和部分伪栅结构所在位置下方的鳍片部内刻蚀形成空腔200。这种结构可以降低栅极和鳍片下面衬底之间的寄生电容，同时减小了漏区6001的节漏电流。
3.刻蚀伪栅结构所在位置下方的牺牲区，形成空腔200。空腔在x方向上的长度可以等于伪栅结构的长度。当栅极结构沿x方向的长度较长时，空腔沿x方向的长度小于栅极结构的长度。这种结构具有优异的短沟道效应，并且能够有效减小源区6002与漏区6001之间通过伪栅结构下方的漏电流。
4.对于在x方向上栅长较长的器件，优选形成一个或者多个在x方向相对较短的短空腔200。这种结构可以在提高隔离效果的情况下，保证器件的机械稳定性，提高了良品率。
刻蚀完空腔200之后，可选择地，对空腔200的边缘以及鳍片部顶面111的边缘进行圆滑(rounding)处理，圆滑处理的方法可以采用各向同性刻蚀或 者氢气环境下700摄氏度以上的退火等方法。该步骤使上鳍片部114的顶部111具有圆滑的表面，如图7所示。上鳍片部114的下表面也可以处理成圆滑曲面。圆滑处理的作用在于，它可以减小器件的局部电场强度，增强器件的可靠性。
特别的，当所述鳍片部110两端的截面形状为基本长方体形时，通过对空腔200的边缘进行圆滑处理，所述上鳍片部114可以形成具有圆角的基本长方体型结构或者圆柱形结构。如果圆滑处理的程度较小，则上鳍片部114形成具有圆角的基本长方体型结构，如果圆滑处理的程度较大，则上鳍片部114形成基本圆柱形结构。
再后，用绝缘材料填充所述空腔200，形成隔离区300。绝缘材料可以是SiO2、HfO2等。填满空腔200后，应继续填充绝缘材料以形成浅沟道隔离(STI)105，如图8所示。浅沟道隔离105的上表面要高于鳍片部的顶端111。之后，进行化学机械平坦化，露出鳍型部的上表面。再对浅沟道隔离进行刻蚀，暴露鳍片部110，刻蚀停止在隔离区300的上表面位置。可以暴露出部分隔离区300，如图9所示。
特别的，在填充绝缘材料之前，可以对鳍片部110进行热氧化处理。鳍片部表面会因热氧化处理而形成SiO2，从而缩小甚至封闭空腔200。热氧化处理后，应向剩余的空腔内和鳍片部110上填充绝缘材料，形成完整的隔离区300和浅沟道隔离105。热氧化可以使得上鳍片部的下表面具有良好的表面质量，从而不会影响鳍片里面载流子的迁移率。
形成完整的隔离区300和浅沟道隔离105后，所述隔离区300沿y方向应从鳍片部110的两侧露出，如图9所示。此后，可以对隔离区300进行回切处理。当隔离区是二氧化硅材料的时候，用氢氟酸进行湿法刻蚀，刻蚀部分隔离区300，在隔离区沿y方向的两侧形成回切区301(undercut)，如图14所示。回切区301沿y方向相对于鳍片部两侧面缩进的距离应小于鳍片部110沿y方向宽度的四分之一，这样可以维持鳍片的机械稳定性。当隔离区300位于栅极结构下方时，如果存在回切区301，则栅极结构可以覆盖回切区301的表面，并且沿y方向向鳍片部内侧包围，覆盖上鳍片部114下端的部分表面。这种结构能够可以增强栅控制，减小短沟道效应，有效增强栅控强度，大幅提高器件 性能。
出于优化器件性能的考虑，可选择地，可以在刻蚀牺牲层形成空腔200之后，在鳍片部110上通过外延生长形成SiGe层和Si层。例如，当上鳍片部114的材料为Si时，可以在鳍片部110和空腔200表面外延生长SiGe外延层，还可以再在SiGe外延层上外延生长形成Si外延层，如图15所示。当上鳍片部114的材料为SiGe时，可以在鳍片部110和空腔200表面外延生长形成Si外延层(图中未示出)。如果上述Si外延层的厚度小于5纳米，则更适合制作PMOS半导体器件。厚度较薄的Si外延层能够对下方的SiGe外延层或者SiGe上鳍片部形成压应力，从而提高SiGe的空穴迁移率，能够提高PMOS器件中沟道的性能。如果Si外延层的厚度较厚，则更适合制作NMOS器件，Si外延层具有更好的表面态，其中的电子是NMOS器件中的载流子。对于优选CMOS实施例，优选鳍片为硅，相对硅锗为牺牲层时具有良好的刻蚀选择性。可以在形成空腔之后，选择性在PMOS鳍片的区域，顺序进行硅锗和硅的外延生长。这些优化的实施例，本领域普通技术人员均可以根据需要进行选择和变化，这些均不超出本发明的保护范围。
另外，在所述步骤B中，也可以先填充绝缘材料形成浅沟道隔离(STI)105，之后，进行化学机械平坦化，露出鳍型部的上表面。再对浅沟道隔离进行刻蚀，暴露鳍片部110，刻蚀停止在暴露出部分牺牲区200的位置处。之后，再从暴露出来的牺牲区200处进行刻蚀、填充步骤，形成隔离区300。
而后，进入步骤C：形成横跨在鳍片部110上的伪栅结构，伪栅结构下方的鳍片部为沟道106，沿y方向在伪栅结构400两侧的鳍片部110上形成源区和漏区。
在本实施例中，可以在鳍片部110上沉积氧化铪、氮化物等其它高K介质材料，在浅沟道隔离105上方形成横跨在鳍片部上的伪栅。刻蚀多余的高K介质材料，形成伪栅结构400，如图10所示。
然后，形成侧墙500，在鳍片部110和伪栅结构400上沉积氮化物，形成氮化物层。刻蚀鳍片部110上和伪栅结构400顶部的氮化物层，从而在沿x方向伪栅结构400两侧、鳍片部110之上形成侧墙500，如图11所示。
最后沿x方向伪栅结构400两侧的鳍片部上进行离子注入，从而形成源区 6002和漏区6001，如图11所示。此外，在形成源区和漏区之前，还可以包括进行离子注入，从而形成源漏扩展区的步骤。
步骤D：利用栅替代工艺替代伪栅结构形成栅极结构。
特别的，为了在工厂中便于批量化生产，一般衬底100在x方向上都会具有比较大的长度，即提供长衬底。所以优选的，可以预先设计好单个器件结构特点、在x方向上的长度以及隔离区300的数量、位置、尺寸，先在具有较大长度的衬底100上完成步骤A和步骤B的工序，之后按照预先设计的器件长度，将已经形成隔离区300和浅沟道隔离105的器件沿x方向截断，形成单独的器件。之后再进行步骤C、D的加工。截断步骤与形成空腔、隔离区的步骤相互独立。
另外，考虑实际生产中，各种半导体器件自身的性能要求并不相同，有些器件并不需要在鳍片部中形成隔离区。例如ESD器件，如果鳍片部中存在隔离区，反而会影响器件的性能。所以，不是所有器件都需要形成隔离区。但是，在批量化的生产线上为了方便供料和加工，所有的衬底中都包含牺牲区。而在加工过程中根据所要生产的器件类型不同，决定是否要在器件中形成隔离区。即，使用本发明的方法加工的半导体器件结构可能只具有牺牲区，但不具有隔离区。鳍片部中的牺牲区全部保留，形成无隔离区鳍型半导体结构。
实施例二
下面将仅就第二实施例区别于第一实施例的方面进行阐述。未描述的部分应当认为与第一实施例采用了相同的步骤、方法或者工艺来进行，因此在此不再赘述。
步骤A：提供一包含牺牲区113的衬底100，在所述衬底100上形成具有下部衬底180和鳍片部110的鳍型衬底100，所述牺牲区113在鳍片部内。
与第一实施例不同，在本实施例中，所述牺牲区113不是贯穿鳍片部的牺牲层，而表现为一个或多个牺牲块113。
形成牺牲块113的方式可以在准备衬底100的工艺中完成，在本实施例中，提供一衬底100，在衬底100表面需要保护的位置形成掩膜，从而暴露需要形成牺牲块113的位置，进行离子注入，优选为n型掺杂，例如P或As。从而在衬底100中形成具有一定浓度的区域，即形成牺牲区113。对衬底进行刻蚀， 形成鳍片部110，所述牺牲区为分布在衬底中的一个或多个区域的牺牲块113。所述牺牲区为位于鳍片部110中的一个或几个区域。
步骤B：刻蚀部分或者全部牺牲区以形成空腔，并在空腔中填充绝缘材料，形成隔离区和浅沟道隔离。
根据形成器件对性能的要求刻蚀部分或全部牺牲块113，可以对形成的空腔200边缘进行圆滑处理，还可以在鳍片部110和空腔200表面外延生长SiGe外延层和/或Si外延层。用二氧化硅或其它绝缘材料填充所述空腔200，形成隔离区300和浅沟道隔离105。
步骤C、在浅沟道隔离105上方形成横跨在鳍片部上的伪栅结构400，伪栅结构下方的鳍片部为沟道106，在伪栅结构400两侧的鳍片部上形成源区6002和漏区6001。
步骤D、利用栅替代工艺替代伪栅结构形成栅极结构。
实施例三
在实施例一和实施例二中，刻蚀部分牺牲区113以形成空腔200的步骤均紧接在提供沉底100的步骤之后，即刻蚀步骤均为步骤B。本发明还提供了一种加工方法，可以在去除伪栅结构之后再对牺牲区113进行刻蚀。具体的，在进行步骤A后，执行如下步骤：
步骤B：在鳍片部110上填充隔离材料，形成浅沟道隔离(STI)105，绝缘材料可以是SiO2、HfO2等。浅沟道隔离105的上表面要高于鳍片部的顶面111。之后，进行化学机械平坦化，露出鳍型部的上表面。再对浅沟道隔离进行刻蚀，暴露鳍片部110和其中的部分牺牲区200。
步骤C：形成横跨在鳍片部110上的伪栅结构，伪栅结构下方的鳍片部为沟道，沿y方向在伪栅结构400两侧的鳍片部110上形成源区和漏区。
然后，在沿x方向伪栅结构400的两侧、鳍片部110之上形成侧墙500，如图16所示。在侧墙500沿x方向的两侧形成层间介质层600。所述层间介质层600将未被伪栅结构400和侧墙500覆盖的鳍片部110完全覆盖。所述层间介质层600的高度可以与伪栅结构400的高度相齐平，如图17所示。层间介质层的材料可以是SiO2。
而后，进入步骤D：如图18所示，首先，对伪栅结构400进行选择性刻 蚀，刻蚀掉整个伪栅结构400，暴露出原先被伪栅结构覆盖、侧墙500内侧的鳍片部110和牺牲区113。之后，可以对两侧墙500内侧的浅沟道隔离105进行刻蚀，使这部分浅沟道隔离105沿z方向向下刻蚀少部分，暴露出牺牲区113。之后，通过刻蚀技术将暴露出的牺牲区113刻蚀掉，特别的，可以刻蚀伪栅结构所在位置正下方的部分牺牲区，或者刻蚀侧墙内侧、伪栅结构正下方的全部牺牲区，形成空腔200。以这种方式暴露出的牺牲区113位于两侧墙500之间，所以，刻蚀掉暴露出的牺牲区113后形成的空腔200隔正好位于两侧墙500之间。再后，用绝缘材料填充所述空腔200，形成隔离区300。最后，执行步骤E，在两侧墙500内侧形成栅极结构410，如图19所示。另外，当牺牲区是贯穿整个鳍片部的牺牲层时，也可以刻蚀掉鳍片部110中的全部牺牲区，空腔贯穿整个鳍片部。
实施例三的方法的优点在于隔离区的自对准。本领域技术人员不需要进行特别的定位、对准步骤，就可以将所述隔离区正好形成在所述栅极结构的正下方。这种结构具有优异的短沟道效应，并且能够有效减小源区与漏区之间通过栅极结构下方的漏电流。另一方面，采用实施例三的方法还可以刻蚀掉整个牺牲区，而不引起上鳍片部塌陷、脱落的问题。因为，在刻蚀牺牲区之前，上鳍片部的上方已经形成了层间介质层，所述层间介质层与所述上鳍片部之间的结合力可以为上鳍片部提供足够的稳定性，即使上鳍片部下方的全部牺牲区或牺牲层都被刻蚀，也能够保持在原始位置处。当需要在整个上鳍片部的下方形成隔离区时，本领域技术人员可以使用具有牺牲层的衬底，并采用实施例三的成型方法。
实施例四
此外，本发明还提出了一种鳍型半导体器件结构，参考图11，所述器件具有：包括下部衬底180和鳍片部110的鳍型衬底100，鳍片部110上的源区6002和漏区6001，源区6002和漏区6001之间横跨在鳍片部110上的栅极结构。在图11中，标记400为伪栅结构，完成栅替代工艺后，栅极结构将代替所述伪栅结构400的位置。栅极结构下方的鳍片部为沟道，沿y方向鳍片部110两侧且位于栅极结构下方的浅沟道隔离105，沿x方向栅极结构的两侧的侧墙500，以及形成在所述鳍片部110中的位于沟道和下部衬底之间的隔离区 300。所述鳍型半导体器件结构上还可以包括沿x方向侧墙500两侧的层间介质层。鳍片部110可以包括上鳍片部114、牺牲区113和下鳍片部112。所述鳍片部110顶面宽度优选为1-10nm，其鳍片部两端的截面可以是长方形，如图6所示，或者为三角形，如图12所示，顶面可以是圆滑的曲面。两端截面为三角形的鳍片部具有更好的机械稳定性，而两端截面为长方形的鳍片部形成器件后栅控更好。
特别的，当所述鳍片部110两端截面形状为长方体形时，所述上鳍片部114可以是具有圆角的长方体型结构或者圆柱形结构。如果圆滑处理的程度较小，则上鳍片部114形成具有圆角的基本长方体型结构，如果圆滑处理的程度较大，则上鳍片部114形成基本圆柱形结构。
所述隔离区的高度优选为5-20nm，隔离区的材料可以是SiO2和/或HfO2。所述浅沟道隔离105的上表面可以低于隔离区300的上表面。浅沟道隔离105的上表面低于隔离区300上表面时，可以使栅极结构沿z方向更多的覆盖上鳍片部，该特征可以减小漏电流，增强驱动电流并加强栅控。
牺牲区113沿y方向从鳍片部110的两侧露出。所述隔离区300形成在所述牺牲区113中。所述牺牲区113可以是贯穿鳍片部110的牺牲层或者是一个或多个牺牲块。
下鳍片部112的材料可以是Si，牺牲区113的材料是SiGe，上鳍片部114的材料是Si。或者，下鳍片部112的材料可以是Si，牺牲区113的材料是SiGe，上鳍片部114的材料是Ge含量比牺牲区113低10％的SiGe。特别的，牺牲区113的材料可以是Ge含量40％的SiGe，上鳍片部114的材料是Ge含量30％的SiGe。这种上鳍片部由SiGe材料形成的结构可以制作PMOS器件，SiGe能够提高PMOS器件中载流子空穴的迁移率，提高沟道的性能，增强栅控。
另外，当上鳍片部114的材料为Si时，鳍片部110的表面可以具有SiGe外延层，在SiGe外延层外还可以具有一层Si外延层。或者，当上鳍片部114的材料为SiGe时，鳍片部110的表面可以具有Si外延层。如果上述Si外延层的厚度小于5纳米，则更适合制作PMOS半导体器件。厚度较薄的Si外延层能够对下方的SiGe外延层或者SiGe上鳍片部形成压应力，从而提高SiGe的空穴迁移率，能够提高PMOS器件中沟道的性能。如果Si外延层的厚度较 厚，则更适合制作NMOS器件，Si外延层具有更好的表面态，其中的电子是NMOS器件中的载流子。
特别的，器件中可以在沿x方向的不同位置上存在多个隔离区300。所述隔离区300基本位于源区6002下方；和/或基本位于漏区6001下方；和/或基本位于栅极结构下方。隔离区300的数量、位置、尺寸可以根据形成所述器件对性能要求的不同进行选择。
当隔离区300只位于源区6002或漏区6001下方的鳍片部110的内部时，隔离区300的隔离效果较好，未形成隔离区300一侧的器件结构的机械强度和导热性更好。因为上鳍片部114通过牺牲层与下鳍片部112相连接，牺牲层113的导热性比隔离区300的导热性好，而且其与上鳍片部114和下鳍片部112之间结合紧密，机械强度高。当隔离区300沿x方向长度相对较短时，器件的导热性和机械强度更好。当牺牲层113中存在多个隔离区300时，器件的隔离效果更好。当栅极沿x方向长度大于120纳米时，牺牲层113中存在一个或多个沿x方向长度较短的短隔离区300，这种结构可以减小源漏之间的漏电流，并维持良好的机械强度。短隔离区300沿x方向的长度应小于鳍片部110沿y方向长度的4倍。
隔离区300在器件中的位置不同，会对器件的性能产生不同的影响，包括以下几点：
1.隔离区300只存在于漏区6001下方。在这种结构中，源区6002以及栅极结构下方的鳍片部110中仍然存在牺牲层113，牺牲层113连接上鳍片部114和下鳍片部112。该结构具有较好的导热性和更高机械强度。同时，由于漏区6001与下部衬底180之间隔离，减小了漏区6001的节漏电流。
2.隔离区300存在于漏区6001和部分栅极结构下面。这种结构可以降低栅极结构和下鳍片部112之间的寄生电容，同时减小了漏区6001的节漏电流。
3.隔离区300存在于栅极结构的下方，隔离区在x方向上的长度可以与栅极结构沿x方向的长度相等。当栅极结构沿x方向的长度较长时，隔离区沿x方向的长度小于栅极结构的长度。这种结构具有优异的短沟道效应，并且能够有效减小源区6002与漏区6001之间通过栅极结构下方的漏电流。
4.对于在x方向上栅极结构长度较长的器件，在鳍片部中存在沿x方向 长度相对较小的多个短隔离区300。这种结构可以在增强隔离效果的情况下，保证器件的机械稳定性，提高了良品率。
对于通过实施例三的方法得到的鳍型半导体结构，所述隔离区300存在于栅极结构410的正下方，隔离区与栅极结构410沿x方向的长度相等或者小于栅极结构的长度。这种结构能够有效减小源区6002与漏区6001之间通过栅极结构410下方的漏电流。特别的，隔离区也可以贯穿整个鳍片部。
特别的，所述层间介质层600的材料可以是SiO2，层间介质层的高度可以与栅极结构410的高度相齐平。
另外，隔离区300沿y方向的两侧具有回切区301，回切区301沿y方向相对于鳍片部两侧面缩进的距离应小于鳍片部110沿y方向宽度的四分之一。回切区301与下鳍片部112接触的位置具有圆滑的曲面，如图14所示。当隔离区300位于栅极结构下方时，如果存在回切区301，则栅极结构可以覆盖回切区301的表面，并且沿y方向向鳍片部内侧包围，覆盖上鳍片部114下端的部分表面。这种结构能够有效增强栅控强度，大幅提高器件性能。
另外，结合实际需要和生产条件，本发明还提供了一种集成芯片。这种芯片由半导体器件集成形成。集成在芯片中的半导体器件包括本实施例中形成的具有隔离区的鳍型半导体结构，以及无隔离区鳍型半导体结构。所述无隔离区鳍型半导体结构与本实施例中的鳍型半导体结构在相同的生产线中制造，所以其中可以具有牺牲区。但是根据器件所需性能的不同，部分鳍型半导体结构中没有形成隔离区，即为所述无隔离区鳍型半导体结构。
以上已经根据本发明的实施例对本发明进行了描述。本发明的应用范围不局限于说明书中描述的特定实施例的制造工艺、机构、物质组成、手段方法或步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的制造工艺、机构、物质组成、手段方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些制造工艺、机构、物质组成、手段方法或步骤包含在其保护范围内。

Claims (20)

  1. 一种鳍型半导体结构，其特征在于，包括：
    具有下部衬底和鳍片部的鳍型衬底；
    形成在鳍片部上的源区和漏区；
    形成在所述源区和漏区之间横跨在鳍片部上的栅极结构，栅极结构下方的鳍片部为沟道；
    形成在所述鳍片部两侧的浅沟道隔离；以及
    形成在所述鳍片部中的位于沟道和下部衬底之间的一个或多个隔离区。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述鳍片部两端的截面为长方形；或者
    所述鳍片部两端的截面为三角形。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述鳍片部的顶面是圆滑的曲面。
  4. 根据权利要求1所述的半导体结构，其特征在于，所述鳍型半导体结构包括位于所述栅极结构两侧的层间介质层和侧墙，所述层间介质层的高度与所述栅极结构齐平。
  5. 根据权利要求1所述的半导体结构，其特征在于，所述隔离区位于所述源区和/或漏区下方。
  6. 根据权利要求1或5所述的半导体结构，其特征在于，所述隔离区位于所述栅极结构的下方，与栅极结构的长度相等或小于栅极结构的长度。
  7. 根据权利要求1所述的半导体结构，其特征在于，包括形成于鳍片部内的牺牲区，所述隔离区形成在所述牺牲区中，所述牺牲区从鳍片部的两侧露出。
  8. 根据权利要求7所述的半导体结构，其特征在于，所述牺牲区为贯穿鳍片部的牺牲层，或者所述牺牲区为一个或多个牺牲块。
  9. 根据权利要求1所述的半导体结构，其特征在于，所述鳍片部包括上鳍片部、牺牲区和下鳍片部。
  10. 根据权利要求9所述的半导体结构，其特征在于，
    所述上鳍片部的材料是Si，鳍片部的表面具有一SiGe外延层；
    或者，所述上鳍片部的材料是SiGe，鳍片部的表面具有Si外延层。
  11. 根据权利要求10所述的半导体结构，其特征在于，在所述SiGe外延层外，具有Si外延层。
  12. 根据权利要求1所述的半导体结构，其特征在于，所述隔离区的两侧具有回切区，所述回切区相对于鳍片部两侧面缩进的距离小于鳍片部宽度的四分之一。
  13. 一种鳍型半导体结构的成型方法，其特征在于，包括以下步骤：
    步骤A、提供一衬底，形成具有下部衬底和鳍片部的鳍型衬底，所述鳍片部包含牺牲区；
    步骤B、刻蚀部分或者全部牺牲区以形成空腔，并在空腔中填充绝缘材料形成隔离区；
    继续填充绝缘材料，形成浅沟道隔离；
    进行化学机械平坦，露出鳍片部的上表面，刻蚀浅沟道隔离，暴露出鳍片部；
    步骤C、形成横跨在鳍片部上的伪栅结构并在伪栅结构两侧形成侧墙，在伪栅结构两侧的鳍片部上形成源区和漏区；
    步骤D、利用栅替代工艺替代伪栅结构形成金属栅结构。
  14. 根据权利要求13所述的方法，其特征在于，所述步骤A包括：提供一衬底，衬底中具有牺牲区，所述牺牲区为贯穿整个衬底的牺牲层；
    或者，提供一衬底，对所述衬底进行离子注入形成牺牲区，所述牺牲区为一个或多个牺牲块；
    在衬底上形成刻蚀阻挡层，在刻蚀阻挡层上形成掩膜，刻蚀所述刻蚀阻挡层以暴露部分衬底，刻蚀所述衬底形成鳍片部，鳍片部具有上鳍片部、牺牲层和下鳍片部。
  15. 根据权利要求13所述的方法，其特征在于，所述步骤A包括：刻蚀形成所述鳍片部，所述鳍片部两端的截面为长方形或所述鳍片部两端的截面为三角形。
  16. 根据权利要求13所述的方法，其特征在于，在漏区和/或源区所在位 置下方的鳍片部内刻蚀形成空腔。
  17. 根据权利要求13所述的方法，其特征在于，刻蚀栅极结构所在位置下方的全部或部分牺牲区，形成空腔。
  18. 根据权利要求13所述的方法，其特征在于，所述步骤B之后，
    在所述鳍片部和空腔的表面外延生长SiGe外延层，
    或者，在所述鳍片部和空腔的表面外延生长Si外延层。
  19. 根据权利要求18所述的方法，其特征在于，在所述SiGe外延层外外延生长Si外延层。
  20. 根据权利要求13所述的方法，其特征在于，在进行步骤C形成伪栅结构之前，对隔离区进行回切处理，形成回切区，所述步骤C形成的伪栅结构覆盖所述回切区的表面，并向所述鳍片部内侧包围。
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