TWI496264B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TWI496264B
TWI496264B TW101141979A TW101141979A TWI496264B TW I496264 B TWI496264 B TW I496264B TW 101141979 A TW101141979 A TW 101141979A TW 101141979 A TW101141979 A TW 101141979A TW I496264 B TWI496264 B TW I496264B
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Taiwan
Prior art keywords
polymer
wafer
substrate
portions
semiconductor device
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TW101141979A
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English (en)
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TW201322406A (zh
Inventor
Jing Cheng Lin
Hsin Chang
Shih Ting Lin
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201322406A publication Critical patent/TW201322406A/zh
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Description

半導體裝置及其形成方法 【交互參照】
本申請案主張在2011年11月30日申請的美國暫時申請案案號61/565,346的優先權，其發明名稱為「Chip-on-Wafer Structures and Methods for Forming the Same」(晶片堆疊晶圓結構及其形成方法)，以參照的方式將該申請案的內容併入本申請案的內容。
本發明主要是關於一種半導體裝置及其形成方法，特別是關於一種具有晶片堆疊晶圓結構之半導體裝置及其形成方法。
在形成三維積體電路(three-dimensional integrated circuit；3DIC)的製程中，可將裝置晶片連接於一晶圓。一般而言，在將上述晶片連接於上述晶圓上後，施加一封膠組合物而將上述裝置晶片與上述晶圓密封。複數個軟銲凸塊是形成於上述晶圓上，以電性連接於上述晶圓中的複數個裝置。上述裝置晶片中的裝置與上述晶圓中的裝置的電性連接，是由矽貫穿孔(Through-Silicon Vias；TSVs)來實現。
在施加上述封膠組合物之後，執行一晶片切割步驟，以將上述晶圓及上述裝置晶片切割成封裝體，其中每個封裝體可包含上述裝置晶片中的一個與上述晶圓中的複數個 晶片中的一個。上述晶片切割步驟一般是使用一刀具來施行，切穿上述晶圓中的切割線。由於上述晶圓可能包含低介電常數介電材料，由上述刀具施加的機械應力可能會造成龜裂。上述低介電常數介電材料中的龜裂可能會傳播到上述晶圓中的晶片，造成良率上的損失。
本發明的一實施例是提供一種半導體裝置，包含一封裝構件、一貫穿導通孔、一導體構件、一第一介電圖形、一凸塊下金屬(Under-Bump-Metallurgy；UBM)、一聚合物以及一第二介電圖形。上述封裝構件包含一基板，其中上述基板包含一正面與在上述正面上的一背面。上述貫穿導通孔是穿透上述基板。上述導體構件是在上述基板的上述背面的上方，並電性連接於上述貫穿導通孔。上述第一介電圖形是形成一環狀物，上述環狀物覆蓋上述導體構件的邊緣部。上述凸塊下金屬是位於上述導體構件的一中央部的上方，並與上述導體構件的上述中央部接觸。上述聚合物是接觸上述基板的一側壁上述第二介電圖形是在上述聚合物的上方並對準於上述聚合物，其中上述第一介電圖形與上述第二介電圖形是由相同的介電材料形成且置於實質上同一水平。
在上述之半導體裝置中，較好為：上述第一介電圖形與上述第二介電圖形包含一額外的聚合物。
在上述之半導體裝置中，較好為：上述第一介電圖形與上述第二介電圖形包含一光敏材料。
在上述之半導體裝置中，較好為：更包含一晶片，上述晶片連接於上述封裝構件的一前面，其中上述聚合物又環繞上述晶片並接觸上述晶片的側壁。
在上述之半導體裝置中，較好為：上述半導體裝置是一分離的封裝體；上述聚合物形成一第一環狀物，上述第一環狀物環繞上述基板並接觸上述基板的側壁；上述第二介電圖形形成一第二環狀物，上述第二環狀物在上述第一環狀物的上方並對準於上述第一環狀物；以及上述第一環狀物與上述第二環狀物具有相互對準的外緣。
在上述之半導體裝置中，較好為：上述第一介電圖形與上述第二介電圖形是相互彼此分離。
在上述之半導體裝置中，較好為：上述第二介電圖形是與上述聚合物接觸。
本發明的另一實施例是提供一種半導體裝置，包含一晶圓、複數個第二晶片、一第一聚合物區、複數個導體構件以及一第二聚合物層。上述晶圓具有複數個第一晶片與複數個切割線，上述第一晶片具有複數個貫穿導通孔，上述貫穿導通孔是穿透上述晶圓的一半導體基板，上述切割線是將上述第一晶片彼此分離。上述第二晶片是位於上述晶圓的一前面的下方，並連接於上述晶圓的上述前面。上述一第一聚合物區具有複數個第一部分與複數個第二部分。上述第一部分是在上述切割線中，穿透上述晶圓並接觸上述半導體基板的側壁；上述第二部分，是與上述第二晶片在同一水平並環繞上述第二晶片。上述導體構件是在上述半導體基板的一背面上並電性連接於上述貫穿導通 孔。上述第二聚合物層具有複數個第三部分與複數個第四部分。上述第三部分是覆蓋上述導體構件的邊緣部；上述第四部分是位於上述第一聚合物區的上述第一部分的上方，並對準於上述第一聚合物區的上述第一部分。
在上述之半導體裝置中，較好為更包含：複數個凸塊下金屬(Under-Bump-Metallurgy；UBM)，位於上述導體構件的中央部的上方並與上述導體構件的上述中央部接觸；以及複數個接合物，在上述凸塊下金屬的上方並對準於上述凸塊下金屬。
在上述之半導體裝置中，較好為：上述第一聚合物區包含一封膠組合物，上述第二聚合物層包含一光敏材料。
在上述之半導體裝置中，較好為：上述第二聚合物層的上述第三部分與上述第四部分是彼此分離，且上述第二聚合物層的上述第三部分是形成複數個環狀物。
在上述之半導體裝置中，較好為：上述第二聚合物層的上述第四部分是與上述第一聚合物區的上述第一部分接觸。
在上述之半導體裝置中，較好為更包含一絕緣層，接觸上述半導體基板的一背面，其中上述第二聚合物層的上述第四部分較好是隔著上述絕緣層而與上述第一聚合物區的上述第一部分間隔、分離。
本發明的又另一實施例是提供一種半導體裝置的形成方法，包含：在一晶圓的複數個切割線形成複數個溝槽，其中上述溝槽從上述晶圓的一正面延伸至上述晶圓的一基板內；將一第一聚合物填入上述溝槽內；從上述基板的一 背面薄化上述基板，其中在薄化的步驟之後，曝露出上述第一聚合物與上述基板中的複數個貫穿導通孔；在上述晶圓的上述背面上形成複數個導體構件，上述導體構件電性連接於上述貫穿導通孔；在上述晶圓的上述背面上形成一第二聚合物層，上述第二聚合物層覆蓋上述導體構件；以及圖形化上述第二聚合物層，其中已圖形化的上述第二聚合物層的殘留部包含複數個第一部分與複數個第二部分，上述第一部分覆蓋上述導體構件的邊緣部，上述第二部分對準於上述溝槽中的部分的上述第一聚合物。
在上述之半導體裝置的形成方法中，較好為：上述第二聚合物層的上述第一部分形成複數個環狀物，上述環狀物彼此分離並與上述第二聚合物層的上述第二部分分離。
在上述之半導體裝置的形成方法中，較好為更包含：形成複數個凸塊下金屬(Under-Bump-Metallurgy；UBM)，上述凸塊下金屬延伸至上述第二聚合物層的上述第一部分內，並分別電性連接於下方的上述導體構件；以及在上述凸塊下金屬的上方形成複數個接合物，上述接合物並對準於上述凸塊下金屬。
在上述之半導體裝置的形成方法中，較好為更包含：在圖形化上述第二聚合物層的步驟之後，對上述晶圓執行一晶片切割步驟以形成一封裝體，其中在上述封裝體中，上述第一聚合物的一部分形成一第一環狀物，上述第一環狀物環繞上述晶圓的一第一晶片，上述第二聚合物層的上述第二部分則形成一第二環狀物，其中上述第一環狀物與上述第二環狀物的各自的外緣是相互對準。
在上述之半導體裝置的形成方法中，較好為：上述第一環狀物與上述第二環狀物的上述外緣是分別對準於上述封裝體的邊緣。
在上述之半導體裝置的形成方法中，較好為更包含：在將上述第一聚合物填入上述溝槽的步驟之前，將一第二晶片連接於上述晶圓上，其中上述第一聚合物還將上述第二晶片密封。
在上述之半導體裝置的形成方法中，較好為：上述第一聚合物具有一封膠組合物，而上述第二聚合物層具有一光敏材料。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：在各種例示的實施例中，提供晶片堆疊晶圓(Chip-on-Wafer；CoW)封裝體及其形成方法。形成上述晶片堆疊晶圓封裝體的中間步驟是繪示於圖式中。以下會討論到各種實施例，在各圖式中所示各實施例中，同類的元件符號是用來代表同類的元件。
第1至11b圖是一系列之剖面圖，顯示某些實施例之積體電路的封裝之中間階段。第1圖是顯示一封裝構件20的剖面圖，其可以是一裝置晶圓、一中介晶圓(interposer wafer)、或上述之類似物。封裝構件20包含一基板22。在某些實施例中，基板22是一半導體基板例如為一晶體矽基 板。此外，基板22可包含其他半導體材料例如矽鍺(silicon germanium)、碳矽(silicon carbon)、或其他複合物或半導體材料來取代前述晶體矽基板或與前述晶體矽基板結合。在某些替代性的實施例中，基板22是一介電質基板。封裝構件20可以是一裝置晶圓，其包含複數個主動裝置(未繪示)例如形成於半導體基板22的表面22A的複數個電晶體。在整篇本說明書中，表面22A與22B是分別稱之為基板22的一正面與一背面。當封裝構件20為一裝置晶圓時，其亦可包含複數個被動裝置(未繪示)例如為電阻器及/或電容器。在某些替代性的實施例中，封裝構件20是一中介晶圓，其內不含主動元件。在這些實施例中，在封裝構件20中可包含或未包含被動元件。
在本實施例中，可形成複數個基板貫穿孔(Through-Substrate Vias；TSVs)24，其從基板22的上表面22A延伸至基板22內，當基板22為一矽基板時，基板貫穿孔亦稱為矽貫穿孔(Through-Silicon Vias；TSVs)。封裝構件20包含複數個封裝組件40，這些封裝組件40可彼此相同。複數個切割線42是位於相鄰的封裝組件40之間。封裝組件40可以是裝置晶片、中介晶片或其類似物，在通篇說明書中，有時會將其稱之為晶片40來取代封裝組件40。
一內連線結構28是形成於基板22的上方，其是用來電性連接於封裝構件20中的積體電路裝置及/或基板貫穿孔24。內連線結構28可包含複數個介電層30，複數個金屬線32則形成於介電層30內，介層窗34則形成於其間， 使上下層的金屬線32相互連接。在某些情況下，金屬線32與介層窗34可稱之為重分布線(Redistribution Lines；RDLs)32/34。在某些實施例中，介電層30包含氧化矽、氮化矽、碳化矽、氧氮化矽或上述之組合。此外，介電層30可包含具有低介電常數之一層或多層的低介電常數介電層來取代前述介電材料。介電層30中的低介電常數介電材料的介電常數例如可低於3.0、或低於2.5。
複數個接合物38是形成於封裝構件20的上表面。在某些實施例中，接合物38是包含複數個金屬柱，其中軟銲蓋(solder caps)可形成於或未形成於上述金屬柱的上表面上。在某些替代性的實施例中，接合物38是包含複數個軟銲區；在其他實施例中，接合物38可以是複數個複合凸塊，其包含複數個銅柱、複數個鎳層、複數個軟銲蓋、及/或其類似物。
請參考第2圖，複數個封裝構件44是例如經由覆晶連接技術(flip-chip bonding)，而連接於封裝構件20。於是，接合物38將封裝構件44內的電路電性連接於封裝構件20內的重分布線32/34與基板貫穿孔24。封裝構件44可包含複數個裝置晶片，包含邏輯電路、記憶體電路、或其類似物。於是，在通篇說明書中，有時會將其稱之為晶片44來取代封裝構件44之名稱。此外，封裝構件44亦可包含其他結構來取代前述的晶片，例如封裝體，其包含連接於個別的中介物(interposer)、封裝基板、及/或其類似物之複數個晶片。在每個晶片40上，可能會有二或更多的晶片44連接於其上。
接下來，將聚合物45施加於晶片44與封裝構件20之間的空間(間隙)內。聚合物45可以是一底膠(underfill)，因此在後文中會稱之為底膠45，雖然其亦可包含其他聚合物例如環氧樹脂。底膠45亦可以是一模封底膠(molding underfill)。
請參考第3圖，對封裝構件20執行一開槽步驟(grooving step)，以形成複數個溝槽46，溝槽46是位於切割線42中。溝槽46的底部可與基板貫穿孔24的底部在實質上相同的水平上、或低於基板貫穿孔24的底部。溝槽46的寬度W1可介於例如約10 μm至約100 μm之間。溝槽46的寬度W1可小於或實質上等於切割線42的寬度W2。
接下來，如第4圖所示，例如使用壓塑法(compression molding)將一聚合物56模封在晶片44與封裝構件20上。在某些實施例中，聚合物56包含一封膠組合物(molding compound)、一環氧樹脂、或其類似物。聚合物56可包含複數個第一部分56A、複數個第二部分與複數個第三部分，其中第一部分56A填入溝槽46中並延伸到基板22中，第二部分填滿相鄰的晶片44之間的間隙，第三部分位於晶片44的上方。然後，將聚合物56熟化。請參考第5圖，在某些實施例中，在將聚合物56熟化之後，執行一平坦化步驟例如一研磨步驟，磨平聚合物56的上表面而成為同一水平，並移除聚合物56之位於晶片44上的部分。其結果，曝露出某些或所有的晶片44的上表面。在某些替代性的實施例中，未執行任何平坦化步驟。
第6至10圖是顯示封裝構件20的背面結構的形成。 首先，將第5圖所示封裝結構上下翻轉180度，而使半導體基板22面朝上。然後，經由例如一黏著劑60將一載體58貼附於上述封裝結構的底部。在某些例示的實施例中，載體58是一晶圓狀玻璃(glass wafer)。在某些例示的實施例中，黏著劑60可以是一紫外線黏膠(UV膠)。
請參考第7a與7b圖，對半導體基板22的背面執行一背面研磨步驟，將半導體基板22薄化，直到曝露出基板貫穿孔24。然後，將一或複數層的絕緣層62形成在半導體基板22的背面上，其中基板貫穿孔24延伸並穿透絕緣層62。絕緣層62是在將半導體基板22薄化之後形成，然後施行一化學機械研磨(Chemical Mechanical Polish；CMP)製程以曝露出基板貫穿孔24。絕緣層62亦可作為將半導體基板22隔離的一隔離層，絕緣層62的材料可包含氧化矽、氮化矽、或其類似物。用來形成絕緣層62的製程可包含低溫沉積製程。在某些實施例中，如第7a圖所示，是經由絕緣層62而曝露出聚合物56的第一部分56A；或如第7b圖所示，以絕緣層62覆蓋聚合物56的第一部分56A的結構取代第7a圖所示結構。
請參考第8圖，複數個導體構件64是形成於絕緣層62的上方並連接於基板貫穿孔24。導體構件64包含複數個重分布線與複數個導體墊。在某些實施例中，導體構件64包含鋁、銅、及/或類似物。在某些實施例中，導體構件64的形成是包含形成一毯覆層及圖形化此毯覆層。
接下來，如第9圖所示，形成介電圖形66A與66B。介電圖形66A與66B可包含一聚合物例如環氧樹脂、聚醯 亞胺(polyimide)、苯並環丁烯(Benzocyclobutene；BCB)、聚苯噁唑(polybenzoxazole；PBO)等等。介電圖形66A與66B亦可包含光敏性材料(例如聚苯噁唑或聚醯亞胺)。於是，介電圖形66A與66B的形成可包含塗覆一毯覆式的光敏材料，並對此光敏材料進行曝光與顯影。介電圖形66A與66B的材料可相對較軟以吸收應力。其他介電材料例如氧化物、氮化物、上述之組合、上述之層積層，亦可用來形成介電圖形66A與66B，取代前述聚合物。形成介電圖形66A與66B的製程分別包含低溫沉積製程，因此不會損及載體58。
在第9圖所示結構的俯視圖中，介電圖形66A可具有環形的形狀。介電圖形66B的部分結構是在聚合物56的第一部分56A的上方並對準於第一部分56A。此外，介電圖形66B的寬度W3可大於第一部分56A的寬度W1，並可分別延伸到第一部分56A的邊緣以外之處。於是，介電圖形66B可覆蓋整個聚合物56的第一部分56A。在第一部分56A穿透絕緣層62的實施例中，介電圖形66B是與聚合物56的第一部分56A接觸。在聚合物56的第一部分56A被絕緣層62覆蓋(第7b圖)的替代性實施例中，是隔著絕緣層62而使介電圖形66B與聚合物56的第一部分56A隔開、分離。介電圖形66A與66B的一例示的俯視圖是繪示於第12圖。
第10圖是顯示複數個接合物68的形成，接合物68是經由導體構件64的曝露的部分而電性連接於基板貫穿孔24。在某些實施例中，接合物68是複數個軟銲球。在其他 實施例中，接合物68可包含複數個金屬墊、複數個金屬凸塊、複數個軟銲蓋、或其類似物。例示的形成製程可包含：使用物理氣相沉積法(Physical Vapor Deposition；PVD)，毯覆性地形成一毯覆式的凸塊下金屬(under-bump-metallurgy；UBM)層(未繪示)；以及形成一罩幕(未繪示)，其中上述凸塊下金屬層之位於導體構件64的曝露部分的正上方的部分，是經由上述罩幕而被曝露，此時上述凸塊下金屬層的某些其他部分則被覆蓋。然後，將接合物68鍍在上述罩幕中的複數個開口內。然後，移除上述罩幕，執行一快速蝕刻(flash etch)步驟以移除未被接合物68覆蓋的凸塊下金屬層的曝露的部分，上述凸塊下金屬層的殘留部分稱之為凸塊下金屬67。在接合物68包含軟銲料的實施例中，可在鍍上接合物68後，進行一重流(reflow)的步驟。接合物68可用來連接於一附加的電性構件(未繪示)，此電性構件可以是一封裝基板、一印刷電路板(printed circuit board；PCB)、或上述之類似物。
然後，執行一晶片切割步驟，將封裝體70從第10圖所示的封裝結構分離。上述晶片切割是沿著切割線42進行。複數個切口(kerf)線69可以在聚合物56的第一部分56A(第10圖)的中間。所形成的封裝體70是示於第11a與11b圖，每個封裝體70是包含複數個晶片40中的一個與複數個晶片44中的一個。在晶片切割的步驟之後，如第11a與11b圖所示，有些第一部分56A會留在基板22的側壁上與介電層30的側壁上。亦有部分的介電圖形66B殘留在第一部分56A上並與聚合物部分56A對準，其中介電圖形66B 的外緣是對準於對應的第一部分56A的外緣。在第11a圖中，介電圖形66B是接觸聚合物56的第一部分56A的上表面；在第11b圖中，介電圖形66B是隔著絕緣層62而與聚合物56的第一部分56A間隔、分離。
第12圖是顯示封裝體70的俯視圖。介電圖形66B是形成一環狀物，其延伸至封裝體70的邊緣。介電圖形66B的邊緣是對準於聚合物56的第一部分56A的邊緣，聚合物56的第一部分56A亦形成一環狀物而環繞並接觸晶片40(請參考第1圖)。介電圖形66B除了覆蓋整個聚合物部分56A之外，亦可向封裝體70的中心的方向延伸而稍稍地超出聚合物56的第一部分56A的範圍。介電圖形66A亦可形成相互分離、且與介電圖形66B分離的複數個環狀物。每個介電圖形66A可形成一環狀物而分別覆蓋其下方的導體構件64的邊緣部分。
在本實施例中，介電圖形66B(第10圖)覆蓋聚合物56的第一部分56A。於是，在上述封裝製程中，例如在如第10圖所示之用以形成凸塊下金屬67的製程中，介電圖形66B避免了來自聚合物56的第一部分56A的釋氣(out-gassing)，因此減少了在形成凸塊下金屬67的過程中不希望發生的再沉積之情況。
本發明的一實施例是提供一種半導體裝置，包含一封裝構件、一貫穿導通孔、一導體構件、一第一介電圖形、一凸塊下金屬(Under-Bump-Metallurgy；UBM)、一聚合物以及一第二介電圖形。上述封裝構件包含一基板，其中上述基板包含一正面與在上述正面上的一背面。上述貫穿導 通孔是穿透上述基板。上述導體構件是在上述基板的上述背面的上方，並電性連接於上述貫穿導通孔。上述第一介電圖形是形成一環狀物，上述環狀物覆蓋上述導體構件的邊緣部。上述凸塊下金屬是位於上述導體構件的一中央部的上方，並與上述導體構件的上述中央部接觸。上述聚合物是接觸上述基板的一側壁上述第二介電圖形是在上述聚合物的上方並對準於上述聚合物，其中上述第一介電圖形與上述第二介電圖形是由相同的介電材料形成且置於實質上同一水平。
本發明的另一實施例是提供一種半導體裝置，包含一晶圓、複數個第二晶片、一第一聚合物區、複數個導體構件以及一第二聚合物層。上述晶圓具有複數個第一晶片與複數個切割線，上述第一晶片具有複數個貫穿導通孔，上述貫穿導通孔是穿透上述晶圓的一半導體基板，上述切割線是將上述第一晶片彼此分離。上述第二晶片是位於上述晶圓的一前面的下方，並連接於上述晶圓的上述前面。上述一第一聚合物區具有複數個第一部分與複數個第二部分。上述第一部分是在上述切割線中，穿透上述晶圓並接觸上述半導體基板的側壁；上述第二部分，是與上述第二晶片在同一水平並環繞上述第二晶片。上述導體構件是在上述半導體基板的一背面上並電性連接於上述貫穿導通孔。上述第二聚合物層具有複數個第三部分與複數個第四部分。上述第三部分是覆蓋上述導體構件的邊緣部；上述第四部分是位於上述第一聚合物區的上述第一部分的上方，並對準於上述第一聚合物區的上述第一部分。
本發明的又另一實施例是提供一種半導體裝置的形成方法，包含：在一晶圓的複數個切割線形成複數個溝槽，其中上述溝槽從上述晶圓的一正面延伸至上述晶圓的一基板內；將一第一聚合物填入上述溝槽內；從上述基板的一背面薄化上述基板，其中在薄化的步驟之後，曝露出上述第一聚合物與上述基板中的複數個貫穿導通孔；在上述晶圓的上述背面上形成複數個導體構件，上述導體構件電性連接於上述貫穿導通孔；在上述晶圓的上述背面上形成一第二聚合物層，上述第二聚合物層覆蓋上述導體構件；以及圖形化上述第二聚合物層，其中已圖形化的上述第二聚合物層的殘留部包含複數個第一部分與複數個第二部分，上述第一部分覆蓋上述導體構件的邊緣部，上述第二部分對準於上述溝槽中的部分的上述第一聚合物。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧封裝構件
22‧‧‧基板
22A‧‧‧表面
24‧‧‧基板貫穿孔
28‧‧‧內連線結構
30‧‧‧介電層
32‧‧‧重分布線(金屬線)
34‧‧‧重分布線(介層窗)
38‧‧‧接合物
40‧‧‧晶片(封裝組件)
42‧‧‧切割線
44‧‧‧晶片(封裝構件)
45‧‧‧底膠(聚合物)
46‧‧‧溝槽
56‧‧‧聚合物
56A‧‧‧第一部分
58‧‧‧載體
60‧‧‧黏著劑
62‧‧‧絕緣層
64‧‧‧導體構件
66A‧‧‧介電圖形
66B‧‧‧介電圖形
67‧‧‧凸塊下金屬
68‧‧‧接合物
69‧‧‧切口線
70‧‧‧封裝體
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧寬度
第1至11b圖是一系列之剖面圖，顯示某些實施例之積體電路的封裝之中間階段，其中：第1圖是顯示某些實施例之一封裝構件的剖面圖；第2圖是一剖面圖，顯示某些實施例之複數個第二封 裝構件連接於第一封裝構件；第3圖是一剖面圖，顯示某些實施例之對封裝構件執行一開槽步驟，以形成複數個溝槽；第4圖是一剖面圖，顯示在某些實施例中，將一聚合物模封在晶片與封裝構件上；第5圖是一剖面圖，顯示在某些實施例中，在將聚合物熟化之後，執行一平坦化步驟而磨平聚合物的上表面而成為同一水平；第6圖是一剖面圖，顯示在某些實施例中，將第5圖所示封裝結構上下翻轉180度，然後將一載體貼附於上述封裝結構的底部；第7a與7b圖是一系列之剖面圖，顯示在某些實施例中，對半導體基板的背面執行一背面研磨步驟而將半導體基板化，直到曝露出基板貫穿孔後，將一或複數層的絕緣層形成在半導體基板的背面上，其中基板貫穿孔延伸並穿透絕緣層，其中第7a圖是顯示經由絕緣層62而曝露出聚合物部分56A，第7b圖所示顯示以絕緣層62覆蓋聚合物部分56A；第8圖是一剖面圖，顯示在某些實施例中，複數個導體構件形成於絕緣層的上方並連接於基板貫穿孔；第9圖是一剖面圖，顯示在某些實施例中，形成複數個介電圖形；第10圖是一剖面圖，顯示在某些實施例中，複數個接合物68的形成；以及第11a與11b圖是一系列之剖面圖，顯示在某些實施 例中的封裝體。
第12圖是一俯視圖，顯示使用第1至11b圖所示製程形成的一封裝體。
22‧‧‧基板
24‧‧‧基板貫穿孔
28‧‧‧內連線結構
30‧‧‧介電層
40‧‧‧晶片(封裝組件)
44‧‧‧晶片(封裝構件)
56‧‧‧聚合物
56A‧‧‧第一部分
62‧‧‧絕緣層
64‧‧‧導體構件
66A‧‧‧介電圖形
66B‧‧‧介電圖形
67‧‧‧凸塊下金屬
68‧‧‧接合物
70‧‧‧封裝體

Claims (10)

  1. 一種半導體裝置，包含：一封裝構件，包含一基板，其中該基板包含一正面與在該正面上的一背面；一絕緣層，在該基板的該背面的上方；一貫穿導通孔，穿透該基板與該絕緣層；一導體構件，在該絕緣層的上方並電性連接於該貫穿導通孔；一第一介電圖形，其形成一環狀物，該環狀物覆蓋該導體構件的邊緣部；一凸塊下金屬(Under-Bump-Metallurgy；UBM)，位於該導體構件的一中央部的上方並與該導體構件的該中央部接觸；一聚合物，接觸該基板的一側壁；以及一第二介電圖形，在該聚合物的上方並對準於該聚合物，其中該第一介電圖形與該第二介電圖形是由相同的介電材料形成且置於實質上同一水平。
  2. 如申請專利範圍第1項所述之半導體裝置，更包含一晶片，該晶片連接於該封裝構件的一前面，其中該聚合物又環繞該晶片並接觸該晶片的側壁。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該半導體裝置是一分離的封裝體，其中該聚合物形成一第一環狀物，該第一環狀物環繞該基板並接觸該基板的側壁；該第二介電圖形形成一第二環狀物，該第二環狀物在 該第一環狀物的上方並對準於該第一環狀物；以及該第一環狀物與該第二環狀物具有相互對準的外緣。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該第一介電圖形與該第二介電圖形是相互彼此分離，該第二介電圖形是與該聚合物接觸。
  5. 一種半導體裝置，包含：一晶圓，其具有：複數個第一晶片，該些第一晶片具有複數個貫穿導通孔，該些貫穿導通孔是穿透該晶圓的一半導體基板；及複數個切割線，將該些第一晶片彼此分離；複數個第二晶片，位於該晶圓的一前面的下方並連接於該晶圓的該前面；一第一聚合物區，其具有：複數個第一部分，在該些切割線中，且穿透該晶圓並接觸該半導體基板的側壁；及複數個第二部分，與該些第二晶片在同一水平並環繞該些第二晶片；複數個導體構件，在該半導體基板的一背面上並電性連接於該些貫穿導通孔；以及一第二聚合物層，其具有：複數個第三部分，覆蓋該些導體構件的邊緣部；及複數個第四部分，位於該第一聚合物區的該些第一部分的上方並對準於該第一聚合物區的該些第一部分。
  6. 如申請專利範圍第5項所述之半導體裝置，其中該第二聚合物層的該些第三部分與該些第四部分是彼此分 離，且該第二聚合物層的該些第三部分是形成複數個環狀物。
  7. 如申請專利範圍第5項所述之半導體裝置，其中該第二聚合物層的該些第四部分是與該第一聚合物區的該些第一部分接觸。
  8. 如申請專利範圍第5項所述之半導體裝置，更包含一絕緣層，接觸該半導體基板的一背面，其中該第二聚合物層的該些第四部分是隔著該絕緣層而與該第一聚合物區的該些第一部分間隔、分離。
  9. 一種半導體裝置的形成方法，包含：在一晶圓的複數個切割線形成複數個溝槽，其中該些溝槽從該晶圓的一正面延伸至該晶圓的一基板內；將一第一聚合物填入該些溝槽內；從該基板的一背面薄化該基板，其中在薄化的步驟之後，曝露出該第一聚合物與該基板中的複數個貫穿導通孔；在該晶圓的該背面上形成複數個導體構件，該些導體構件電性連接於該些貫穿導通孔；在該晶圓的該背面上形成一第二聚合物層，該第二聚合物層覆蓋該些導體構件；以及圖形化該第二聚合物層，其中已圖形化的該第二聚合物層的殘留部包含複數個第一部分與複數個第二部分，該些第一部分覆蓋該些導體構件的邊緣部，該些第二部分對準於該些溝槽中的部分的該第一聚合物。
  10. 如申請專利範圍第9項所述之半導體裝置的形成方法，其中該第二聚合物層的該些第一部分形成複數個環狀 物，該些環狀物彼此分離並與該第二聚合物層的該些第二部分分離。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614848B (zh) * 2015-08-20 2018-02-11 矽品精密工業股份有限公司 電子封裝結構及其製法

Families Citing this family (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10297550B2 (en) 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US8557684B2 (en) * 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
US9782165B2 (en) 2011-11-11 2017-10-10 VentureMD Innovations, LLC Transosseous attachment
US10136883B2 (en) 2011-11-16 2018-11-27 VentureMD Innovations, LLC Method of anchoring a suture
US10548585B2 (en) 2011-11-16 2020-02-04 VentureMD Innovations, LLC Soft tissue attachment
US10675014B2 (en) 2011-11-16 2020-06-09 Crossroads Extremity Systems, Llc Knotless soft tissue attachment
US10470756B2 (en) 2011-11-16 2019-11-12 VentureMD Innovations, LLC Suture anchor and method
US8643148B2 (en) * 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
US8664040B2 (en) * 2011-12-20 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Exposing connectors in packages through selective treatment
US8987851B2 (en) * 2012-09-07 2015-03-24 Mediatek Inc. Radio-frequency device package and method for fabricating the same
US9136159B2 (en) * 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US10714378B2 (en) 2012-11-15 2020-07-14 Amkor Technology, Inc. Semiconductor device package and manufacturing method thereof
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9687221B2 (en) 2013-02-13 2017-06-27 Venture MD Innovations, LLC Method of anchoring a suture
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
WO2014196105A1 (ja) * 2013-06-03 2014-12-11 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9343431B2 (en) * 2013-07-10 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Dam structure for enhancing joint yield in bonding processes
US9368458B2 (en) * 2013-07-10 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Die-on-interposer assembly with dam structure and method of manufacturing the same
US20150014852A1 (en) * 2013-07-12 2015-01-15 Yueli Liu Package assembly configurations for multiple dies and associated techniques
US9478498B2 (en) * 2013-08-05 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Through package via (TPV)
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9252054B2 (en) 2013-09-13 2016-02-02 Industrial Technology Research Institute Thinned integrated circuit device and manufacturing process for the same
US9978637B2 (en) 2013-10-11 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
DE102014119308B4 (de) 2013-12-30 2021-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Zweischritt-Formmasse-Schleifen für Kapselungsanwendungen
US9209048B2 (en) * 2013-12-30 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Two step molding grinding for packaging applications
US9412662B2 (en) * 2014-01-28 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and approach to prevent thin wafer crack
US9406650B2 (en) 2014-01-31 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9917068B2 (en) * 2014-03-14 2018-03-13 Taiwan Semiconductor Manufacturing Company Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices
TWI548052B (zh) * 2014-04-22 2016-09-01 矽品精密工業股份有限公司 半導體中介板及封裝結構
KR20150123420A (ko) * 2014-04-24 2015-11-04 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조 방법
KR102258743B1 (ko) * 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
CN105304602A (zh) * 2014-07-18 2016-02-03 日月光半导体制造股份有限公司 半导体衬底、半导体封装结构及其制造方法
US20160071822A1 (en) * 2014-09-08 2016-03-10 International Business Machines Corporation OPTIMIZING POWER DISTRIBUTION FROM A POWER SOURCE THROUGH A C4 SOLDER BALL GRID INTERCONNECTED THROUGH SILICON VIAS IN INTERMEDIATE INTEGRATED CIRCUIT CHIP CONNECTED TO CIRCUITRY IN AN UPPER INTEGRATED CIRCUIT CHIP THROUGH A GRID OF MICRO uC4 SOLDER BALLS
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US9711474B2 (en) * 2014-09-24 2017-07-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure with polymeric layer and manufacturing method thereof
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
DE102014117594A1 (de) * 2014-12-01 2016-06-02 Infineon Technologies Ag Halbleiter-Package und Verfahren zu seiner Herstellung
US9443785B2 (en) * 2014-12-19 2016-09-13 Advanced Semiconductor Engineering, Inc. Semiconductor package
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
TWI778938B (zh) * 2015-03-16 2022-10-01 美商艾馬克科技公司 半導體裝置和製造其之方法
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10820918B2 (en) 2015-07-17 2020-11-03 Crossroads Extremity Systems, Llc Transosseous guide and method
US9962174B2 (en) 2015-07-17 2018-05-08 Kator, Llc Transosseous method
US10154868B2 (en) 2015-07-17 2018-12-18 Kator, Llc Transosseous method
US10226243B2 (en) 2015-08-04 2019-03-12 Kator, Llc Transosseous suture anchor
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US9818659B2 (en) * 2015-10-12 2017-11-14 Deca Technologies Inc. Multi-die package comprising unit specific alignment and unit specific routing
KR20170065397A (ko) 2015-12-03 2017-06-13 삼성전자주식회사 반도체 장치
US10020239B2 (en) * 2016-01-12 2018-07-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US9613895B1 (en) * 2016-03-03 2017-04-04 Inotera Memories, Inc. Semiconductor package with double side molding
US10062583B2 (en) 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
JP2018006591A (ja) * 2016-07-04 2018-01-11 ソニーセミコンダクタソリューションズ株式会社 半導体装置およびその製造方法、並びに電子機器
US10134708B2 (en) * 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
JP7035014B2 (ja) 2016-08-12 2022-03-14 コーボ ユーエス，インコーポレイティド 性能が強化されたウェハレベルパッケージ
EP3497717A1 (en) 2016-08-12 2019-06-19 Qorvo Us, Inc. Wafer-level package with enhanced performance
CN109716511A (zh) 2016-08-12 2019-05-03 Qorvo美国公司 具有增强性能的晶片级封装
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10141253B2 (en) 2016-11-14 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10418311B2 (en) * 2017-03-28 2019-09-17 Micron Technology, Inc. Method of forming vias using silicon on insulator substrate
US10515837B2 (en) * 2017-04-13 2019-12-24 Raytheon Company Method of wafer bonding of dissimilar thickness die
US10833021B2 (en) * 2017-06-29 2020-11-10 Alpha And Omega Semiconductor (Cayman) Ltd. Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer
US10403602B2 (en) * 2017-06-29 2019-09-03 Intel IP Corporation Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory
US10269587B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
DE102017122650B4 (de) * 2017-09-28 2023-02-09 Infineon Technologies Ag Halbleiterchip einschliesslich einer selbstausgerichteten rückseitigen leitfähigen schicht und verfahren zum herstellen desselben
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10510634B2 (en) 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
KR102072994B1 (ko) * 2017-12-06 2020-02-04 엘비세미콘 주식회사 사이드 몰딩을 이용한 반도체 패키지의 제조방법
EP3531446B1 (en) 2018-02-23 2024-04-03 Infineon Technologies Austria AG Semiconductor module, electronic component and method of manufacturing a semiconductor module
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
EP3818558A1 (en) 2018-07-02 2021-05-12 Qorvo US, Inc. Rf semiconductor device and manufacturing method thereof
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN113632209A (zh) 2019-01-23 2021-11-09 Qorvo美国公司 Rf半导体装置和其制造方法
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN112018054A (zh) * 2019-05-30 2020-12-01 意法半导体有限公司 具有在部分之间的电介质的半导体器件
TWI712135B (zh) * 2019-09-16 2020-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
CN113035823A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 封装结构
US11508692B2 (en) * 2019-12-25 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
CN113113402A (zh) * 2019-12-25 2021-07-13 盛合晶微半导体(江阴)有限公司 3dic封装结构及制备方法
CN114424323B (zh) * 2020-02-21 2022-08-09 新唐科技日本株式会社 单片化方法
US11393763B2 (en) * 2020-05-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (info) package structure and method
US11424191B2 (en) * 2020-06-30 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US11908831B2 (en) * 2020-10-21 2024-02-20 Stmicroelectronics Pte Ltd Method for manufacturing a wafer level chip scale package (WLCSP)
US11842935B2 (en) * 2021-02-18 2023-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a reconstructed package substrate comprising substrates blocks
CN113013076B (zh) * 2021-02-25 2022-06-10 长鑫存储技术有限公司 套刻标记的形成方法及半导体结构
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
US20220399269A1 (en) * 2021-06-09 2022-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit device and method
US20230154765A1 (en) * 2021-11-12 2023-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Oxygen-Free Protection Layer Formation in Wafer Bonding Process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603191B2 (en) * 2000-05-18 2003-08-05 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20090302448A1 (en) * 2008-06-05 2009-12-10 Cheng-Tang Huang Chip Stacked Structure and the Forming Method
TW201015687A (en) * 2008-10-02 2010-04-16 Siliconware Precision Industries Co Ltd Multi-chip stacked structure having through silicon via and fabrication method thereof
TW201119005A (en) * 2009-10-01 2011-06-01 Xintec Inc Chip package and fabrication method thereof

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
JP4298856B2 (ja) 1999-07-16 2009-07-22 浜松ホトニクス株式会社 半導体装置及びその製造方法
JP4087019B2 (ja) 1999-07-16 2008-05-14 浜松ホトニクス株式会社 半導体装置の製造方法
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6826830B2 (en) 2002-02-05 2004-12-07 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
KR100676039B1 (ko) * 2005-04-22 2007-01-30 스텝시스템주식회사 관통전극을 통해 웨이퍼 하면에 외부접속단자를 형성시킨웨이퍼 레벨 칩스케일 패키지 제조방법
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7157372B1 (en) * 2005-06-14 2007-01-02 Cubic Wafer Inc. Coaxial through chip connection
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US8581418B2 (en) * 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
CN102446886B (zh) * 2010-09-30 2014-10-15 中国科学院微电子研究所 3d集成电路结构及其形成方法
US8614488B2 (en) * 2010-12-08 2013-12-24 Ying-Nan Wen Chip package and method for forming the same
US8580683B2 (en) * 2011-09-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for molding die on wafer interposers
US8643148B2 (en) * 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
KR101918608B1 (ko) * 2012-02-28 2018-11-14 삼성전자 주식회사 반도체 패키지
US20140120657A1 (en) * 2012-10-30 2014-05-01 Apple Inc. Back Channel Etching Oxide Thin Film Transistor Process Architecture
US8618651B1 (en) * 2012-11-01 2013-12-31 Nvidia Corporation Buried TSVs used for decaps
US20140151895A1 (en) * 2012-12-05 2014-06-05 Texas Instruments Incorporated Die having through-substrate vias with deformation protected tips

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603191B2 (en) * 2000-05-18 2003-08-05 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20090302448A1 (en) * 2008-06-05 2009-12-10 Cheng-Tang Huang Chip Stacked Structure and the Forming Method
TW201015687A (en) * 2008-10-02 2010-04-16 Siliconware Precision Industries Co Ltd Multi-chip stacked structure having through silicon via and fabrication method thereof
TW201119005A (en) * 2009-10-01 2011-06-01 Xintec Inc Chip package and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614848B (zh) * 2015-08-20 2018-02-11 矽品精密工業股份有限公司 電子封裝結構及其製法

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