TW201015687A - Multi-chip stacked structure having through silicon via and fabrication method thereof - Google Patents

Multi-chip stacked structure having through silicon via and fabrication method thereof Download PDF

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TW201015687A
TW201015687A TW097137858A TW97137858A TW201015687A TW 201015687 A TW201015687 A TW 201015687A TW 097137858 A TW097137858 A TW 097137858A TW 97137858 A TW97137858 A TW 97137858A TW 201015687 A TW201015687 A TW 201015687A
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wafer
channel
pad
metal
layer
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TW097137858A
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Chinese (zh)
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TWI407540B (en
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Cheng-Jen Liu
Cheng-Chia Chiang
Jung-Pin Huang
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a multi-chip stacked structure having through silicon via and method of fabricating the same, comprising providing a wafer having a plurality first chips each formed with a through silicon via (TSV), the wafer and each first chip having corresponding first and second surfaces; forming a cutting groove on the first surface between each of the first chips; stacking at least one second chip on the first chip and electrically connecting the second chip to the through silicon via of the first chip; forming a molded compound layer on the wafer, each first chip and the first surface for covering the first surface, filling the cutting groove and enclosing the second chip; and thinning the second surface of the wafer to expose the metal pillar formed in the through silicon via therefrom and cutting the wafer to form individual chip structures. The invention does not require carrier boards and adhesive layers in the process of stacking and mounting chips, thereby simplifying the manufacturing process and reducing the cost as a result.

Description

201015687 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體I置及其製法，尤指一種 多晶片利用矽通道堆疊之結構及其製法。 ，【先前技術】 由於通訊、網路、及電腦等各式可攜式（pQrtaMe) 電子產品及其周邊產品輕薄短小之趨勢的日益重要且該 等電子產品係朝多功能及高性能的方向發展，以滿足半導 體封裝件高積集度（Integration)及微型化 (Miniaturization)的封裝需求，且為求提昇單一半導體 封裝件之性能UbiUty)與容量（eapaGity)以符合電子產 品小型化、大容量與高速化之趨勢，習知相半導體封裝 件多晶片模組化（Multi-chip Module ; MCM)的形式呈現， 以在單一封裝件之基板上接置至少二個以上之晶片。 習知多晶片'模組化之半導體封裝件係在一基板上以 ❹水平間隔方式排列多數晶片，並透過銲線而電性連接至該 基板，此種多晶片模組化之半導體封裝件主要缺點在於二 為避免晶片間之導線誤觸，須以一定之間隔來黏接各該晶 片，故若需黏接多數之晶片則需於基板上佈設大面積的晶 片接置區域（Die Attachment Area)以容設所需數詈 ΘΘ 片’此舉將造成基板使用面積及製程成本之增加。 另外美國專利第6, 538, 331號案則揭露以疊晶方式 (Stacked)將第一晶片及第二晶片疊接於基板上二=時^ 該疊接晶片係相對下層晶片偏位（〇ff_set)一段距離’以 111048 5 201015687 方便該第-及第二晶片分別打設薛線至該基板。 此方法雖可較則述以水平間隔方式排列多晶片之技 術即省基板空間，惟其仍須利用銲線技術電性連接晶片及 基板，使晶片與基板間電性連接品質易受鲜線之線長影響 而導致電性不佳，同時由於該些晶片於堆疊時須偏移一段 距離，且加上銲線設置空間之影響，依舊可能造成晶片堆 疊面積過大而無法容納更多晶片。 鑒於則述問題，美國專利US5, 270, 261 、 US5, 202, 754 ' US6, 903, 442 > US6, 809, 421 > US6, 642, 081 及fS6’465, 892揭露使用載板辅助堆疊晶片之技術，舉例 而δ，请參閱第ία至iG圖，美國專利US5, 27〇, 261及 5,202’754 揭露一種利用矽通道（Thr〇ugh SUic〇n Via， SV)技術以供複數半導體晶片垂直堆疊且相互電性連接 之結構及製法。 其製法主要係提供具相對第一表面ηι及第二表面 ❹112之第一晶圓Ua，該第一晶圓na包含有複數第一晶 片U，其中該第一表面11丨形成有複數孔洞11〇，並於該 孔洞11 〇中形成金屬柱丨3，以構成矽通道結構，及於該 金屬柱13外露端形成銲墊131 ,以將該第一晶圓lla第 表面111透過膠黏層141而黏置於一如玻璃之载板Hi 上俾藉由該载板151提供製程所需之支撐強度（如第 圖所示）；利用研磨作業，對該第一晶圓lla之第二表面 112進行薄化，以外露出該金屬柱13(如第1B圖所示）； 於外露出該第二表面112之金屬柱13上形成銲墊丨32, 111048 6 201015687 ^以供另一形成有矽通道之具複數第二晶片12之第二晶圓 12a藉由其矽通道之金屬柱16垂直接置並電性連接於該 第一晶圓11a之第二表面112上（如第lc圖所示）；接^ 重複前述製程，研磨薄化該具複數第二晶片12之笛一曰 _ 。心乐一日日201015687 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor I and its manufacturing method, and more particularly to a structure in which a multi-wafer is stacked using a meandering channel and a method of manufacturing the same. [Prior Art] Due to the increasing importance of the portable and (pQrtaMe) electronic products such as communication, networking, and computers, and their peripheral products, the trend is toward versatility and high performance. To meet the packaging requirements of semiconductor package high integration and miniaturization, and to improve the performance of single semiconductor package UbiUty) and capacity (eapaGity) to meet the miniaturization and large capacity of electronic products. The trend of high speed is in the form of a multi-chip module (MCM) of a semiconductor package to connect at least two or more wafers on a substrate of a single package. The conventional multi-chip 'modularized semiconductor package is a plurality of wafers arranged on a substrate in a horizontal interval, and is electrically connected to the substrate through a bonding wire. The main disadvantage of the multi-chip modular semiconductor package is In order to avoid mis-touching of the wires between the wafers, the wafers must be bonded at regular intervals. Therefore, if a large number of wafers need to be bonded, a large area of the Die Attachment Area should be disposed on the substrate. The required number of wafers is required. This will increase the substrate area and process cost. In addition, in U.S. Patent No. 6,538,331, the first wafer and the second wafer are stacked on the substrate in a stacked manner. The stacked wafer is offset from the lower wafer (〇ff_set). A distance of '111048 5 201015687 is convenient for the first and second wafers to be respectively set to the substrate. Although this method can save the substrate space by the technique of arranging the multi-wafer in a horizontally spaced manner, it is still necessary to electrically connect the wafer and the substrate by the bonding wire technology, so that the electrical connection quality between the wafer and the substrate is susceptible to the line of the fresh wire. Long-term effects lead to poor electrical performance, and because the wafers have to be offset by a certain distance during stacking, and the influence of the wire-arrangement space, the wafer stacking area may still be too large to accommodate more wafers. In view of the above-mentioned problems, U.S. Patent Nos. 5,270,261, 5,202,754, US 6, 903, 442 > US 6,809, 421 > US 6,642 081 and fS 6 '465,892 disclose the use of carrier-assisted stacking The technique of the wafer, for example, δ, see the ία to iG diagram, U.S. Patent Nos. 5, 27, 261, and 5,202 '754 disclose a technique for using a channel (Thr〇ugh SUic〇n Via, SV) for a plurality of semiconductor wafers. A structure and a method of vertically stacking and electrically connecting each other. The first wafer na includes a first wafer Ua having a first surface η1 and a second surface ❹112. The first wafer Nav includes a plurality of first wafers U, wherein the first surface 11 is formed with a plurality of holes 11〇. And forming a metal pillar 3 in the hole 11 以 to form a 矽 channel structure, and forming a pad 131 on the exposed end of the metal pillar 13 to pass the first surface 111 of the first wafer 11a through the adhesive layer 141 Adhering to a carrier plate Hi such as glass, the carrier plate 151 is used to provide the support strength required for the process (as shown in the figure); the second surface 112 of the first wafer 11a is performed by a grinding operation. Thinning, exposing the metal post 13 (as shown in FIG. 1B); forming a pad 丨32, 111048 6 201015687 ^ on the metal post 13 exposing the second surface 112 for another forming a meandering channel The second wafer 12a having the plurality of second wafers 12 is vertically connected to and electrically connected to the second surface 112 of the first wafer 11a (as shown in FIG. 1c); The above process is repeated, and the flutes of the plurality of second wafers 12 are thinned. Heart day

•圓12a，以外露出該矽通道之金屬柱16，及於該金屬柱 16外露端形成銲墊136(如第1D圖所示）；後續為供第一 及第二晶片11’12與外部裝置電性連接，需於該第一晶圓 11a之第一表面iU植設複數銲球，此時即需再利用=一 如玻璃之載板152以透過膠黏層142而將該第一及第二晶 圓Ua，12a黏置其上，且外露出該第一晶圓lla之第一表 面111(如第1E圖所示），俾於該第一晶圓第一表面^ 之銲墊131上植設銲球丨7(如第1F圖所示）；接著切割該 堆疊之第一及第二晶圓lla，12a，以形成複數個相互垂直 堆疊之第一及第二晶片1112,再經拾取及透過銲球P 而電性連接至基板18，以形成多晶片模組化之半導體封 ❹裝件（如第1G圖所示）。 然而於前述之製程中，須額外使用複數之載板 151,152，且將第一及第二晶圓Ua，12a多次反覆黏置於 載板151，152上，惟此不僅增加製程成本，亦造成製程複 ^性的提高，再者，若所使用之膠黏層141，142為例如環 氧樹脂（epoxy)之高分子材料時，於形成該銲墊131，136 所進行之濺鍍（sputtering)及後續之濕式蝕刻（str丨p)作 業，極易造成製程上之污染而致生產不易。 是以，如何解決上述習知多晶片模組化半導體裝襞件 7 111048 201015687 —於製程中所產生之問題，並開發 層之多曰Η +备黑u # 个肩使用載板及膠黏 ?〜片堆疊結構及其製法，以簡化製零 及避免因使用高分子膠黏層而發氏成本， 欲解決的課題。“㈣’實為目前亟 【發明内容】 提供繁述先前技術之缺點’本發明之-目的在於 =-=棗程中不須使用载板及膠黏層之具石夕通道之 夕日日片堆疊結構及其製法。 之且二Γ、Γ之，—目的在於提供-種製程簡單及低成本 之具矽通道之多晶片堆疊結構及其製法。 本發月之再一目的在於提供一種具石夕通道之多晶片 堆疊結構及其製法，避免因使用高分子勝黏層而發生污染 _問題。 為達上揭及其他目的，本發明揭露一種具石夕通道之多 晶片堆疊結構之製法，係包括提供具複數第一晶片之晶 ❹該晶圓及第一晶片具相對之第一及第二表面，該第一 S曰片之第一表面形成有複數孔洞，且該孔洞處形成金屬柱 及形成於該金屬柱上之銲墊以構成矽通道結構；於各該第 一晶片之間的第一表面形成切割槽；將至少一第二晶片堆 疊於該第一晶片上並電性連接至該第一晶片矽通道之銲 墊，於該晶圓及第一晶片之第一表面和該第二晶片上形成 模製化合物（molding compound)層，以覆蓋第一表面並填 充該切割槽及包覆該第二晶片；以及於該晶圓之第二表面 上薄化該晶圓至外露出該金屬柱。 8 111048 201015687 該製法可復包括：於該第一晶 金屬柱上植設録墊，接著於該銲塾上形二;=外= 行切割以分離各該第-晶片；接著，°字槽圖案=該晶圓進 =晶片透過該導電元件而接置並電性連接至晶片^ 於一態樣中，本發明之製法 衣法了包括在薄化該晶圓後， 第-表面上形成具有外露出第—晶片金屬柱和㈣ 槽之開口的第一絕緣層，並於該第一晶片金 =成銲塾底部金屬結構;接著於第一絕緣層上形成二 卜露出該銲墊底部金屬結構和切割槽之開口的第二絕緣 1並於該銲墊底部金屬結構上形成導電元件後，對該晶 圓進行切割以分離各該第一晶片。 另外’本發明之另-態樣中，該第二晶片中復形成有 矽通道，以供後續於平整化該第一模製化合物層，且令該 ❹第二晶片料道之金屬柱外露出該第—模製化合物層 後，使該第二晶片上堆疊及電性連接第三晶片。且視需要 於第-模製化合物層和該第三晶片上形成第二模製化合 物層，以包覆該第三晶片；或者該堆疊的第三晶片為經封 裝後的晶片。 在本發明之包括經堆疊的第三晶片的態樣中，於該第 二晶片外露之表面上形成具有外露出第二晶片金屬柱之 開口的第三絕緣層，接著，於該第二晶片金屬柱上之開口 處形成銲墊底部金屬結構之銲墊；以及於第三絕緣層上形 111048 9 201015687 /成具有外露出該銲墊底部金屬結構之開口的第四絕緣層。 之再亦可視需要於切割該晶圓之前，於該第一晶片 .有第四晶片，並使該第四晶片電性連接 強化整體結構之電性功能。冑由日日片數目之增加，以 堆疊ΪΠί法’本發明復揭示一種具梦通道之多晶片 #且,：一广具有相對之第一及第二表面的第-晶 ❹^二:成有複數個自第—表面延伸至第二表面 孔而處形成有金屬柱且於該金屬柱之第一表面 形成有銲㈣構成料道結構；第二晶片，係堆疊 執以第一晶片上並電性連接至該第一晶片梦通道之鋒 ==一模製化合物層，覆蓋該第-晶片之第-表面 並包覆該第二晶片。 通道之多晶片堆疊結構可復包括：銲墊，係形 成於該金屬柱於第二表面—端或形成於該第-晶片之第 ❹:表3過線路重佈置層（RDL)而連接至該第—晶片石夕通 t之/柱，導電70件，係植設於該第一晶片第二表面之 銲塾；以及晶片承载件，供堆疊之第二晶片及第-晶片透 f該導電70件而接置並電性連接至該晶片承載件。此外， 發月之夕阳片堆疊結構可視需要復包括形成於該第二 表面上外露出該鮮塾的第一絕緣層。 曰不同於則述於第二表面一端形成的銲墊，本發明之多 么2 —構可包括形成於該第二表面上具有外露出該 、 之開口的第一絕緣層；且形成於該金屬柱上之開口 111048 10 201015687 處之銲墊底部金屬結構；以及形成於 外露出該鋒塾底部金屬結構之開口的第一絕^層上具有 ' $ ^ 〜罘一絕緣層。 構^;於另冑施例中’該具⑪通道之多晶片堆疊社 •構復包括有第三晶片，係堆疊於該第二曰 隹宜、、，° .晶片中形成有石夕通道，以供與該第：曰二曰金且該第二 签一J，可視需要復包括形成於該 第模製化合物層上具有外露出該第一握制、 銲墊的第三絕緣層，或者更進 成：二層之 ^上八有外路出該銲墊之開口的第四絕緣層，其中，該 墊具有銲墊底部金屬結構。 、以知 片Γ桩又番一實施例中’該多晶片堆疊結構復包括有第四晶 片，係接置並電性連接至該第一晶片第二表面上a circle 12a, a metal post 16 exposing the crucible channel, and a solder pad 136 formed on the exposed end of the metal post 16 (as shown in FIG. 1D); followed by a first and a second wafer 11'12 and an external device For the electrical connection, a plurality of solder balls are implanted on the first surface iU of the first wafer 11a, and the first and the first are to be reused by the carrier plate 152 of the glass to pass through the adhesive layer 142. The two wafers Ua, 12a are adhered thereon, and the first surface 111 of the first wafer 11a is exposed (as shown in FIG. 1E) on the first surface of the first wafer. Deploying solder balls 7 (as shown in FIG. 1F); then cutting the stacked first and second wafers 11a, 12a to form a plurality of first and second wafers 1112 stacked vertically, and then picking up And electrically connected to the substrate 18 through the solder ball P to form a multi-chip modular semiconductor package (as shown in FIG. 1G). However, in the foregoing process, a plurality of carrier plates 151, 152 are additionally used, and the first and second wafers Ua, 12a are repeatedly adhered to the carrier plates 151, 152, which not only increases the process cost, but also causes The improvement of the process is further improved. If the adhesive layers 141 and 142 used are, for example, a polymer material of epoxy, the sputtering is performed on the pads 131 and 136. And the subsequent wet etching (str丨p) operation, it is easy to cause pollution on the process and the production is not easy. Therefore, how to solve the above-mentioned conventional multi-chip modular semiconductor device 7 111048 201015687 - the problems generated in the process, and the development of the layer of 曰Η + 备 black u # shoulder use carrier and adhesive? The chip stack structure and its manufacturing method are used to simplify the zeroing and avoid the cost of using the polymer adhesive layer and the cost to be solved. "(4)' is the current 亟 [Summary] Provides a description of the shortcomings of the prior art 'The present invention - the purpose is to =-= in the process of jujube without the use of the carrier and the adhesive layer Structure and its method. The purpose is to provide a multi-wafer stack structure with a simple process and a low cost, and a method for manufacturing the same. A further objective of the present month is to provide a stone eve. The multi-wafer stack structure of the channel and the manufacturing method thereof avoid the pollution caused by the use of the polymer layer. For the purpose of achieving the above, the present invention discloses a method for manufacturing a multi-wafer stack structure with a stone channel, including Providing a wafer having a plurality of first wafers, the first wafer and the first wafer having opposite first and second surfaces, the first surface of the first S wafer being formed with a plurality of holes, and the metal pillars are formed at the holes and formed a pad on the metal post to form a meandering channel structure; a first surface between each of the first wafers forming a cutting groove; stacking at least one second wafer on the first wafer and electrically connecting to the first a wafer a pad of the channel, forming a molding compound layer on the first surface of the wafer and the first wafer and the second wafer to cover the first surface and filling the cutting groove and coating the second wafer And thinning the wafer on the second surface of the wafer to expose the metal pillar. 8 111048 201015687 The method may include: implanting a recording pad on the first metal pillar, and then bonding the soldering pad Upper shape 2; = outer = row cutting to separate each of the first wafers; then, the groove pattern = the wafer is inserted into the wafer through the conductive member and electrically connected to the wafer in a state, The method of the present invention includes forming a first insulating layer having an opening exposing a first metal stem and a (four) trench on the first surface after thinning the wafer, and forming a solder on the first wafer a bottom metal structure; then forming a second insulating layer 1 on the first insulating layer exposing the opening of the metal structure of the pad and the opening of the cutting groove, and forming a conductive element on the bottom metal structure of the pad, the wafer is Cutting is performed to separate each of the first wafers. In another aspect of the invention, the second wafer is formed with a meandering channel for subsequently planarizing the first molding compound layer, and exposing the metal pillar of the second wafer track to the first After molding the compound layer, stacking and electrically connecting the second wafer to the third wafer, and forming a second molding compound layer on the first molding compound layer and the third wafer as needed to coat the a third wafer; or the stacked third wafer is a packaged wafer. In the aspect of the present invention comprising the stacked third wafer, forming a second exposed wafer on the exposed surface of the second wafer a third insulating layer of the opening of the metal post, and then a pad of the metal structure of the bottom of the pad is formed at the opening on the second metal post; and the upper insulating layer is formed on the third insulating layer 111048 9 201015687 / a fourth insulating layer of the opening of the metal structure at the bottom of the pad. The fourth wafer may be further disposed on the first wafer before the wafer is cut, and the fourth wafer is electrically connected to strengthen the electrical function of the overall structure.胄 By the increase of the number of Japanese films, the method of stacking ΪΠί法's invention reveals a multi-chip with a dream channel# and: a wide-numbered first- and second-surface first-crystal ❹^2: a plurality of metal pillars are formed from the first surface extending to the second surface hole and a solder (four) is formed on the first surface of the metal pillar to form a channel structure; and the second wafer is stacked on the first wafer and electrically A layer connected to the first wafer dream channel == a molding compound layer covering the first surface of the first wafer and covering the second wafer. The multi-wafer stack structure of the channel may further include: a solder pad formed on the second surface end of the metal post or formed on the third surface of the first wafer: Table 3 is a line repeating layer (RDL) connected to the a first wafer, a conductive member, a solder pad implanted on a second surface of the first wafer, and a wafer carrier for the stacked second wafer and the first wafer to transmit the conductive 70 And connected to and electrically connected to the wafer carrier. In addition, the stacking structure of the moon-shaped sunset sheet may optionally include a first insulating layer formed on the second surface to expose the fresh enamel. Unlike the solder pad formed at one end of the second surface, the second structure of the present invention may include a first insulating layer formed on the second surface having an opening exposing the opening; and formed on the metal pillar The upper opening 111048 10 201015687 is at the bottom of the metal structure of the pad; and the first layer formed on the opening of the metal structure of the front edge of the front has a '$^~罘-insulation layer. In another embodiment, the 11-channel multi-wafer stacking device includes a third wafer stacked on the second Changi, and a wafer channel formed in the wafer. Providing the second insulating layer and the second insulating layer J, which may be formed on the first molding compound layer to have a third insulating layer exposing the first holding and soldering pad, or Advance: The second layer has a fourth insulating layer that is externally out of the opening of the pad, wherein the pad has a pad bottom metal structure. In the embodiment, the multi-wafer stack structure further includes a fourth wafer attached and electrically connected to the second surface of the first wafer.

第四晶片電性連接至該第-晶片第二表面之銲墊。、W 本發明透過形成於晶圓和第一晶片 合物層包覆並保鳟笸- ΘΗ^ίπί_ ^ ο復卫保瘦第一曰曰片，利用該堆疊之晶圓和第一模 ❹•化合物層作為薄化晶圓或堆疊額外晶片時之承載架 構’避免習知於堆疊複數晶片及將該些晶片接置於晶片承 载件上時須多次使用載板及膠黏層，所產生的製程繁雜、 f本高以及可能遭受污㈣問題，此外，本發明利用薄化 晶圓後第二表面所顯露之切割槽圖案作為線路重佈置層 之辨識標記，更可提高線路重佈置之精密度和產品信賴 性。 、 施方式 施方 以下係藉由特定的具體實施例說明本創作之實 111048 11 201015687 式’所屬技術領域中具有通常知識者可由本說明書所揭示 之内容輕易地瞭解本創作之其他優點與功效。 μ 第一實施例 請參閱第2Α至2F圖，係為本發明之具矽通道之多晶 片堆疊結構及其製法第一實施例之示意圖。 ΜThe fourth wafer is electrically connected to the pads of the second surface of the first wafer. The present invention utilizes the stacked wafer and the first module by coating the wafer and the first wafer layer to cover and protect the first wafer. The carrier layer is used as a thinning wafer or a carrier structure for stacking additional wafers. It is known to use a carrier board and an adhesive layer multiple times when stacking a plurality of wafers and attaching the wafers to the wafer carrier. The process is complicated, f is high, and may be contaminated (4). In addition, the present invention utilizes the groove pattern revealed by the second surface after thinning the wafer as an identification mark of the line rearrangement layer, thereby improving the precision of the line rearrangement. And product reliability. The following is a description of the present invention by way of specific embodiments. 111048 11 201015687 The following general knowledge of the present invention can be easily understood by those of ordinary skill in the art. μ First Embodiment Referring to Figures 2 to 2F, there is shown a schematic diagram of a multi-chip stack structure having a meandering channel of the present invention and a first embodiment thereof. Μ

如第2Α圖所示，提供具複數第一晶片21之晶圓 21a，該晶圓21a及第一晶片21具相對之第一表面211 及第二表面212,該第一晶片21之第一表面211形成有 複數孔洞210，且該孔洞210處形成金屬柱23及形成於 該金屬柱23上之銲墊231以構成矽通道（TSV)結構，且利 用晶圓切割機（Dicing saw)在各該第一晶片21之間的第 一表面211形成有切割槽2120,切割槽212〇之深度可約 等於或大於金屬柱23之深度； 該矽通道之孔洞210與金屬柱23間係設有如二氧化 矽或氮化矽之絕緣層23”，且該絕緣層23”與金屬柱23間 ❹係設有如鎳之阻障層23,，而該金屬柱23之材質係選自 銅、金及鋁所組群組之一者。 如第2B圖所示，將至少一第二晶片22堆疊於該第一 晶片21上並電性連接至該第一晶片矽通道之銲墊23ι。 如第2C圖所示，於該晶圓2la及第一晶片21之第一 表面211和該第二晶片22上形成第一模製化合物 (molding (：0即01111(1)層25，以覆蓋第一表面2ιι並填充 該切割槽2120及包覆該第二晶片22。此外，可視需要 利用研磨法平整化該第一模製化合物層以得到平坦的表 111048 12 201015687 面。 «r 、赫圖所示，利用例如濕式#刻之化學㈣法、 入 1 meChniCal grinding)、化學機械研磨法（CMP) .磨:=法’例如，進行崎再施以化學： 如第2E圖所示，於該第一晶片21之第二表面犯 ❹金屬柱23上植設㈣如’或者，如第2E，圖所 二？η利用薄化晶圓後第二表面212所顯露之切割槽 圖案作為辨識標記，以濺鑛方式於該第一晶片21之 第=表面212上形成電性連接至該第一晶片21梦通道之 =柱23的線路重佈置層挪⑽），並於該線路重佈 撕之終端形成有銲墊23卜接著於該鮮墊231上 形成導電το件27 ’以及對該晶圓21a進行切割以分離各 該第曰曰片2卜由於本發明利用第二表面所顯露之切割 ❹槽圖案作為線路重佈置層之辨識標記，更可提高線路重佈 置之精密度和產品信賴性。 曰如第2F圖所示’進行拾取作業，以將經堆疊之第二 晶片22及第-晶片21透過該導電元件27而接置並電性 連接至晶片承載件28上。 此外’ 5月參閱第2G圖所顯示之該晶圓於第二表面的 局部示意圖’在本發明之㈣通道之多晶片堆疊結構製法 中’可復包括在形成導電^件27之前，於該晶圓化之 第二表面212上形成具有外露出該銲墊231和切割槽 111048 201015687 2120之開口的第一絕緣層225。 或者如第2G圖所示，可在薄化該晶圓後，於該第 212上形成具有外露出第-晶片21金屬柱23和切 2 2120之開口的第-絕緣層225，並於該第一晶片21 •柱23上之開口處形成銲墊底部金屬結構227(UBM); 於第、絕緣層225上形成具有外露出該鲜塾底部金屬結 構m和切割槽212G之開口的第二絕緣層226，且如圖 "〇開口可未覆盍該銲墊底部金屬結構227 ;在該輝 墊底部金屬結構227上形成導電元件27 ;以及對該晶圓 21a進行切割以分離各該第—晶片2卜在具有銲墊底部金 屬結構之另一具體實例中，如第2G”圖所示，該第二絕緣 = 226曰的開口面積可小於該銲墊底部金屬結構的面積，覆 盍該銲塾底部金屬結構的部分區域，吨升結構上的結合 強度和信賴性。 透過則述製法，本發明復揭示一種具矽通道之多晶片 ❹堆疊結構，係包括：第-晶片2卜該第-晶片21具有相 對之第-表面211及第二表面212，該第一表面211形成 有複數個自第一表面211延伸至第二表面212的孔洞 21〇,該孔洞210處形成有金屬柱23且於該金屬柱”於 第一表面211的一端形成有銲墊231以構成矽通道結構； 第二晶片22,係堆疊於該第一晶片21上並電性連接至該 第一晶片矽通道之銲墊231 ;以及第一模製化合物層25， 覆蓋該第一晶片21之第一表面211並包覆該第二晶片 22 〇 111048 14 201015687 . .本發明之該具矽通道之多晶片堆疊結構可復包括 ,有：有形成於該金屬柱23於第二表面212 —端的銲熱 (如第2F圖所示）或者在該第一晶片21之第二表面 .212上透過線路重佈置層2232而連接至該第一晶片u矽 -通道之金屬柱23的銲墊231(如第2E，圖所示）；以及 係植設於該第一晶…二表面212之辉： 以了，-態樣中第2 F圖所^本發明之該具石夕通 ❹：疊及：可復包括晶片承載件28，係供堆叠 、日曰2及第一晶片21透過該導電元件27而 並電性連接至該晶片承载件28。 晶片二=前述實施例之說明’本發明之具石夕通道之多 袅面二。冓’可如第2Η圖所示’復包括形成於該第二 上外露出該鮮墊231的第一絕緣層225。同樣 包括Π:態樣中’該具石夕通道之多晶片堆疊結構，亦可 Λ二絕❹該第一表面上具有外露出該金屬柱之開口的 〇播…曰，形成於該金屬柱上之開口處之銲墊 =以及形成於該第一絕緣層上具有外露出該銲二屬 金屬結構之開口的第二絕緣層（如第％，圖所示）。底4 法，：係二 二晶片堆疊至第二:第上形成切_^ 合物層，填充該切割槽並包覆第_表曰:上:士第-模製化 :和切_之製程。本發J二: 製化合物層作為薄化晶圓或堆疊額外晶片：之和承第= 111048 15 201015687 構，避免習知於堆疊複數晶片及將該些晶片接置於晶片承 載件上時須多次使用载板及膠黏層，所產生的製程繁雜、 成本高以及可能遭受污染等問題。 • 第二實施例 請參閱第3A至3F圖，係為本發明之具矽通道之多晶 片堆疊結構及其製法第二實施例之示意圖。同時為簡化本 圖示，本實施例中對應前述相同或相似之元件係採用相同 標號表示。 ® 本實施例之具♦通道之多晶片堆疊結構及其製法與 前述實施例大致相同，主要差異在於第二晶片中形成㈣ 通道’藉以於該第：晶片上垂直堆疊及電性連接第三晶 片，俾藉由晶片堆疊數目之增加以強化整體結構之電性功 如第3A圖所示，於具複數第-晶片21之晶圓2] 上，將至少一第二晶片22堆疊於該第一晶片2ι上並電1 連接至該第-晶片21 ♦通道之輝墊如，1中該 片22中形成有金屬柱223以構成矽通道。 / 一 * 如第3B圖所示，平整化該第一模製化合物層25, _ 令該第一晶片22梦通道之夺厘& 化合物層25;、之金屬柱酬露出該第一模〗 如第3C圖所示’利用例如濺鑛（事u 於外露之第二晶片心通道之金屬柱挪上方= 223、或者’請參考第_，亦可利㈣ : 二晶片22上形成電性連接至該第二晶片心夕通:二 111048 201015687 柱223的線路重佈置層2232 ,並於該線路重佈置層2232 之終端形成有銲墊2231。 此外，請參閱第3D圖之示例性說明，可視需要於該 外路之第二晶片22之金屬柱223上形成銲墊之前，於該 第一晶片22外露之表面上形成具有外露出第二晶片22 金屬柱223之開口及切割槽212〇之開口的第三絕緣層 228接著，於該第二晶片22金屬柱223上之開口處形成 ❹銲墊底部金屬結構之銲墊2231 ;以及於第三絕緣層 上形成具有外露出該銲墊底部金屬結構之開口及切割槽 2/20之開口的第四絕緣層229;或者，以第沭圖為例，s w選擇於該外露之第二晶片Μ之金屬柱223上开）成銲墊 2231後’於該第二晶片22外露之表面上形成具有外露出 該銲墊2231之開口的第三絕緣層228。 ，第3F圖所示，於銲墊2231上形成導電元件27， 將第三晶片26接置於該第二晶片22上，並電性連接至該 ❹第二晶片22之銲墊2231。 曰如第3G圖所示’於該第一模製化合物層25和該第三 曰曰片26上形成第二模製化合物層29，以包覆該第三晶片 26 ° 如第3H圖所示，於該晶圓21a之第二表面212上 化該晶圓21a至外露出第一晶片21之該金屬柱23。當 然’亦可視需要地於堆疊第三晶片之前即對該晶圓進行；As shown in FIG. 2, a wafer 21a having a plurality of first wafers 21 is provided. The wafer 21a and the first wafer 21 have a first surface 211 and a second surface 212 opposite to each other. The first surface of the first wafer 21 The 211 is formed with a plurality of holes 210, and the metal pillars 23 and the pads 231 formed on the metal pillars 23 are formed at the holes 210 to form a through-channel (TSV) structure, and each of the wires is used by a Dicing saw. The first surface 211 between the first wafers 21 is formed with a cutting groove 2120. The depth of the cutting groove 212 is about equal to or greater than the depth of the metal pillars 23; and the holes 210 and the metal pillars 23 of the crucible channel are provided with, for example, dioxide. An insulating layer 23" of tantalum or tantalum nitride, and a barrier layer 23 such as nickel is interposed between the insulating layer 23" and the metal pillar 23, and the material of the metal pillar 23 is selected from the group consisting of copper, gold and aluminum. One of the group groups. As shown in FIG. 2B, at least one second wafer 22 is stacked on the first wafer 21 and electrically connected to the pads 23 of the first wafer via. As shown in FIG. 2C, a first molding compound (molding (0: 01111 (1) layer 25) is formed on the first surface 211 of the wafer 21a and the first wafer 21 and the second wafer 22 to cover The first surface 2 is filled and filled with the cutting groove 2120 and the second wafer 22. Further, the first molding compound layer may be planarized by grinding to obtain a flat surface 111048 12 201015687 as needed. «r , Hertu As shown, for example, the wet chemical method (four) method, the 1 meChniCal grinding method, the chemical mechanical polishing method (CMP), the grinding:= method, for example, the re-application of chemistry: as shown in Fig. 2E, The second surface of the first wafer 21 is implanted on the metal pillar 23 (4) as 'or, as in FIG. 2E, the second surface 212 is used as the identification mark after the thinned wafer is exposed. Forming, on the first surface 212 of the first wafer 21, a line rearrangement layer (10) electrically connected to the first channel 21 of the dream channel = column 23, and re-wiring the line on the line The terminal is formed with a solder pad 23, and then a conductive τ member 27' is formed on the fresh pad 231 and The circle 21a is cut to separate each of the second sheets 2. Since the cutting groove pattern revealed by the second surface of the present invention is used as an identification mark of the line rearranging layer, the precision and product reliability of the line rearrangement can be improved. . The picking operation is performed as shown in Fig. 2F to connect and electrically connect the stacked second wafer 22 and the first wafer 21 through the conductive member 27 to the wafer carrier 28. In addition, a partial schematic view of the wafer on the second surface shown in FIG. 2G is performed in the method of the fourth embodiment of the multi-wafer stack structure of the present invention, which may be included in the formation of the conductive member 27 before the crystal A first insulating layer 225 having an opening exposing the pad 231 and the cutting groove 111048 201015687 2120 is formed on the rounded second surface 212. Or, as shown in FIG. 2G, after the wafer is thinned, a first insulating layer 225 having an opening exposing the metal pillar 23 of the first wafer 21 and the slit 2 2120 may be formed on the 212th layer, and a wafer 21 • a pad bottom metal structure 227 (UBM) is formed at the opening on the pillar 23; a second insulating layer having an opening exposing the fresh crucible bottom metal structure m and the cutting trench 212G is formed on the first insulating layer 225 226, and as shown in the figure, the opening may not cover the bottom metal structure 227 of the pad; forming a conductive element 27 on the bottom pad metal structure 227; and cutting the wafer 21a to separate the first wafer In another specific example having a metal structure at the bottom of the pad, as shown in FIG. 2G”, the opening area of the second insulation=226曰 may be smaller than the area of the metal structure at the bottom of the pad, covering the soldering ring. Partial area of the bottom metal structure, bonding strength and reliability in a ton-liter structure. The present invention discloses a multi-wafer ❹ stack structure having a ruthenium channel, comprising: a first wafer - the first wafer 21 has a relative first surface 211 and a second table The first surface 211 is formed with a plurality of holes 21 延伸 extending from the first surface 211 to the second surface 212. The hole 210 is formed with a metal pillar 23 and the metal pillar is at one end of the first surface 211. a pad 231 is formed to form a meandering channel structure; a second wafer 22 is stacked on the first wafer 21 and electrically connected to the pad 231 of the first wafer channel; and a first molding compound layer 25, Covering the first surface 211 of the first wafer 21 and coating the second wafer 22 〇 111048 14 201015687 . The multi-wafer stack structure of the 矽 channel of the present invention may further include: formed on the metal pillar 23 The heat of soldering at the end of the second surface 212 (as shown in FIG. 2F) or the metal of the first wafer u矽-channel through the line rearranging layer 2232 on the second surface .212 of the first wafer 21 a pad 231 of the pillar 23 (as shown in FIG. 2E, as shown); and a bristles implanted on the first surface 212 of the first crystal: in the second aspect of the invention, the apparatus of the invention Shi Xitong: stacking: may include a wafer carrier 28 for stacking, day 2 and first wafer 21 27 and the electrically conductive element is connected to the wafer carrier 28. Wafer II = Description of the foregoing embodiment 'The present invention has a plurality of 夕 通道 channels.冓' may include a first insulating layer 225 formed on the second surface to expose the fresh pad 231 as shown in Fig. 2 . Also included in the Π: the multi-wafer stack structure of the Shi Xi channel, or the sputum on the first surface having the opening of the metal pillar exposed, formed on the metal pillar a pad at the opening = and a second insulating layer (shown as %, shown) formed on the first insulating layer with an opening exposing the metal structure of the solder. The bottom 4 method: stacking the second and second wafers to the second: forming a layer of the cut layer on the first surface, filling the cutting groove and coating the first sheet: the top: the mold-molding: and the cutting process . The present invention J: The compound layer is used as a thinned wafer or an additional wafer is stacked: the same as the 111048 15 201015687 structure, avoiding the need to stack multiple wafers and attach the wafers to the wafer carrier The use of carrier plates and adhesive layers can cause problems such as complicated processes, high cost, and possible contamination. • Second Embodiment Referring to Figures 3A to 3F, there is shown a schematic view of a multi-chip stack structure having a meandering channel of the present invention and a second embodiment thereof. In the embodiment, the same or similar elements are denoted by the same reference numerals in the embodiment. The multi-wafer stack structure of the embodiment of the present invention is substantially the same as the foregoing embodiment, and the main difference is that a (four) channel is formed in the second wafer by which the third wafer is vertically stacked and electrically connected to the wafer. And enhancing the electrical work of the overall structure by increasing the number of wafer stacks. As shown in FIG. 3A, at least one second wafer 22 is stacked on the first wafer 22 having a plurality of wafers 21] The wafer 2 is connected to the first wafer 21 ♦ the channel of the wafer. For example, in the sheet 22, a metal pillar 223 is formed to form a crucible channel. / a * as shown in Figure 3B, planarizing the first molding compound layer 25, _ so that the first wafer 22 dream channel wins & compound layer 25;, the metal column reveals the first mode As shown in Fig. 3C, 'Using, for example, splashing (the above-mentioned metal column of the exposed second chip core channel is shifted above = 223, or 'Please refer to the first _, but also profitable (4): the second wafer 22 is electrically connected To the second wafer: 211010 201015687 The line 223 of the column 223 is rearranged by a layer 2232, and a pad 2231 is formed at the end of the line rearranging layer 2232. In addition, please refer to the exemplary description of FIG. 3D, visible An opening having an opening exposing the metal post 223 of the second wafer 22 and the opening of the cutting groove 212 is formed on the exposed surface of the first wafer 22 before the soldering pad is formed on the metal post 223 of the second wafer 22 of the external circuit. a third insulating layer 228, then a pad 2231 of a bottom pad metal structure is formed on the opening of the second pillar 22 on the metal pillar 223; and a metal structure is formed on the third insulating layer to expose the bottom of the pad The fourth insulation of the opening and the opening of the cutting groove 2/20 229; or, in the example of the second drawing, sw is selected on the exposed metal wafer 223 of the second wafer, and is formed into a bonding pad 2231, and then formed on the exposed surface of the second wafer 22 to have an external exposure. A third insulating layer 228 of the opening of the pad 2231. As shown in FIG. 3F, a conductive member 27 is formed on the pad 2231, and the third wafer 26 is placed on the second wafer 22 and electrically connected to the pad 2231 of the second wafer 22. For example, as shown in FIG. 3G, a second molding compound layer 29 is formed on the first molding compound layer 25 and the third die 26 to coat the third wafer 26° as shown in FIG. 3H. The wafer 21a is formed on the second surface 212 of the wafer 21a to expose the metal pillar 23 of the first wafer 21. Of course, the wafer can also be performed before the third wafer is stacked as needed;

晶片之第二表面上植設銲墊與導 111048 17 201015687 電元件，如第2E至2G,，hi张-^ *· ~ 圖所不，進行後續製程，並對該 .«分離各該第_晶片，以供堆φ之第一、第 — m過料電元件接置並電性連接至晶片承 =藉由第31圖說明本發明之另-具石夕通道之多 日日片堆疊結構，包括第一 B 夕 針之黛“。 該第一晶片21具有相 對之第一表面211及第二表面212,竽篦一矣6 有複數個自第一表面211 ^ 該第表面211形成 〇?ln 面211延伸至第二表面212的孔洞 第1：孔9洞210處形成有金屬柱23且於該金屬柱23之 形成右的一端形成有鲜塾231以構成石夕通道結構； &quot; 、之第二晶片22,係堆疊於該第一晶片21上 =性連接至該第-晶片21料道之鲜塾231;第一模 覆：：物f 25 ’覆盖該第一晶片21之第-表面211並包 外=山.^ 22’且令該第二晶片22石夕通道之金屬柱223 路出該第一模製化合物層25;銲墊23卜係形成於該第 ❹一晶片22上且電性連接至外露出該第-模製化合物層25 之第一晶片22石夕通道之金屬柱223;以及第三晶片％， 係接置於該第二晶片22上’並電性連接至該第二晶片U 上之銲墊231 〇 此外，於本發明中用以堆疊的晶片可為經過封裝之封 裳件，舉例而言，本發日种所堆疊之該第三晶片可為經球 柵陣列（BGA)封裝的晶片。 其次，於包含形成第三絕緣層或第四絕緣層的製法 中所得到的具;^通道之多晶片堆疊結構，將可復包括形 111048 18 201015687 ‘·=該第三絕緣層上具有外露出該銲墊之開口的第 ，=中’該銲墊具有銲墊底部金屬結構;或者:ί .路出該第-模製化合物層之辉塾 、有外 -部分結構係如第仙和3Ε圖所示，故由於，此 農_三實施你丨 身义 請參閱第4圖’係為本發明之具石夕通道之多 結構及其製法第三實施例之 :ι ❹士杳—/,丄 1J呀為間化本圖示， 表示應前述相同或相似之^件係制相同標號 大致相本同實施 復可接置至第二21之第二表_上 夕此认 日日片24，例如，於切割該晶圓21 片之二該第-晶片21之第二表面212上接置有第四.晶 矣而第四晶片24電性連接至第—晶片12第二 θ整體姓禮之鲜塾231，俾藉由晶片堆疊數目之增加以強化 整體結構之電性功能。 ，上所述之具體實_，僅係用則釋本發明之特點 1效’而非用以限定本發明之可實施範嘴，在未脫離本 二日士揭之精神與技術㈣下，任何運用本發明所揭示内 :而完成之等效改變及修飾’均仍應為下述之申請專利範 圍所涵蓋。 【圖式簡單說明】 第1A至1G圖係為習知美國專利仍5, 270, 261及 19 111048 201015687 藉由…⑽技術垂直堆_ 第2A至2謂係為本發明之多晶片堆疊結構及其製法 第一實施例之示意圖； 第3A至31圖係、為本發明之多晶片堆疊結構及其製法 第二實施例之示意圖；以及 第4 ®係為本發明之多晶片堆疊結構及其製法第三 實施例之示意圖。The second surface of the wafer is implanted with a pad and a conductor 111048 17 201015687 electrical components, such as 2E to 2G, hi---*· ~ Figure does not, follow-up process, and the separation of the The wafer is connected to the first and the m-th electrical components of the stack φ and electrically connected to the wafer carrier. The multi-day wafer stack structure of the present invention is illustrated by FIG. 31, including The first wafer 21 has a first surface 211 and a second surface 212 opposite to each other, and the first surface 211 has a plurality of surfaces 211 from the first surface 211. 211 extends to the hole of the second surface 212. The first hole 9 hole 210 is formed with a metal post 23 and the right end of the metal post 23 is formed with a fresh 塾 231 to form a stone channel structure; &quot; The second wafer 22 is stacked on the first wafer 21 and is connected to the fresh 231 of the first wafer 21; the first mold: the material f 25 ′ covers the first surface 211 of the first wafer 21 And the outer cover=mountain.^22' and the metal pillar 223 of the second wafer 22 is arranged to exit the first molding compound layer 25; the pad 23 is formed on the The first wafer 22 is electrically connected to the metal pillar 223 of the first wafer 22 which exposes the first mold compound layer 25; and the third wafer % is attached to the second wafer 22 And electrically connected to the pad 231 on the second wafer U. In addition, the wafer used for stacking in the present invention may be a packaged package, for example, the first stack of the present invention The three wafers may be a ball grid array (BGA) packaged wafer. Secondly, the multi-wafer stack structure obtained in the method for forming the third insulating layer or the fourth insulating layer may include a shape 111048 18 201015687 '·= the third insulating layer has an opening exposing the opening of the pad, and the middle pad has a pad bottom metal structure; or: ί. the first molding compound layer The 塾 塾 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 部分 部分 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于The third embodiment of the system of law: ι ❹士杳—/, 丄1J is the illustration of the interval, indicating that it should be The same reference numerals are used to form the same reference numerals to the second table of the second 21. This is the day of the day. For example, the second piece of the wafer is cut. - the fourth surface 212 of the wafer 21 is connected to the fourth wafer, and the fourth wafer 24 is electrically connected to the second wafer 231 of the first wafer 12, by the increase in the number of wafer stacks. Strengthening the electrical function of the overall structure. The specifics described above are only used to explain the characteristics of the present invention, but not to limit the implementation of the present invention, without departing from the second day. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are conventional US patents still 5, 270, 261 and 19 111048 201015687 by the (10) technology vertical stack _ 2A to 2 is the multi-wafer stack structure of the present invention and FIG. 3A to FIG. 31 are schematic diagrams showing a multi-wafer stack structure of the present invention and a second embodiment thereof; and a fourth wafer is a multi-wafer stack structure of the present invention and a method of fabricating the same A schematic diagram of a third embodiment.

【主要元件符號說明】[Main component symbol description]

Ha 第一晶圓 12a 第二晶圓 11 第一晶片 111 第一表面 112 第二表面 110 孔洞 12 第二晶片 13, 16 金屬柱 131,132,136 銲墊 141，142膠黏層 151，152 載板 17 鲜球. 18 基板 21 第一晶片 210 孔洞 111048 20 201015687 211 第一表面 212 第二表面 23 金屬柱 231 銲墊 23” 絕緣層 23’ 阻障層 2120 切割槽 22 第二晶片 ❹223 金屬柱 2231 銲墊 2232 線路重佈置層 24 第四晶片 25 第一模製化合物層 2 6 苐二晶片 27 導電元件 0 28 晶片承載件 29 第二模製化合物層 21 β 晶圓 225 第一絕緣層 226 第二絕緣層 227 銲墊底部金屬結構 228 第三絕緣層 229 第四絕緣層 21 111048Ha First Wafer 12a Second Wafer 11 First Wafer 111 First Surface 112 Second Surface 110 Hole 12 Second Wafer 13, 16 Metal Post 131, 132, 136 Pad 141, 142 Adhesive Layer 151, 152 Carrier Plate 17 Fresh Ball 18 substrate 21 first wafer 210 hole 111048 20 201015687 211 first surface 212 second surface 23 metal pillar 231 pad 23" insulating layer 23' barrier layer 2120 cutting groove 22 second wafer 223 metal column 2231 pad 2232 line Rearrangement layer 24 fourth wafer 25 first molding compound layer 2 6 second wafer 27 conductive element 0 28 wafer carrier 29 second molding compound layer 21 β wafer 225 first insulating layer 226 second insulating layer 227 soldering Pad bottom metal structure 228 third insulation layer 229 fourth insulation layer 21 111048

Claims (1)

201015687 十、申請專利範圍： 1· 一種具矽通道之多晶片堆疊結構之製法，係包括： 提供具複數第一晶片之晶圓，該晶圓及第一晶片 具相對之第一及第二表面’該第一晶片之第一表面形 成有複數孔洞，且該孔洞處形成金屬柱及形成於該金 屬柱上之銲墊以構成矽通道（TSV)結構； 於各該第一晶片之間的第一表面形成切割槽； 將至少一第二晶片堆疊於該第一晶片上並電性 連接至該第一晶片矽通道之銲墊； 於該晶圓及第一晶片之第一表面和該第二晶片 上形成第一模製化合物（molding c〇mp〇und)層，以覆 蓋第一表面並填充該切割槽及包覆該第二晶片；以及 於該晶圓之第二表面上薄化該晶圓至外露出該 金屬柱。 2. ❹ 3. 如申請專祕圍第丨項之具料道之多晶片堆疊結構 之製法，其中，該孔洞與金屬柱間復設有絕緣層，該 絕緣層與金屬柱間復設有阻障層。 如申請專利㈣第2項之初通道之多晶片堆疊㈣ 之製法’其中’該絕緣層為二氧化矽及氮化矽之其I :-者’該阻障層為鎳，該金屬柱之材質係選自銅 金及鋁所組群組之一者。 :::專利範圍第！項之具石夕通道之多晶 之製法，復包括： 於該第一晶片之第 表面所外露之金屬柱上植 111048 22 4. 201015687 设鋒墊，接著於該鋅塾上形成導電元件；以及 對該晶圓進行切割以分離各該第一晶片。 5.如申請專利範圍第4項之具破通道之多晶片堆疊結構 之製法，其中，該第一晶片之第二表面上之鲜塾係透 過線路重佈置層(RDL)而連接至該第一晶片矽通道之 金屬柱。 6. 如申請專利範圍第4或5項之具料道之多晶片堆疊 ❹ ❹ 結構之製法，復包括在形成導電元件之前，於該晶圓 之第二表面上形成具有外露出該銲塾和切割槽之開 口的第一絕緣層。 如申請專利範圍第1項之具料道之多晶片堆疊結構 :製法，復包括在薄化該晶圓後，於該第二表面上形 ^具有外露出第—晶片金屬柱和切割槽之開口的第 =緣層，並於該第-晶片金屬柱上之開口處形成錄 墊底部金屬結構（UBM); 於第一絕緣層上形虚且古·从# , 成具有外露出該銲墊底部金 屬、纟。構和切割槽之開口的第二絕緣層； 在該銲墊底部金屬結構上形成導電元件；以及 對該晶圓進行切割以分離各該第-晶片。 專2圍第7項之具♦通道之多晶片堆疊結構 的=:絕緣層的開口面積一墊 第4或7項之具碎通道之多晶片堆疊 構之1法，復包括將堆疊之第二晶片及第-晶片透 111048 23 9. 201015687 ' ιη 導電元件而接置並電性連接至晶片承載件上。 •C範圍第4或7項之具矽通道之多晶片堆疊 、。構之製法，復包括於切割該晶圓之前 μ ^ . 次步日日 性、車垃—面上接置有第四晶片，並使該第四晶片電 -性連接至該第一晶片第二表面之銲墊。 u· 一種具料道之多晶片堆疊結構之製法係包括： 提供具複數第-晶片之晶圓，該晶 具相對之第一及第二表面，該第一 第曰曰片 =有複數孔洞’且該孔洞處形成金屬柱及銲墊以構成 矽通道結構； 風 於各該第-晶片之間的第一表面形成切割槽； 一曰將至少一形成有矽通道之第二晶片堆疊於該第 aa片上並電性連接至該第一晶片矽通道之銲墊； 於該晶圓及第一晶片之第一表面和該第二晶片 上^第-模製化合物層，以覆蓋第—表面並填充該 切割槽； 、平整化該第-模製化合物層’且令該第二晶片矽 通道之金屬柱外露出該第一模製化合物層； 於該第二晶片外露之金屬柱上形成鲜塾·以及 於該第一晶片上接置第三晶片，並使該第三晶片 電性連接至該第二晶片上之銲墊。 12·如申請專利範圍第n項之具石夕通道之多晶片堆叠結 構之製法，復包括於該第一模製化合物層和該第三晶 片上形成第二模製化合物層’以包覆該第三晶片。 111048 24 201015687 · 13::2利=第太項之具梦通道之多晶片堆疊結 14如申咬蛮、該第二晶片為經封震後的晶片。 .構ΙΠ圍第11項之㈣通道之多晶片堆疊結 復包括於該外露之第二晶片之金屬柱上 第二晶片外露之表面上形成具有外露 出該銲墊之開口的第三絕緣層。 'tm!:11項之具♦通道之多晶片堆疊結 ❹卜露之第二晶片之金屬柱上形 露出第-：二=一晶片外露之表面上形成具有外 :第一曰曰片金屬柱之開口的第三絕緣層，接著，於 片金屬柱上之開口處形成銲塾底部金屬結 絕緣層上形成具有外露出該銲 墊底。卩金屬結構之開口的第四絕緣層。 1' =利範圍第&quot;項…通道之多晶片堆曼結 =法’復包括：於形成第—模製化合物層後，在 之該金屬柱。 -圓至外露出第一晶片 利範圍第11項之具石夕通道之多晶片堆疊結 法，其中’該孔洞與金屬_復設有絕緣層， 該絕緣層與金屬柱間復設有阻障層。 18.:申：專利範圍第17項之具料道之多晶片堆叠社 ，之^法，其巾’該絕緣層為二氧切及氮切之^ 之-者，該阻障層為鎳’該金屬桎 銅、金及鋁所組群組之一者。 貝保選自 111048 25 201015687 ^ .19.::;r::16 項―… 於該第一晶片之篦-矣&amp; #炉故# 第一表面所外露之金屬柱上植 &quot;又鲜墊，並於該銲墊上形成導電元件；以及 • 對該晶圓進行切割以分離各該第一曰 2°.:Γ:Γ:Γ19項之㈣通道之堆疊結 透過線路重佈置層而連接 f ❹ 屬柱。 币日日片矽通道之金 21. 如申請專利範圍第19 矗沾姓K具矽通道之多晶片堆 一構之I法，復包括將堆疊之 »贫一 SU4 即门示一日日月 第二曰曰片透過該導電元件而接置並電性連接至曰 片承載件上。 电戌逆接至曰日 22. 如申請專利範圍第u項之具 構之製法，其中，該M 一曰μ [ 夕曰曰月堆疊結 ^ 兮筮-曰Η &amp; 〇第一日日片上之銲墊係直接形成於 ❹ 該第一曰曰片矽通道之金屬柱上方。 23·如申請專利範圍第u ^ ^ 項之八矽通道之多晶片堆疊結 # ^ ^ ，該第二晶片上之銲墊係透過線路重 24 θ、㈣第二晶片@通道之金屬柱。 24· 一種具=道之多晶片堆疊結構，包括： 面 ^ ^該第一晶片具有相對之第一及第二表 表面二：：形成有複數個自第一表面延伸至第二 第一矣而二一^孔洞處形成有金屬柱且於該金屬柱之 、一端形成有銲墊以構成矽通道結構； 111048 26 201015687 第二晶片，係堆疊於該第一晶片上並電性 該第一晶片矽通道之銲墊；以及 連接至 第一模製化合物層，覆蓋該第一晶 • 並包覆該第二晶片。 乃之第一表面 .25.如申請專利範圍第24項之具矽通道之多 構，復包括有形成於該金屬柱於 疊、、，》 墊。 木一表面一端的銲 〇26·:申圍第24項之具梦通道之多晶片堆μ ;二:括有形成於該第一“之第二 路 墊。 接至該第—晶0通道之金屬柱的銲 ”申請專利範圍第25或26項之具 :=緣r括形成於該第二表面上外露心： 〇28:=:πγ7項之具梦通道之多晶片堆疊結 〇面之=括有導電元件’係植設於該第…第二表 29.:申::::圍第28項之具梦通道之多晶片堆疊&amp; 一/ 有晶片承載件’係供堆疊之第二晶片及第 日日片透過該導電元件而接署 日日片及第 承載件。 i疋件而接置並電性連接至該晶片 3〇.如申請專利範圍第28項之具碎 構，德白拓筮 _ ^之夕晶片堆疊結 上，丄二第四四二片接置於該第一晶片之第二表面 第四阳片電性連接至該第-晶片第二表面 111048 27 201015687 31.如申請專利範圍 構，復包括❹％ 項之”梦通道之多晶片堆疊結 復匕括形成於該第二表 * 之開口的第一解絡a 兩外露出該金屬柱 -料底部金屬屬往上之開口處之 構’以及形成於該第一 外露出該録熱麻如Α ' S上/、有 32·如申請專利範圍 妁第一絕緣層。 構，复中_ 4項之具矽通道之多晶片堆疊結 〇 廣，〇孔洞與金屬柱間復設有絕緣層，該絕緣 〇層與金屬柱間復設有阻障層。 ㉟純緣 33.如申請專利範圍第 槿項具矽通道之多晶片堆疊結 $其中，該絕緣層為二氧化石夕及氮化石夕之其中之一 ’該阻障層為鎳，該金屬柱之材質係選自銅及 鋁所組群組之一者。 及 34· -種具砍通道之多晶片堆叠結構係包括： 第一晶片，該第一晶片具有相對之第一及第二表 〇 ® ’該第-表面形成有複數個自第—表面延伸至第二 表：的孔洞，該孔洞處形成有金屬柱且於該金屬柱: 第一表面的一端形成有銲墊以構成矽通道結構； 形成有矽通道之第二晶片，係堆疊於該第一晶片 上並電性連接至該第一晶片矽通道之銲墊； 、第一模製化合物層，覆蓋該第一晶片之第一表面 並包覆該第二晶片，且令該第二晶片矽通道之金屬柱 外露出該第一模製化合物層； 知墊係形成於該第二晶片上且電性連接至外露 111048 28 201015687 出該第一模製化合物層之第二晶片矽通道之金屬 柱；以及 第二晶片’係接置於該第一晶上，並電性連接 至該第—晶片上之鲜塾。 .35.如申請專利範圍第34項之具矽通道之多晶片堆疊結 構，復包括形成於該第一模製化合物層上具有外露出 該第一模製化合物層之銲墊的第三絕緣層。 ❹36.如申請專利範圍第35項之具石夕通道之多晶片堆疊結 構，復包括形成於該第三絕緣層上具有外露出該銲墊 ^口的第四絕緣層，其中，該銲塾具有銲塾底部金 屬結構。 π:申Π利範圍第34項之具梦通道之多晶片堆叠結 冓，、中，該第三晶片為經封裝的晶片。 38·Γ:ΓΓ第34項…通道之多晶片堆叠 ❹層與金屬柱間復設有阻障層。 、、邑緣層，該絕 39.如申請專利範圍第38項之具矽 構，其中，該絕緣層為二氧化石夕及=夕晶片堆疊 者，該阻障層為鎳，該金屬柱之材t石夕之其中之. 鋁所組群組之一者。 負係選自鋼、金j 40·如申請專利範圍第^項之具 構，復包括有形成於該第一晶^之多晶片堆疊為 端的銲墊。 金屬挺於第二表面- 41.如申請專利範圍第34項之具石夕 、之多晶片堆疊結 111048 201015687 構，復包括有形成於該苐一 重佈置層而連接至該第〜曰曰曰 一表面透過線路 42.如申請專利範圍曰曰片之金屬桂的銲墊。 表面之料。電⑦件，係植設㈣第—晶片第 切.如申請專利範圍第42項之具 構，復包括有曰 八、夕晶片堆疊結 Λ —晶片透載件，係供堆疊之第：晶片及第 ❹承載件。 電70件而接置並電性連接至該晶片 〇 111048 30201015687 X. Patent Application Range: 1. A method for fabricating a multi-wafer stack structure having a channel, comprising: providing a wafer having a plurality of first wafers, the wafer and the first wafer having opposite first and second surfaces Forming a plurality of holes in the first surface of the first wafer, and forming a metal pillar and a pad formed on the metal pillar to form a buffer channel (TSV) structure; and between the first wafers Forming a cutting groove on a surface; stacking at least one second wafer on the first wafer and electrically connecting to the pad of the first wafer cassette; on the first surface of the wafer and the first wafer, and the second Forming a first molding compound layer on the wafer to cover the first surface and filling the dicing trench and coating the second wafer; and thinning the crystal on the second surface of the wafer The metal column is exposed to the outside. 2. ❹ 3. For the method of preparing a multi-wafer stack structure with a material channel of the essay item, wherein the hole and the metal column are provided with an insulating layer, and the insulating layer and the metal column are provided with a resistance Barrier layer. For example, the method of preparing a multi-wafer stack (4) of the channel at the beginning of the second item of the application (4), wherein the insulating layer is cerium oxide and tantalum nitride, and the barrier layer is nickel, the material of the metal pillar It is selected from one of the group of copper and aluminum. ::: Patent scope! The method for producing polycrystalline crystals of a stone-like channel, comprising: implanting a metal pillar exposed on a surface of the first wafer; 111048 22 4. 201015687 setting a front pad, and then forming a conductive element on the zinc crucible; The wafer is diced to separate each of the first wafers. 5. The method of fabricating a multi-wafer stack structure having a broken channel according to claim 4, wherein the fresh enamel on the second surface of the first wafer is connected to the first through a line rearrangement layer (RDL) The metal column of the wafer 矽 channel. 6. The method of fabricating a multi-wafer stacking structure according to claim 4 or 5, further comprising forming an exposed outer surface of the wafer on the second surface of the wafer before forming the conductive element A first insulating layer that cuts the opening of the trench. The multi-wafer stack structure of claim 1, wherein the method comprises: after thinning the wafer, forming an opening on the second surface to expose the first-grain metal pillar and the cutting trench a bottom edge layer, and a bottom pad metal structure (UBM) is formed on the opening on the first wafer metal pillar; the dummy layer is formed on the first insulating layer, and the bottom portion of the solder pad is exposed Metal, enamel. Forming and etching a second insulating layer of the opening; forming a conductive member on the bottom metal structure of the pad; and cutting the wafer to separate each of the first wafer. The second item of the seventh item is ♦ the channel of the multi-wafer stack structure =: the opening area of the insulating layer is a pad of the fourth or seventh item with a fragmented channel of the multi-stack stacking structure, including the second stack The wafer and the first wafer are permeable to the wafer carrier by 111048 23 9. 201015687 ' ιη conductive elements. • Multi-wafer stacking with a channel of item 4 or 7 of the C range. The method of fabricating the method includes: before the cutting of the wafer, a fourth step, a fourth wafer is attached to the surface of the vehicle, and the fourth wafer is electrically connected to the first wafer. Surface pad. u. A method for fabricating a multi-wafer stack structure comprising: providing a wafer having a plurality of wafer-to-wafers, the wafer having opposite first and second surfaces, the first wafer = having a plurality of holes And forming a metal pillar and a pad at the hole to form a meandering channel structure; forming a cutting groove on the first surface between the first wafers; and stacking at least one second wafer formed with the channel in the first layer Aa is electrically connected to the pad of the first wafer channel; the first surface of the wafer and the first wafer and the second wafer are coated with a compound layer to cover the first surface and fill The dicing groove; flattening the first molding compound layer ′ and exposing the first molding compound layer to the metal pillar of the second wafer 矽 channel; forming a fresh enamel on the exposed metal pillar of the second wafer And mounting a third wafer on the first wafer and electrically connecting the third wafer to the pads on the second wafer. 12. The method of fabricating a multi-wafer stack structure of the Shixi channel according to the nth aspect of the patent application, comprising forming a second molding compound layer on the first molding compound layer and the third wafer to coat the Third wafer. 111048 24 201015687 · 13::2 Lee = the first item of the dream channel multi-chip stacking junction 14 such as Shenbitan, the second wafer is the sealed wafer. The multi-wafer stacking of the (4) channel of the eleventh item is formed on the exposed metal post of the second wafer, and a third insulating layer having an opening exposing the pad is formed on the exposed surface of the second wafer. 'tm!: 11 items of ♦ channel multi-wafer stacking ❹ 之 之 之 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二The opening of the third insulating layer, and then forming a solder bump bottom metal junction insulating layer on the opening on the sheet metal pillar to form an exposed outer surface of the solder pad. a fourth insulating layer of the opening of the base metal structure. 1' = profit range &quot; item... channel multi-wafer stack = = 法 法 复 复 复 复 复 复 复 复 复 复 复 ’ ’ 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成- a multi-wafer stacking method with a Shiyue channel extending from the eleventh item of the first wafer, wherein the hole and the metal layer are provided with an insulating layer, and the insulating layer and the metal column are provided with a barrier Floor. 18.: Application: Patent No. 17 of the patented multi-chip stacking company, the method of which is characterized in that the insulating layer is dioxo and nitrogen-cut, and the barrier layer is nickel. One of the group of metal beryllium copper, gold and aluminum. Beibao is selected from 111048 25 201015687 ^ .19.::;r::16 items-...in the first wafer 篦-矣&amp;#炉故# The first surface is exposed on the metal column &quot; fresh a pad, and forming a conductive element on the pad; and • cutting the wafer to separate each of the first 曰2°.: Γ: Γ: Γ 19 (4) The stacked junction of the channel is connected to the line through the line rearrangement layer ❹ is a column. The currency of the film is the gold of the channel. 21. If the patent application scope is 19th, the method of multi-chip stacking of the K-channel is the I method, including the stacking of the poor one SU4. The two dies are connected and electrically connected to the cymbal carrier through the conductive element. The electric raft is reversed to the next day. 22. If the application method of the scope of the patent application is in the U, the M 曰μ [ 曰曰 曰曰 堆叠 ^ ^ 曰Η 曰Η 曰Η 曰Η 曰Η 曰Η 曰Η 曰Η 曰Η 曰Η 〇 〇 The pad is formed directly on the metal post of the first cymbal channel. 23. The multi-wafer stack junction # ^ ^ of the eight-channel channel of the patent application scope u ^ ^, the solder pads on the second wafer are through the line weight 24 θ, (4) the second wafer @ channel metal column. 24· A multi-wafer stack structure having a track, comprising: a surface of the first wafer having opposite first and second surface surfaces:: forming a plurality of surfaces extending from the first surface to the second first surface a metal pillar is formed at the hole and a solder pad is formed at one end of the metal pillar to form a meandering channel structure; 111048 26 201015687 a second wafer stacked on the first wafer and electrically electrically connected to the first wafer a pad of the channel; and a layer connected to the first molding compound covering the first crystal and covering the second wafer. The first surface. 25. The multi-layered structure of the channel of claim 24, which is formed on the metal column, and the pad. Soldering 一端 26 at one end of the surface of a wooden surface: a multi-chip stack μ of the dream channel of the 24th item; 2: including a second road pad formed in the first “the second channel of the first channel” Welding of metal posts" Patent application No. 25 or 26: = edge r formed on the second surface of the exposed heart: 〇 28: =: πγ7 of the dream channel multi-chip stacking knot surface = Included with the conductive element 'is implanted in the second ... 29..::::: The 28th dream channel multi-chip stack &amp; a / with wafer carrier 'for the second stack The wafer and the first day piece are connected to the day piece and the carrier by the conductive element. The device is connected and electrically connected to the chip 3〇. As claimed in the 28th article of the patent application, the white chip is stacked on the wafer stack, and the second and fourth plates are connected. The fourth positive electrode is electrically connected to the second surface of the first wafer to the second surface of the first wafer 111048 27 201015687 31. As claimed in the patent application, the multi-wafer stacking of the "dream channel" is included. Forming a first de-compression a formed in the opening of the second table*, exposing the structure of the metal pillar to the upper opening of the metal column, and forming the first outer portion to expose the recording heat 'S on /, there are 32 · as claimed in the scope of the first insulating layer. Structure, complex _ 4 of the multi-wafer stack with 矽 channel, the 〇 hole and the metal column is provided with an insulating layer, A barrier layer is further disposed between the insulating layer and the metal pillar. 35 pure edge 33. The multi-wafer stacking junction of the channel of the invention is in the form of a parallel channel, wherein the insulating layer is a dioxide dioxide and a nitride One of the 'the barrier layer is nickel, and the material of the metal column is selected from copper and aluminum. One of the group groups. and a multi-wafer stack structure having a chopping channel includes: a first wafer having a first and a second surface opposite to each other; a hole extending from the first surface to the second surface: a metal pillar is formed at the hole, and a metal pad is formed on the first surface of the first surface: a pad is formed at one end of the first surface to form a meandering channel structure; and a second wafer having a meandering channel is formed a solder pad stacked on the first wafer and electrically connected to the first wafer cassette channel; a first molding compound layer covering the first surface of the first wafer and covering the second wafer, and And exposing the first molding compound layer to the metal pillar of the second wafer 矽 channel; the shims are formed on the second wafer and electrically connected to the exposed 111048 28 201015687 to form the second layer of the first molding compound a metal post of the wafer 矽 channel; and a second wafer ′ is placed on the first crystal and electrically connected to the squid on the first wafer. 35. The 矽 channel of claim 34 Multi-wafer stack structure, complex a third insulating layer formed on the first molding compound layer and having a solder pad exposing the first molding compound layer. ❹36. The multi-wafer stack structure of the Shiyue channel as claimed in claim 35, The fourth insulating layer is formed on the third insulating layer to expose the soldering pad, wherein the soldering pad has a metal structure of the bottom of the soldering pad. π: the dream channel of the 34th item of the application The multi-wafer stack is formed, and the third wafer is a packaged wafer. 38 · Γ: ΓΓ 34th... The multi-wafer stack of the channel is provided with a barrier layer between the ruthenium layer and the metal pillar. The layer is the structure of claim 38, wherein the insulating layer is a dioxide dioxide and a wafer stacker, the barrier layer is nickel, and the metal pillar is a stone One of them. One of the group of aluminum groups. The negative system is selected from the group consisting of steel and gold. The method of claim 4 includes a pad formed at the end of the first wafer stack. The metal is stronger than the second surface - 41. As claimed in claim 34, there is a multi-chip stacking junction 111048 201015687 structure, which is formed in the stacking layer and connected to the first layer The surface is transmitted through the line 42. The metal pad of the ruthenium of the patent application range. Surface material. 7 pieces of electricity, the planting (4) the first - wafer cutting. If the application of the scope of the 42nd article, including the 曰 、 夕 晶片 wafer stacking Λ 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片Dijon carrier. 70 pieces of electricity are connected and electrically connected to the wafer 〇 111048 30
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US8962481B2 (en) 2011-11-30 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer structures and methods for forming the same
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