TWI479638B - 兩個或兩個以上晶粒之多晶粒面向下堆疊 - Google Patents
兩個或兩個以上晶粒之多晶粒面向下堆疊 Download PDFInfo
- Publication number
- TWI479638B TWI479638B TW101114250A TW101114250A TWI479638B TW I479638 B TWI479638 B TW I479638B TW 101114250 A TW101114250 A TW 101114250A TW 101114250 A TW101114250 A TW 101114250A TW I479638 B TWI479638 B TW I479638B
- Authority
- TW
- Taiwan
- Prior art keywords
- microelectronic
- component
- opening
- edge
- front surface
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
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- H10W40/778—
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- H10W70/68—
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- H10W74/10—
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- H10W74/117—
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- H10W76/42—
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- H10W90/00—
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- H10W90/701—
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- H10W72/01—
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- H10W72/701—
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- H10W72/865—
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- H10W72/9445—
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- H10W90/24—
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- H10W90/288—
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- H10W90/291—
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- H10W90/732—
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- H10W90/734—
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- H10W90/754—
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161477877P | 2011-04-21 | 2011-04-21 | |
| US13/306,300 US8338963B2 (en) | 2011-04-21 | 2011-11-29 | Multiple die face-down stacking for two or more die |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201248829A TW201248829A (en) | 2012-12-01 |
| TWI479638B true TWI479638B (zh) | 2015-04-01 |
Family
ID=47020674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101114250A TWI479638B (zh) | 2011-04-21 | 2012-04-20 | 兩個或兩個以上晶粒之多晶粒面向下堆疊 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8338963B2 (enExample) |
| EP (1) | EP2700098A1 (enExample) |
| JP (1) | JP6033843B2 (enExample) |
| KR (1) | KR20140028014A (enExample) |
| CN (1) | CN103620773B (enExample) |
| TW (1) | TWI479638B (enExample) |
| WO (1) | WO2012145477A1 (enExample) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
| US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
| US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
| US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
| US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
| US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
| US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
| US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
| US8569884B2 (en) | 2011-08-15 | 2013-10-29 | Tessera, Inc. | Multiple die in a face down package |
| US8659141B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
| US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
| KR101894823B1 (ko) | 2011-10-03 | 2018-09-04 | 인벤사스 코포레이션 | 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화 |
| US8659143B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
| EP2769409A1 (en) | 2011-10-03 | 2014-08-27 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
| WO2013052544A1 (en) | 2011-10-03 | 2013-04-11 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
| US8659140B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
| US8704384B2 (en) | 2012-02-17 | 2014-04-22 | Xilinx, Inc. | Stacked die assembly |
| US8704364B2 (en) * | 2012-02-08 | 2014-04-22 | Xilinx, Inc. | Reducing stress in multi-die integrated circuit structures |
| US8957512B2 (en) | 2012-06-19 | 2015-02-17 | Xilinx, Inc. | Oversized interposer |
| US8869088B1 (en) | 2012-06-27 | 2014-10-21 | Xilinx, Inc. | Oversized interposer formed from a multi-pattern region mask |
| US9026872B2 (en) | 2012-08-16 | 2015-05-05 | Xilinx, Inc. | Flexible sized die for use in multi-die integrated circuit |
| US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
| US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
| US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
| US8946901B2 (en) | 2013-01-22 | 2015-02-03 | Invensas Corporation | Microelectronic package and method of manufacture thereof |
| US8907500B2 (en) | 2013-02-04 | 2014-12-09 | Invensas Corporation | Multi-die wirebond packages with elongated windows |
| US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
| US9547034B2 (en) | 2013-07-03 | 2017-01-17 | Xilinx, Inc. | Monolithic integrated circuit die having modular die regions stitched together |
| JP2015216263A (ja) * | 2014-05-12 | 2015-12-03 | マイクロン テクノロジー, インク. | 半導体装置 |
| US9915869B1 (en) | 2014-07-01 | 2018-03-13 | Xilinx, Inc. | Single mask set used for interposer fabrication of multiple products |
| US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
| US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
| JP2016071269A (ja) * | 2014-09-30 | 2016-05-09 | 株式会社東芝 | 電子機器、及びシステム |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
| KR102517779B1 (ko) * | 2016-02-18 | 2023-04-03 | 삼성전자주식회사 | 리드 프레임 및 이를 포함하는 반도체 패키지, 반도체 패키지의 제조 방법 |
| US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
| KR102647423B1 (ko) * | 2019-03-04 | 2024-03-14 | 에스케이하이닉스 주식회사 | 와이어 본딩 연결 구조를 가지는 반도체 패키지 및 이를 포함하는 반도체 패키지 구조물 |
| US11532595B2 (en) | 2021-03-02 | 2022-12-20 | Micron Technology, Inc. | Stacked semiconductor dies for semiconductor device assemblies |
Citations (3)
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| US20070160817A1 (en) * | 2006-01-11 | 2007-07-12 | Samsung Techwin Co., Ltd. | Printed circuit board and method of manufacturing semiconductor package using the same |
| US20080093725A1 (en) * | 2006-10-18 | 2008-04-24 | Samsung Electronics Co., Ltd. | Semiconductor package preventing warping and wire severing defects, and method of manufacturing the semiconductor package |
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-
2011
- 2011-11-29 US US13/306,300 patent/US8338963B2/en active Active
-
2012
- 2012-04-19 JP JP2014506538A patent/JP6033843B2/ja not_active Expired - Fee Related
- 2012-04-19 EP EP12717551.1A patent/EP2700098A1/en not_active Withdrawn
- 2012-04-19 KR KR1020137030770A patent/KR20140028014A/ko not_active Withdrawn
- 2012-04-19 CN CN201280030798.3A patent/CN103620773B/zh not_active Expired - Fee Related
- 2012-04-19 WO PCT/US2012/034196 patent/WO2012145477A1/en not_active Ceased
- 2012-04-20 TW TW101114250A patent/TWI479638B/zh not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6199743B1 (en) * | 1999-08-19 | 2001-03-13 | Micron Technology, Inc. | Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies |
| US20070160817A1 (en) * | 2006-01-11 | 2007-07-12 | Samsung Techwin Co., Ltd. | Printed circuit board and method of manufacturing semiconductor package using the same |
| US20080093725A1 (en) * | 2006-10-18 | 2008-04-24 | Samsung Electronics Co., Ltd. | Semiconductor package preventing warping and wire severing defects, and method of manufacturing the semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6033843B2 (ja) | 2016-11-30 |
| KR20140028014A (ko) | 2014-03-07 |
| CN103620773A (zh) | 2014-03-05 |
| US8338963B2 (en) | 2012-12-25 |
| WO2012145477A1 (en) | 2012-10-26 |
| CN103620773B (zh) | 2016-08-17 |
| JP2014512694A (ja) | 2014-05-22 |
| TW201248829A (en) | 2012-12-01 |
| EP2700098A1 (en) | 2014-02-26 |
| US20120267798A1 (en) | 2012-10-25 |
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