TWI460826B - 記憶體單元,記憶體陣列,形成記憶體單元之方法,及形成垂直定向閘流體與垂直定向存取電晶體之共用摻雜半導體區域之方法 - Google Patents
記憶體單元,記憶體陣列,形成記憶體單元之方法,及形成垂直定向閘流體與垂直定向存取電晶體之共用摻雜半導體區域之方法 Download PDFInfo
- Publication number
- TWI460826B TWI460826B TW101104088A TW101104088A TWI460826B TW I460826 B TWI460826 B TW I460826B TW 101104088 A TW101104088 A TW 101104088A TW 101104088 A TW101104088 A TW 101104088A TW I460826 B TWI460826 B TW I460826B
- Authority
- TW
- Taiwan
- Prior art keywords
- access
- gate
- doped
- semiconductor regions
- control gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 128
- 238000000034 method Methods 0.000 title claims description 23
- 238000003491 array Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 43
- 239000012535 impurity Substances 0.000 claims description 33
- 239000012530 fluid Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims 1
- 238000012986 modification Methods 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 239000004020 conductor Substances 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000010953 base metal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66386—Bidirectional thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1027—Thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Thyristors (AREA)
Description
本文揭示之實施例涉及記憶體單元、記憶體陣列、形成記憶體單元之方法及形成一垂直定向閘流體與一垂直定向存取電晶體之一共用摻雜半導體區域之方法。
許多積體電路(IC)記憶體裝置習知包含靜態隨機存取記憶體(SRAM)。習知SRAM係基於四個電晶體記憶體單元(4T SRAM單元)或六個電晶體記憶體單元(6T SRAM單元),其等與習知記憶體元件(諸如互補金屬氧化物半導體(CMOS)裝置)相容、以低電壓位準操作且以相對高速度執行。然而,習知SRAM消耗限制SRAM之高密度設計之一大單元面積。
嘗試減小IC記憶體裝置之面積,已製作通常稱為一「薄電容耦合閘流體(TCCT)」之包含四層交替n型及p型半導體材料之高密度低電壓SRAM單元。如本文使用,術語「閘流體」意指且包含一雙穩態三終端裝置,該裝置包含一四層結構,其包含以一p-n-p-n組態配置之一p型陽極區域、一n型基底、一p型基底及一n型陰極區域。該閘流體可包含兩個主終端(一陽極及一陰極)。此外,通常稱為「閘極」之一控制終端可操作相鄰於與該陰極最近的p型材料。基於閘流體之隨機存取記憶體(T-RAM)單元相比於習知SRAM單元顯示較快切換速度及較低操作電壓。
可藉由對閘極加偏壓使得一p-n-p-n通道傳導一電流而接
通一記憶體裝置中之一閘流體。一旦接通該裝置,(通常稱為「閂鎖」),該閘流體不需要對該閘極加偏壓來維持陰極與陽極之間傳導的電流。替代之,其將繼續傳導直到該陽極與陰極之間不再維持一最小保持電流或直到該陽極與該陰極之間之電壓反轉。因此,該閘流體可作用為能夠在一「導通」狀態及一「關斷」狀態之間切換之一開關或二極體。
首先關於圖1及圖2之一記憶體單元10描述根據本發明之記憶體單元之一些實例實施例。在一實施例中,此包括至少一閘流體12及至少一垂直定向存取電晶體14。
可相對於可係同質或非同質之一適宜基底基板(未展示)(舉例而言,包括多個不同組合物材料及/或層)製作記憶體單元10。如一實例,此可包括大塊單晶矽及/或一絕緣體上半導體基板。如一額外實例,此可包括其中形成有導電接觸件或通孔之介電材料,該等導電接觸件或通孔垂直或以其他方式延伸進入而與高度上不超過該介電材料之收納的電子裝置組件、區域或材料電流導電電連接。在此文件中,垂直係大致上與一主表面正交之一方向,在製作期間相對於該主表面處理一基板且該主表面可考慮定義一大致上水平方向。此外,如本文使用的「垂直」及「水平」係大致上獨立於在三維空間中該基板之定向之相對於彼此之垂直方向。此外,在此文件中,「高度」及「高度上」係參考與其上製作電路之該基底基板之垂直方向。該
基底基板可係或不是一半導體基板。在此文件中,定義術語「半導體基板」或「半導電基板」意指包括半導電材料之任何構造,包含(但不限於)大塊半導電材料(諸如一半導電晶圓(單獨或在包括其上之其他材料之組裝中))及半導電材料層(單獨或在包括其他材料之組裝中)。術語「基板」指任何支撐結構,包含(但不限於)上文描述的該等半導電基板。
閘流體12可包括複數個交替摻雜垂直疊加半導體區域15、16、17及18。垂直定向存取電晶體14可包括複數個交替摻雜疊加半導體區域18、19及20。因此,在一些實施例中,閘流體12與存取電晶體14共用該等交替摻雜疊加半導體區域之一者,舉例而言,圖1及圖2中之區域18。如本文使用,術語「垂直疊加」意指且包含高度上佈置在頂部或位於彼此上方之材料或區域。其等之橫向周邊可大致上一致。此外,「交替摻雜」意指且包含關於闡述的區域彼此相繼佈置之相對n及p導電率型。各別區域15至20之材料可係同質或非同質的且可包括任何現有或待發展的半導體材料。結晶矽材料、矽鍺材料、砷化鎵材料及/或氮化鎵材料係一些實例。
半導體區域15、18及20可「高摻雜」至相同或不同各別n或p摻雜劑濃度。半導體區域16、17及19可不高摻雜且可具有相同或不同摻雜劑濃度。如本文使用,術語「高摻雜」意指且包含相比於未高摻雜的材料或區域具有一摻雜劑之一較高濃度之一材料或區域。關於閘流體12,區域15
可係一p型陽極區域、區域16可係一n型基底區域,區域17可係一p型基底區域,且區域18可係一n型陰極區域。
在一實施例中,存取電晶體14具有一存取閘極22,該存取閘極操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域(舉例而言,如展示之區域19)。在至少存取閘極22與區域19之間收納一適宜閘極介電質24,在實例實施例中,該閘極介電質亦在共用區域18之一部分上延伸且在半導體區域20上橫向延伸。一控制閘極26與存取閘極22橫向間隔且操作地橫向相鄰於該等交替摻雜垂直疊加半導體區域之一者(舉例而言,如展示之非共用區域17)。在至少控制閘極26與半導體區域17之間收納一適宜閘極介電質28,在實例實施例中,閘極介電質28在共用半導體區域18上延伸且在半導體區域16上橫向延伸。閘極介電質24及28可係同質或非同質且具有相同或不同組合物。閘極22及26包括電流導電材料且可係同質或非同質。在此文件中,「電流導電材料」係一組合物,其中當產生亞原子正及/或負電荷時主要由該等電荷之移動將其中固有引起電流流動(與主要由離子之移動相反)。實例電流導電材料係基本金屬、基本金屬之合金、電流導電金屬化合物及導電摻雜半導電材料,包含其等之任何組合。
在一實施例中,該存取閘極及該控制閘極高度上重疊,且在一實施例中,高度上一致。在此文件中,若數個構造之一些各別部分高度上處於相同位準,則該等構造「高度上重疊」。若高度上重疊構造之高度上最外與最裡延伸區/
表面在高度上處於相同位準,則該等高度上重疊構造係「高度上一致」。
一電極30可與半導體區域15電流導電連接,且一電極32可與半導體區域20電流導電連接。每一者可包括電流導電材料且可係同質或非同質。
在本發明之一實施例中,一記憶體單元包括一垂直定向閘流體及操作地橫向相鄰於其之一控制閘極。此記憶體單元亦包含一垂直定向存取電晶體,其與該垂直定向閘流體橫向間隔且其與該垂直定向閘流體共用一摻雜半導體區域,該摻雜半導體區域在該垂直定向閘流體與該垂直定向存取電晶體之間橫向延伸。圖1及圖2中描繪的記憶體單元只不過係一此實例實施例。
在一實施例中,一垂直定向存取電晶體包括具有一對橫向對置側之一通道區域,該存取閘極操作地橫向相鄰於此等側之僅一者。記憶體單元10係一實例之此記憶體單元,其中半導體區域19包括具有一對橫向對置側35及37之一通道區域,存取閘極22操作地橫向相鄰於僅一側35。圖3描繪一替代實例實施例記憶體單元10a,其中存取閘極22及閘極介電質24經收納而操作地橫向相鄰於半導體區域19之僅一側37。
在一實施例中,操作地橫向相鄰於該控制閘極之該等交替摻雜垂直疊加半導體區域之一者具有一對橫向對置側,該控制閘極僅如此相鄰於此等側之一者。舉例而言,關於圖2中之記憶體單元10,半導體區域17具有一對橫向對置
側36及38,控制閘極26操作地橫向相鄰於僅該側38。圖3描繪一替代實例實施例,其中控制閘極26僅相鄰於一側36。圖1至圖3描繪只不過兩個實例實施例,其中閘極22及26僅在一通道區域之一各別側上。當然,存取閘極22在圖3中可替代地在側35上(未展示),或控制閘極26在圖3中可在側38上(未展示)。
在一實施例中,該存取閘極可包括一對此等閘極,每一對之一者經收納而操作地橫向相鄰於該通道區域之該對橫向對置側之一者。另外或替代地,該控制閘極可包括一對此等閘極,每一對之一者經收納而操作地橫向相鄰於該閘流體之該等垂直疊加交替摻雜半導體區域之一者之該對橫向對置側之一者。舉例而言,圖4描繪此一記憶體單元10b。在適當之處使用來自上文描述實施例之相同數字,用字母「b」展示一些構造差異。記憶體單元10b包含一對存取閘極22b及一對控制閘極26b。在一實施例中,存取閘極22b可硬佈線在一起。在一實施例中,控制閘極26b可硬佈線在一起。無論如何,可組合圖1及圖2實施例之任一者與圖3實施例,其中該存取閘極或控制閘極包括在對置橫向側上之一對此等閘極,另一者僅包括在僅一橫向側上之一單一閘極。
在一實施例中,一記憶體單元包括複數個交替摻雜疊加半導體區域,該等區域之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀。該等半導體區域集體包括該記憶體單元之一閘流體及一存取電晶體之可串聯電連
接部分且其等共用該等摻雜半導體區域之一者。一存取閘極操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域。一控制閘極操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域。僅舉例而言,如展示及描述之圖1至圖4之實施例之任一者係此等實例記憶體單元。
舉例而言,關於描繪的記憶體單元,大致上用參考數字40指示半導體區域15至20之橫向橫截面中之一高度上內部向上引導容器形狀。在一實施例中且如展示,該向上引導容器形狀係呈一大致U形狀之形式。可使用「V」及/或其他向上引導容器形狀。在一實施例中,該存取閘極橫向收納在該向上引導容器形狀內(即,圖1、圖2及圖4),且在一實施例中,不橫向收納在該向上引導容器形狀之外側(即,圖1及圖2)。在一實施例中,該存取閘極橫向收納在該向上引導容器形狀之外側(即,圖3及圖4),且在一實施例中,不橫向收納在該向上引導容器形狀內(即,圖3)。在一實施例中,該存取閘極包括一對存取閘極部分,其等之一者橫向收納在該向上引導容器形狀內且其等之另一者橫向收納在該向上引導容器形狀外側(即,圖4)。關於該存取閘極之剛剛描述的橫向定向之任一者或組合可另外或交替關於該控制閘極發生。
在一實施例中,該容器形狀(如一大致U形狀)具有一對垂直桿,具有在橫向橫截面中在該對垂直桿之間橫向延伸之一基底,該等桿之一者高於另一者。舉例而言,關於圖1至圖4之實施例,U形狀40可考慮為具有垂直桿41及43,
一基底44在垂直桿41與43之間橫向延伸。垂直桿41高於垂直桿43。替代地,僅舉例而言,各別桿之高度可反轉,藉此該存取電晶體之一桿43高於該閘流體之一桿41(未展示),或此等桿可具有相同高度/身高(未展示)。無論如何,可使用如上文描述的其他屬性。
本發明之實施例涵蓋包括一水平記憶體單元陣列之一記憶體陣列,一此實例記憶體陣列50包含參考圖5展示且描述之記憶體單元10。圖5中在適當之處使用來自圖1及圖2之相同數字,用不同數字指示一些構造差異及增加物。陣列50收納在一些適宜基底基板51上且包括在一第一方向「x」上之複數列52中及在相對於該第一方向「x」成角度之一第二方向「y」上之複數行54中實質上對齊之複數個閘流體12。在如展示之一實施例中,「x」與「y」垂直。該等閘流體之個別者包括複數個交替摻雜垂直疊加半導體區域(舉例而言,區域15至18)。
陣列50包含在第一方向「x」上之複數列56中及第二方向「y」上之複數行54中實質上對齊之複數個垂直定向存取電晶體14。因此,在一實施例中,閘流體行54及存取電晶體行54可係相同的。該等存取電晶體之個別者具有一存取閘極,該存取閘極包括定向在第一方向「x」上之複數列中之個別導電存取閘極線58之一部分。一控制閘極操作地橫向相鄰於該複數個閘流體12之個別者之該複數個垂直疊加交替摻雜半導體區域之一者,舉例而言,控制閘極26操作地橫向相鄰於各別半導體區域17。該等控制閘極之個
別者包括定向在第一方向「x」上之複數列中之個別導電控制閘極線60之一部分。在一實施例中,該等閘流體垂直高於該等存取電晶體。在一實施例中,該等存取閘極線與該等控制閘極線橫向間隔,且在一實施例中,在第二方向「y」上彼此交替橫跨水平陣列。在一實施例中,該等存取閘極線及控制閘極線高度上重疊,且在一實施例中高度上一致。無論如何,列、行及/或其中之線可係如展示之直線或曲線(未展示)。
複數個陰極線62在第一方向「x」上之複數列中實質上對齊,高度上超過存取閘極線58且高度上超過控制閘極線60。陰極線62可係同質或非同質且包括電流導電材料。複數個陽極線64在第二方向「y」上之複數行中實質上對齊,高度上超過控制閘極線60且高度上超過存取閘極線58。無論如何,線62及/或64可係如展示之直線或曲線(未展示)。
圖5描繪一實例實施例,其中陽極線64在高度上超過陰極線62。替代地該等陰極線可在高度上超過該等陽極線(未展示)。在一實施例中,該等陰極線在高度上超過該等垂直定向存取電晶體。在一實施例中,該等陽極線在高度上超過該等閘流體。可使用關於圖1及圖2或其他實施例之如上文描述的任何其他屬性。
圖6舉例而言僅描繪另一實例記憶體陣列50a,其包括圖3實施例之實例記憶體單元10a之一水平陣列。在適當之處使用來自圖3及圖5之實施例之相同數字。關於圖5之記憶
體陣列實施例之上文剛剛描述的屬性之任一者亦可用於圖6實施例中。
圖7描繪另一替代實施例記憶體陣列50b,其併入圖4之記憶體單元10b。在適當之處使用來自圖4及圖5實施例之相同數字。如一實例,控制閘極線60/26b及存取閘極線58/22b分別展示為相對於彼此硬佈線。圖7亦描繪一實例實施例,其中存取閘極線及控制閘極線橫向間隔開,該等存取閘極線及該等控制閘極線在第二方向「y」上成對交替橫跨水平陣列。關於圖5及圖6之陣列實施例之如上文描述的其他屬性可另外或替代結合圖7之陣列50b使用。
可藉由任何現有或待發展的方式製作記憶體單元及記憶體陣列之上文實施例。然而,本發明之實施例涵蓋形成可涵蓋或不涵蓋上文描述的結構屬性之一些之一或多個記憶體單元之方法。因此,本文提供的方法主旨不必要受結構主旨限制,也不是必定受可製作此(等)結構之方法限制的如剛剛描述的結構主旨。
本發明之一實施例涵蓋形成一記憶體單元之一方法,該記憶體單元包括一垂直定向閘流體及操作地橫向相鄰於其之一控制閘極。此記憶體單元亦包括與該閘流體共用一摻雜半導體區域之一垂直定向存取電晶體。僅參考圖8至圖21舉例而言描述關於製作圖5之陣列50之一此方法。因此,在適當之處使用來自圖1、圖2及圖5實施例之相同數字,用不同數字指示一些構造差異或構造先驅。圖8描繪一基板片段70,舉例而言,該基板片段包括一基底51,半
導體材料72形成在該基底上。渠溝73經蝕刻穿過半導體材料72,藉此材料72保留為定向在「y」方向上之平板或翼片。此展示為正矩形,但可替代或另外使用其他形狀,包含彎曲或弧形形狀。
參考圖9,已用平坦化回來之介電材料74填充間隙73。可使用任何適宜介電材料,摻雜或未摻雜二氧化矽、氮化矽等等係實例。可用於產生圖8之結構之任何遮罩材料(未展示)在圖9之結構中可收納在半導體材料72上。
參考圖10,基板70經正交圖案化至由圖8描繪之圖案,因而形成交替半導體材料及介電材料之區塊71,渠溝75(僅展示一個)形成在區塊71之間。
參考圖11,已用介電材料76填充渠溝75。實例包含關於介電材料74之上文描述的該等介電材料。在一實施例中,材料74及76可係相同組合物或至少能夠以相對於彼此之實質上相同速率蝕刻。無論如何,穿過圖11之處理描繪在一基板上形成半導體材料72之一區塊78之只不過一實例,展示多個此等區塊78。
參考圖12,已蝕刻至區塊78中以在關於個別區塊之橫向橫截面中形成半導體材料72之一向上引導容器形狀(在描繪的實施例中為一大致U形狀)。在其中該容器形狀係一大致U形狀之一實施例中,此具有一對垂直桿80,一基底82在此橫向橫截面中在該對垂直桿80之間橫向延伸。如一實例,適宜遮罩材料(未展示)可提供在圖12之結構之外表面上。可形成穿過其之開口,該等開口之橫向及徑向尺寸對
應於圖12中形成之該等渠溝(舉例而言,藉由蝕刻),以產生描繪的橫截面向上引導容器形狀。舉例而言,可進行蝕刻以留下自大約20奈米至50奈米之基底82之一厚度。可同時及/或循序蝕刻材料72及74。
參考圖13,桿80之間之基底82已用一第一類型的一導電率改質雜質離子植入至一第一雜質濃度,舉例而言,以包括區域18。在此離子植入期間可遮罩圖13結構之該容器形狀內之描繪的橫向面向內側壁及高度上外表面(未展示)。在此離子植入期間或之後,舉例而言,如展示,該導電率改質雜質可橫向擴展。在一實施例中,該第一類型係n,實例摻雜劑植入物種係磷及/或砷。替代地,該第一類型可係p,一實例摻雜劑植入物種係硼。
參考圖14,已在至少半導體材料72之面向內側壁上沈積閘極介電質24、28。此可係相同組合物或不同組合物。可藉由在該基板上沈積一層或如另一實例及如展示藉由熱氧化半導體材料72之暴露表面(舉例而言,包含描繪區域18之最上表面)之一者或兩者形成該閘極介電質。隨後,可沈積一電流導電材料以與描繪的開口對準且隨後經受一各向異性間隔物蝕刻以形成控制閘極線26/60及存取閘極線22/58。因此,一控制閘極經提供而操作地橫向相鄰於一桿80之一中間部分,且一存取電晶體之一存取閘極經提供而操作地橫向相鄰於另一桿80之一中間部分。閘極介電質24、28可暴露且蝕刻穿過閘極線26/60及22/58之間。此外,如展示,可高度上向內蝕刻及/或橫向下切下方之區
域18之半導體材料72。
參考圖15,介電質86經沈積以填充該等容器形狀之剩餘中心容積且隨後經平坦化回來。
參考圖16,該第一類型之一適宜導電率改質雜質植入已傳導至該對桿80之高度上最外部分中,因而形成實例半導體區域16。參考圖17,已遮罩至少此等區域16且該第一類型之一植入已傳導至各別對置桿中以形成存取電晶體14之半導體區域20。因此,以低於區域18內之該第一類型雜質濃度之該第一類型(區域16)之一第二雜質濃度提供該對桿80之一者之高度上最外部分(即此等桿對之左邊繪示的)。
高度上最外部分16、20與基底82/18之間之桿80之中間部分摻雜有不同於該第一類型且至一第三雜質濃度之一第二類型之一導電率改質雜質,舉例而言,以形成半導體區域17及19。在一實施例中且如一實例,區塊78之半導體材料72(圖11)可在圖11中且在整體摻雜有至該第三雜質濃度之該第二類型之導電率改質雜質之前提供。可藉由關於圖15、圖16及圖17之上文描述的處理以該第二類型之其他雜質濃度提供區域16、18及20。無論如何,區域16及/或20可在植入之前或之後摻雜有其等之各別導電率改質雜質濃度以產生區域18。
參考圖18,已形成陰極線62。可藉由任何適宜現有或待發展方式提供此,消減圖案化與蝕刻及/或鑲嵌式處理係實例。各別陰極線62可如展示硬佈線在一起。
參考圖19,已形成摻雜有至一第四雜質濃度之該第二類
型之一導電率雜質之半導體材料,其高度上超過且直接抵於左邊繪示的桿之高度上最外部分16,因而形成半導體區域15。在此文件中,當存在闡述材料或結構相對於彼此之至少一些實體觸摸接觸時,一材料或結構係「直接抵於」另一者。相比之下,「上方」涵蓋「直接抵於」以及其中介入材料或結構不引起該等闡述材料或結構相對於彼此之實體觸摸接觸之構造。該第四雜質濃度大於該第三雜質濃度。亦可藉由任何適宜現有或待發展方式(舉例而言,包含磊晶矽生長)形成半導體區域15。如另一實例,可沈積介電材料且隨後穿過其蝕刻接觸開口而呈區域15之形狀。此等開口隨後可填充或提供有適宜半導體材料,該半導體材料摻雜有至一期望第四雜質濃度之該第二類型之導電率雜質。
參考圖20,可形成與半導體區域15電流導電連接之陽極線64。在圖式中出於清楚在圖20中未展示高度上超過區域16、20之介電材料及其等之間之材料。
參考圖21,基板70已經受一適宜退火以付與共用區域18內之摻雜劑橫向向外的橫向擴散。在一實施例中且如展示,此擴散至桿80之橫向最外表面。由圖21描繪之處理可關於與圖14至圖20相關聯之上文處理而固有發生使得可不進行一專用退火步驟。替代地,舉例而言,如圖14中描繪,可不發生此橫向擴散使得完成的記憶體單元構造可具有很少或沒有橫向擴散。
可替代進行處理以產生如上文關於圖3至圖7描述之該等
記憶體單元或陣列構造之任一者,舉例而言,以提供如上文展示且描述之該等控制閘極及/或存取閘極之任一者。
本發明之一實施例包含形成一垂直定向閘流體及一垂直定向存取電晶體之一共用摻雜半導體區域之一方法。此方法包括在橫向橫截面中形成一大致U形狀半導體材料,此形狀具有一對垂直桿及在此橫向橫截面中在該對垂直桿之間橫向延伸之一基底。該基底在該等桿之間摻雜有n型及p型之至少一者之一導電率改質雜質,由其形成共用摻雜半導體區域。此摻雜可藉由離子植入或其他技術。
在一實施例中,在此摻雜期間可遮罩該等桿之橫向面向內側壁隔離此摻雜。在一實施例中,該共用摻雜半導體區域可經退火以使該導電率改質雜質橫向向外擴散至該等桿中,且在一實施例中擴散至該等桿之橫向最外表面之一程度。關於圖13至圖21之上文描述的處理只不過係此等實施例之一實例。
10‧‧‧記憶體單元
10b‧‧‧記憶體單元
12‧‧‧閘流體
14‧‧‧垂直定向存取電晶體
15‧‧‧半導體區域
16‧‧‧半導體區域
17‧‧‧半導體區域
18‧‧‧半導體區域
19‧‧‧半導體區域
20‧‧‧半導體區域
22‧‧‧存取閘極
22b‧‧‧存取閘極
24‧‧‧閘極介電質
26‧‧‧控制閘極
26b‧‧‧控制閘極
28‧‧‧閘極介電質/閘極
30‧‧‧電極
32‧‧‧電極
35‧‧‧側
36‧‧‧側
37‧‧‧側
38‧‧‧側
40‧‧‧U形狀
41‧‧‧垂直桿
43‧‧‧垂直桿
44‧‧‧基底
50‧‧‧記憶體陣列
50a‧‧‧記憶體陣列
50b‧‧‧記憶體陣列
51‧‧‧基底基板/基底
52‧‧‧列
54‧‧‧行/閘流體行/存取電晶體行
56‧‧‧列
58‧‧‧存取閘極線
60‧‧‧控制閘極線
62‧‧‧陰極線
64‧‧‧陽極線
70‧‧‧基板片段
71‧‧‧區塊
72‧‧‧半導體材料
73‧‧‧渠溝
74‧‧‧介電材料
75‧‧‧渠溝
76‧‧‧介電材料
78‧‧‧區塊
80‧‧‧垂直桿
82‧‧‧基底
86‧‧‧介電質
圖1係根據本發明之一實施例之一記憶體單元之一示意斜投影圖。
圖2係圖1之記憶體單元之一側正視圖。
圖3係根據本發明之一實施例之一記憶體單元之一側正視圖。
圖4係根據本發明之一實施例之一記憶體單元之一側正視圖。
圖5係根據本發明之一實施例之記憶體單元之一水平陣
列之一部分之一示意斜投影圖。
圖6係根據本發明之一實施例之記憶體單元之另一水平陣列之一部分之一示意斜投影圖。
圖7係根據本發明之一實施例之記憶體單元之另一水平陣列之一部分之一示意斜投影圖。
圖8係根據本發明之一實施例之製程中之一基板片段之一示意斜投影圖。
圖9係圖8展示的步驟隨後之一處理步驟處之圖8的基板片段之一圖。
圖10係圖9展示的步驟隨後之一處理步驟處之圖9的基板片段之一圖。
圖11係圖10展示的步驟隨後之一處理步驟處之圖10的基板片段之一圖。
圖12係圖11展示的步驟隨後之一處理步驟處之圖11的基板片段之一圖。
圖13係圖12展示的步驟隨後之一處理步驟處之圖12的基板片段之一圖。
圖14係圖13展示的步驟隨後之一處理步驟處之圖13的基板片段之一圖。
圖15係圖14展示的步驟隨後之一處理步驟處之圖14的基板片段之一圖。
圖16係圖15展示的步驟隨後之一處理步驟處之圖15的基板片段之一圖。
圖17係圖16展示的步驟隨後之一處理步驟處之圖16的基
板片段之一圖。
圖18係圖17展示的步驟隨後之一處理步驟處之圖17的基板片段之一圖。
圖19係圖18展示的步驟隨後之一處理步驟處之圖18的基板片段之一圖。
圖20係圖19展示的步驟隨後之一處理步驟處之圖19的基板片段之一圖。
圖21係圖20展示的步驟隨後之一處理步驟處之圖20的基板片段之一圖。
10‧‧‧記憶體元
12‧‧‧閘流體
14‧‧‧垂直定向存取電晶體
15‧‧‧半導體區域
16‧‧‧半導體區域
17‧‧‧半導體區域
18‧‧‧半導體區域
19‧‧‧半導體區域
20‧‧‧半導體區域
22‧‧‧存取閘極
24‧‧‧閘極介電質
26‧‧‧控制閘極
28‧‧‧閘極介電質/閘極
30‧‧‧電極
32‧‧‧電極
35‧‧‧側
36‧‧‧側
37‧‧‧側
Claims (23)
- 一種記憶體單元,其包括:一閘流體,其包括複數個交替摻雜垂直疊加半導體區域;一垂直定向存取電晶體,其具有一存取閘極,該閘流體垂直高於該存取電晶體;及一控制閘極,其操作地橫向相鄰於該等交替摻雜垂直疊加半導體區域之一者;該控制閘極與該存取閘極橫向間隔。
- 如請求項1之記憶體單元,其中該存取閘極及該控制閘極高度上重疊。
- 如請求項2之記憶體單元,其中該存取閘極及該控制閘極高度上一致。
- 如請求項1之記憶體單元,其中該閘流體與該存取電晶體共用一摻雜半導體區域,該摻雜半導體區域在該閘流體與該存取電晶體之間橫向延伸。
- 一種記憶體單元,其包括:複數個交替摻雜疊加半導體區域,其等之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀,該等半導體區域集體包括共用該等摻雜半導體區域之一者之該記憶體單元之一閘流體與一存取電晶體之可串聯電連接部分;一存取閘極,其操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域,該存取閘極橫向在該向 上引導容器形狀內且不橫向在該向上引導容器形狀外側;及一控制閘極,其操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域。
- 一種記憶體單元,其包括:複數個交替摻雜疊加半導體區域,其等之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀,該等半導體區域集體包括共用該等摻雜半導體區域之一者之該記憶體單元之一閘流體與一存取電晶體之可串聯電連接部分;一存取閘極,其操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域,該存取閘極橫向在該向上引導容器形狀外側且不橫向在該向上引導容器形狀內;及一控制閘極,其操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域。
- 一種記憶體單元,其包括:複數個交替摻雜疊加半導體區域,其等之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀,該等半導體區域集體包括共用該等摻雜半導體區域之一者之該記憶體單元之一閘流體與一存取電晶體之可串聯電連接部分;一存取閘極,其操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域;及 一控制閘極,其操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域,該控制閘極橫向在該向上引導容器形狀內且不橫向在該向上引導容器形狀外側。
- 一種記憶體單元,其包括:複數個交替摻雜疊加半導體區域,其等之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀,該等半導體區域集體包括共用該等摻雜半導體區域之一者之該記憶體單元之一閘流體與一存取電晶體之可串聯電連接部分;一存取閘極,其操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域;及一控制閘極,其操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域,該控制閘極橫向在該向上引導容器形狀外側且不橫向在該向上引導容器形狀內。
- 一種記憶體單元,其包括:複數個交替摻雜疊加半導體區域,其等之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀,該等半導體區域集體包括共用該等摻雜半導體區域之一者之該記憶體單元之一閘流體與一存取電晶體之可串聯電連接部分;一存取閘極,其操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域;及一控制閘極,其操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域,該控制閘極及該存取閘極橫 向在該向上引導容器形狀外側且不橫向在該向上引導容器形狀內。
- 一種記憶體單元,其包括:複數個交替摻雜疊加半導體區域,其等之至少一高度上內部部分在橫向橫截面中形成一向上引導容器形狀,該等半導體區域集體包括共用該等摻雜半導體區域之一者之該記憶體單元之一閘流體與一存取電晶體之可串聯電連接部分;一存取閘極,其操作地橫向相鄰於該存取電晶體之該等半導體區域之一非共用區域;一控制閘極,其操作地橫向相鄰於該閘流體之該等半導體區域之一非共用區域;及該向上引導容器形狀包括具有一對垂直桿之一大致U形狀,在橫向橫截面中一基底在該對垂直桿之間橫向延伸,該等桿之一者高於另一者。
- 一種記憶體陣列,其包括:記憶體單元之一水平陣列,其包括:複數個閘流體,其等在一第一方向上之複數列中及在相對於該第一方向成角度之一第二方向上之複數行中實質上對齊;該等閘流體之個別者包括複數個交替摻雜垂直疊加半導體區域;複數個垂直定向存取電晶體,其等在該第一方向上之複數列中及該第二方向上之複數行中實質上對齊,該等存取電晶體之個別者具有一存取閘極,該存取閘極包 括定向在該第一方向上之複數列中之個別導電存取閘極線之一部分;一控制閘極,其操作地橫向相鄰於該複數個閘流體之個別者之該複數個垂直疊加交替摻雜半導體區域之一者;該等控制閘極之個別者包括定向在該第一方向上之複數列中之個別導電控制閘極線之一部分;複數個陰極線,其等在該第一方向上之複數列中實質上對齊,高度上超過該等存取閘極線;複數個陽極線,其等在該第二方向上之複數行中實質上對齊,高度上超過該等控制閘極線;及該等垂直定向存取電晶體之個別者包括具有一對橫向對置側之一各別通道區域,該等垂直定向存取電晶體之個別者之該存取閘極操作地橫向相鄰於該各別通道區域之該對橫向對置側之僅一者。
- 一種記憶體陣列,其包括:記憶體單元之一水平陣列,其包括:複數個閘流體,其等在一第一方向上之複數列中及在相對於該第一方向成角度之一第二方向上之複數行中實質上對齊;該等閘流體之個別者包括複數個交替摻雜垂直疊加半導體區域;複數個垂直定向存取電晶體,其等在該第一方向上之複數列中及該第二方向上之複數行中實質上對齊,該等存取電晶體之個別者具有一存取閘極,該存取閘極包括定向在該第一方向上之複數列中之個別導電存取閘極 線之一部分;一控制閘極,其操作地橫向相鄰於該複數個閘流體之個別者之該複數個垂直疊加交替摻雜半導體區域之一者;該等控制閘極之個別者包括定向在該第一方向上之複數列中之個別導電控制閘極線之一部分;複數個陰極線,其等在該第一方向上之複數列中實質上對齊,高度上超過該等存取閘極線;複數個陽極線,其等在該第二方向上之複數行中實質上對齊,高度上超過該等控制閘極線;及該等閘流體垂直高於該等存取電晶體。
- 一種形成一垂直定向閘流體與一垂直定向存取電晶體之一共用摻雜半導體區域之方法,該方法包括:在橫向橫截面中形成一大致U形狀半導體材料,該大致U形狀具有一對垂直桿,在橫向橫截面中一基底在該對垂直桿之間橫向延伸;及在該等桿之間之該基底摻雜有n型及p型之至少一者之一導電率改質雜質且由其形成該共用摻雜半導體區域。
- 如請求項13之方法,其中在該摻雜期間遮罩該等桿之橫向面向內側壁隔離此摻雜。
- 如請求項13之方法,其中由其形成該共用摻雜半導體區域包括:退火以使該導電率改質雜質橫向向外擴散至該等桿中。
- 一種形成包括一垂直定向閘流體及操作地橫向相鄰於其之一控制閘極之一記憶體單元之方法,該記憶體單元包 括與該閘流體共用一摻雜半導體區域之一垂直定向存取電晶體,該方法包括:相對於一基板形成半導體材料之一區塊;蝕刻至該區塊中以在橫向橫截面中形成該半導體材料之一大致U形狀,該大致U形狀具有一對垂直桿,在橫向橫截面中一基底在該對垂直桿之間橫向延伸;該蝕刻之後,在該等桿之間之該基底用一第一類型的一導電率改質雜質離子植入至一第一雜質濃度;提供摻雜有該第一類型之一導電率改質雜質之該對桿之高度上最外部分,以低於該第一雜質濃度之一第二雜質濃度提供該對桿之一者之該高度上最外部分;提供該等高度上最外部分與該基底之間之該等桿之各別中間部分,其等摻雜有不同於該第一類型且至一第三雜質濃度之一第二類型之一導電率改質雜質;形成摻雜有至一第四雜質濃度之該第二類型之一導電率雜質之半導體材料,其高度上超過且直接抵於該一個桿之該高度上最外部分,該第四雜質濃度大於該第三雜質濃度;提供一控制閘極,其操作地橫向相鄰於該一個桿之該中間部分;提供一存取電晶體之一存取閘極,其操作地橫向相鄰於該對桿之另一者之該中間部分。
- 如請求項16之方法,其中該對桿之該等高度上最外部分在該離子植入之後摻雜有該第一類型之一導電率改質雜 質。
- 如請求項16之方法,其中該一個桿之該高度上最外部分在該離子植入之前摻雜有該第一類型之一導電率改質雜質。
- 一種記憶體陣列,其包括:記憶體單元之一水平陣列,其包括:複數個閘流體,其等在一第一方向上之複數列中及在相對於該第一方向成角度之一第二方向上之複數行中實質上對齊;該等閘流體之個別者包括複數個交替摻雜垂直疊加半導體區域;複數個垂直定向存取電晶體,其等在該第一方向上之複數列中及該第二方向上之複數行中實質上對齊,該等存取電晶體之個別者具有一存取閘極,該存取閘極包括定向在該第一方向上之複數列中之個別導電存取閘極線之一部分;一控制閘極,其操作地橫向相鄰於該複數個閘流體之個別者之該複數個垂直疊加交替摻雜半導體區域之一者;該等控制閘極之個別者包括定向在該第一方向上之複數列中之個別導電控制閘極線之一部分;複數個陰極線,其等在該第一方向上之複數列中實質上對齊,高度上超過該等存取閘極線;複數個陽極線,其等在該第二方向上之複數行中實質上對齊,高度上超過該等控制閘極線;該等存取閘極線與該等控制閘極線橫向間隔;及 該複數個閘流體之個別者之該複數個垂直疊加交替摻雜半導體區域之該者之個別者具有一對橫向對置側;該等控制閘極之個別者操作地橫向相鄰於該對橫向對置側之僅一者。
- 一種記憶體陣列,其包括:記憶體單元之一水平陣列,其包括:複數個閘流體,其等在一第一方向上之複數列中及在相對於該第一方向成角度之一第二方向上之複數行中實質上對齊;該等閘流體之個別者包括複數個交替摻雜垂直疊加半導體區域;複數個垂直定向存取電晶體,其等在該第一方向上之複數列中及該第二方向上之複數行中實質上對齊,該等存取電晶體之個別者具有一存取閘極,該存取閘極包括定向在該第一方向上之複數列中之個別導電存取閘極線之一部分;一控制閘極,其操作地橫向相鄰於該複數個閘流體之個別者之該複數個垂直疊加交替摻雜半導體區域之一者;該等控制閘極之個別者包括定向在該第一方向上之複數列中之個別導電控制閘極線之一部分;複數個陰極線,其等在該第一方向上之複數列中實質上對齊,高度上超過該等存取閘極線;複數個陽極線,其等在該第二方向上之複數行中實質上對齊,高度上超過該等控制閘極線;及該等陽極線高度上超過該等陰極線。
- 一種記憶體陣列,其包括:記憶體單元之一水平陣列,其包括:複數個閘流體,其等在一第一方向上之複數列中及在相對於該第一方向成角度之一第二方向上之複數行中實質上對齊;該等閘流體之個別者包括複數個交替摻雜垂直疊加半導體區域;複數個垂直定向存取電晶體,其等在該第一方向上之複數列中及該第二方向上之複數行中實質上對齊,該等存取電晶體之個別者具有一存取閘極,該存取閘極包括定向在該第一方向上之複數列中之個別導電存取閘極線之一部分;一控制閘極,其操作地橫向相鄰於該複數個閘流體之個別者之該複數個垂直疊加交替摻雜半導體區域之一者;該等控制閘極之個別者包括定向在該第一方向上之複數列中之個別導電控制閘極線之一部分;複數個陰極線,其等在該第一方向上之複數列中實質上對齊,高度上超過該等存取閘極線;複數個陽極線,其等在該第二方向上之複數行中實質上對齊,高度上超過該等控制閘極線;及該等陰極線高度上超過該等陽極線。
- 一種記憶體單元,其包括:一閘流體,其包括複數個交替摻雜垂直疊加半導體區域,該等半導體區域之一者包括一通道區域;一垂直定向存取電晶體,其具有一存取閘極及一通道 區域,該閘流體之該通道區域垂直高於該存取電晶體之該通道區域;及一控制閘極,其操作地橫向相鄰於該閘流體之該通道區域;該控制閘極與該存取閘極橫向間隔。
- 如請求項22之記憶體單元,其中該閘流體垂直高於該存取電晶體。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/025,591 US8598621B2 (en) | 2011-02-11 | 2011-02-11 | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201246464A TW201246464A (en) | 2012-11-16 |
TWI460826B true TWI460826B (zh) | 2014-11-11 |
Family
ID=46636234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101104088A TWI460826B (zh) | 2011-02-11 | 2012-02-08 | 記憶體單元,記憶體陣列,形成記憶體單元之方法,及形成垂直定向閘流體與垂直定向存取電晶體之共用摻雜半導體區域之方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8598621B2 (zh) |
TW (1) | TWI460826B (zh) |
WO (1) | WO2012108977A2 (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9608119B2 (en) | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US8513722B2 (en) | 2010-03-02 | 2013-08-20 | Micron Technology, Inc. | Floating body cell structures, devices including same, and methods for forming same |
US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
US8507966B2 (en) | 2010-03-02 | 2013-08-13 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
US8598621B2 (en) | 2011-02-11 | 2013-12-03 | Micron Technology, Inc. | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
US8952418B2 (en) | 2011-03-01 | 2015-02-10 | Micron Technology, Inc. | Gated bipolar junction transistors |
US8519431B2 (en) | 2011-03-08 | 2013-08-27 | Micron Technology, Inc. | Thyristors |
US8772848B2 (en) | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
WO2015112163A1 (en) * | 2014-01-24 | 2015-07-30 | Intel Corporation | Fin-based semiconductor devices and methods |
US9331088B2 (en) | 2014-03-25 | 2016-05-03 | Sandisk 3D Llc | Transistor device with gate bottom isolation and method of making thereof |
US9673054B2 (en) * | 2014-08-18 | 2017-06-06 | Micron Technology, Inc. | Array of gated devices and methods of forming an array of gated devices |
US9209187B1 (en) * | 2014-08-18 | 2015-12-08 | Micron Technology, Inc. | Methods of forming an array of gated devices |
US9224738B1 (en) | 2014-08-18 | 2015-12-29 | Micron Technology, Inc. | Methods of forming an array of gated devices |
US20180102161A1 (en) * | 2016-10-07 | 2018-04-12 | Kilopass Technology, Inc. | Vertical Thyristor Memory Array and Memory Array Tile Therefor |
WO2018089559A1 (en) * | 2016-11-08 | 2018-05-17 | Kilopass Technology, Inc. | Vertical thyristor cell and memory array with silicon germanium base regions |
US10636473B2 (en) * | 2017-07-11 | 2020-04-28 | Tc Lab, Inc. | 3D stacked high-density memory cell arrays and methods of manufacture |
US10790304B2 (en) * | 2018-07-26 | 2020-09-29 | Micron Technology, Inc. | Integrated assemblies comprising ferroelectric transistors and non-ferroelectric transistors |
US10629732B1 (en) | 2018-10-09 | 2020-04-21 | Micron Technology, Inc. | Elevationally-extending transistors, devices comprising elevationally-extending transistors, and methods of forming a device comprising elevationally-extending transistors |
KR20210132809A (ko) | 2020-04-28 | 2021-11-05 | 삼성전자주식회사 | 반도체 메모리 장치 및 이의 제조 방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020158254A1 (en) * | 2001-04-30 | 2002-10-31 | International Business Machines Corporation | Memory system capable of operating at high temperatures and method for fabricating the same |
US20070080385A1 (en) * | 2005-10-10 | 2007-04-12 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical transistor and method of fabricating the same |
TW200802866A (en) * | 2006-03-29 | 2008-01-01 | Micron Technology Inc | Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions |
Family Cites Families (229)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3988771A (en) | 1974-05-28 | 1976-10-26 | General Electric Company | Spatial control of lifetime in semiconductor device |
US4487639A (en) | 1980-09-26 | 1984-12-11 | Texas Instruments Incorporated | Localized epitaxy for VLSI devices |
DE3507484C2 (de) | 1985-03-02 | 1993-10-28 | Teves Gmbh Alfred | Hydraulische Bremsanlage |
JPS6379605A (ja) | 1986-09-24 | 1988-04-09 | フランスベッド株式会社 | ベツド装置 |
US5106776A (en) | 1988-06-01 | 1992-04-21 | Texas Instruments Incorporated | Method of making high performance composed pillar dRAM cell |
JPH0750772B2 (ja) | 1989-01-24 | 1995-05-31 | 富士通株式会社 | 半導体装置およびその製造方法 |
EP0481703B1 (en) | 1990-10-15 | 2003-09-17 | Aptix Corporation | Interconnect substrate having integrated circuit for programmable interconnection and sample testing |
JP3081967B2 (ja) | 1990-11-21 | 2000-08-28 | 富士通株式会社 | シリコンオンインシュレータ基板の製造方法 |
US5102821A (en) | 1990-12-20 | 1992-04-07 | Texas Instruments Incorporated | SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium |
US5098861A (en) | 1991-01-08 | 1992-03-24 | Unitrode Corporation | Method of processing a semiconductor substrate including silicide bonding |
JPH04283914A (ja) | 1991-03-12 | 1992-10-08 | Fujitsu Ltd | 貼り合わせ半導体基板とその製造方法 |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US5465249A (en) | 1991-11-26 | 1995-11-07 | Cree Research, Inc. | Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate |
US5412598A (en) | 1992-04-27 | 1995-05-02 | The University Of British Columbia | Bistable four layer device, memory cell, and method for storing and retrieving binary information |
JP2616862B2 (ja) | 1992-06-23 | 1997-06-04 | ジャパンライフ株式会社 | 連続型スペーサー及び連続型スペーサー用成形品の製法 |
JPH0798460A (ja) | 1992-10-21 | 1995-04-11 | Seiko Instr Inc | 半導体装置及び光弁装置 |
US5260233A (en) | 1992-11-06 | 1993-11-09 | International Business Machines Corporation | Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding |
US5600160A (en) | 1993-04-14 | 1997-02-04 | Hvistendahl; Douglas D. | Multichannel field effect device |
US5510630A (en) | 1993-10-18 | 1996-04-23 | Westinghouse Electric Corporation | Non-volatile random access memory cell constructed of silicon carbide |
US5471039A (en) | 1994-06-22 | 1995-11-28 | Panda Eng. Inc. | Electronic validation machine for documents |
JPH0888153A (ja) | 1994-09-19 | 1996-04-02 | Toshiba Corp | 積層構造ウェハおよびその形成方法 |
DE4433845A1 (de) | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
FR2729008B1 (fr) | 1994-12-30 | 1997-03-21 | Sgs Thomson Microelectronics | Circuit integre de puissance |
US5981992A (en) | 1995-06-07 | 1999-11-09 | International Business Machines Corporation | Mechanical supports for very thin stacked capacitor plates |
US6750091B1 (en) | 1996-03-01 | 2004-06-15 | Micron Technology | Diode formation method |
US5920105A (en) | 1996-09-19 | 1999-07-06 | Fujitsu Limited | Compound semiconductor field effect transistor having an amorphous gas gate insulation layer |
US7888764B2 (en) | 2003-06-24 | 2011-02-15 | Sang-Yun Lee | Three-dimensional integrated circuit structure |
US7470598B2 (en) | 2004-06-21 | 2008-12-30 | Sang-Yun Lee | Semiconductor layer structure and method of making the same |
US7052941B2 (en) | 2003-06-24 | 2006-05-30 | Sang-Yun Lee | Method for making a three-dimensional integrated circuit structure |
US8018058B2 (en) | 2004-06-21 | 2011-09-13 | Besang Inc. | Semiconductor memory device |
FR2755537B1 (fr) | 1996-11-05 | 1999-03-05 | Commissariat Energie Atomique | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
JPH10150176A (ja) | 1996-11-15 | 1998-06-02 | Tadahiro Omi | 半導体基体とその作製方法 |
US5874760A (en) | 1997-01-22 | 1999-02-23 | International Business Machines Corporation | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
US6225151B1 (en) | 1997-06-09 | 2001-05-01 | Advanced Micro Devices, Inc. | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion |
US5936274A (en) | 1997-07-08 | 1999-08-10 | Micron Technology, Inc. | High density flash memory |
US5909618A (en) | 1997-07-08 | 1999-06-01 | Micron Technology, Inc. | Method of making memory cell with vertical transistor and buried word and body lines |
US6255731B1 (en) | 1997-07-30 | 2001-07-03 | Canon Kabushiki Kaisha | SOI bonding structure |
JP4623451B2 (ja) | 1997-07-30 | 2011-02-02 | 忠弘 大見 | 半導体基板及びその作製方法 |
FR2767416B1 (fr) | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
US5904507A (en) | 1998-02-23 | 1999-05-18 | National Semiconductor Corporation | Programmable anti-fuses using laser writing |
US6242775B1 (en) | 1998-02-24 | 2001-06-05 | Micron Technology, Inc. | Circuits and methods using vertical complementary transistors |
US5963469A (en) | 1998-02-24 | 1999-10-05 | Micron Technology, Inc. | Vertical bipolar read access for low voltage memory cell |
US6365488B1 (en) | 1998-03-05 | 2002-04-02 | Industrial Technology Research Institute | Method of manufacturing SOI wafer with buried layer |
EP0945901A1 (de) | 1998-03-23 | 1999-09-29 | Siemens Aktiengesellschaft | DRAM-Zellenanordnung mit vertikalen Transistoren und Verfahren zu deren Herstellung |
US6225165B1 (en) | 1998-05-13 | 2001-05-01 | Micron Technology, Inc. | High density SRAM cell with latched vertical transistors |
US6545297B1 (en) | 1998-05-13 | 2003-04-08 | Micron Technology, Inc. | High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown |
US6229161B1 (en) | 1998-06-05 | 2001-05-08 | Stanford University | Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches |
US6137128A (en) | 1998-06-09 | 2000-10-24 | International Business Machines Corporation | Self-isolated and self-aligned 4F-square vertical fet-trench dram cells |
JP4476390B2 (ja) | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6245663B1 (en) | 1998-09-30 | 2001-06-12 | Conexant Systems, Inc. | IC interconnect structures and methods for making same |
US5977579A (en) | 1998-12-03 | 1999-11-02 | Micron Technology, Inc. | Trench dram cell with vertical device and buried word lines |
JP2000208771A (ja) | 1999-01-11 | 2000-07-28 | Hitachi Ltd | 半導体装置、液晶表示装置およびこれらの製造方法 |
US6288954B1 (en) | 1999-01-19 | 2001-09-11 | Micron Technology, Inc. | Integrated circuit having an on-board reference generator |
JP3911585B2 (ja) | 1999-05-18 | 2007-05-09 | 富士通株式会社 | 半導体装置およびその製造方法 |
US6690038B1 (en) | 1999-06-05 | 2004-02-10 | T-Ram, Inc. | Thyristor-based device over substrate surface |
FR2795865B1 (fr) | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'un film mince utilisant une mise sous pression |
US6355520B1 (en) | 1999-08-16 | 2002-03-12 | Infineon Technologies Ag | Method for fabricating 4F2 memory cells with improved gate conductor structure |
US6391658B1 (en) | 1999-10-26 | 2002-05-21 | International Business Machines Corporation | Formation of arrays of microelectronic elements |
KR100392166B1 (ko) | 2000-03-17 | 2003-07-22 | 가부시끼가이샤 도시바 | 반도체 장치의 제조 방법 및 반도체 장치 |
US6797604B2 (en) | 2000-05-08 | 2004-09-28 | International Business Machines Corporation | Method for manufacturing device substrate with metal back-gate and structure formed thereby |
JP2002359247A (ja) | 2000-07-10 | 2002-12-13 | Canon Inc | 半導体部材、半導体装置およびそれらの製造方法 |
EP2323164B1 (en) | 2000-08-14 | 2015-11-25 | SanDisk 3D LLC | Multilevel memory array and method for making same |
US6621725B2 (en) | 2000-08-17 | 2003-09-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device with floating storage bulk region and method of manufacturing the same |
US6600173B2 (en) | 2000-08-30 | 2003-07-29 | Cornell Research Foundation, Inc. | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
US6583440B2 (en) | 2000-11-30 | 2003-06-24 | Seiko Epson Corporation | Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus |
US6559471B2 (en) | 2000-12-08 | 2003-05-06 | Motorola, Inc. | Quantum well infrared photodetector and method for fabricating same |
FR2818010B1 (fr) | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
JP2002184993A (ja) | 2000-12-11 | 2002-06-28 | Sony Corp | 半導体装置 |
US6576944B2 (en) | 2000-12-14 | 2003-06-10 | Infineon Technologies Ag | Self-aligned nitride pattern for improved process window |
US6635550B2 (en) | 2000-12-20 | 2003-10-21 | Texas Instruments Incorporated | Semiconductor on insulator device architecture and method of construction |
US6570208B2 (en) | 2001-01-18 | 2003-05-27 | International Business Machines Corporation | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI |
US6713791B2 (en) | 2001-01-26 | 2004-03-30 | Ibm Corporation | T-RAM array having a planar cell structure and method for fabricating the same |
US6891205B1 (en) | 2001-03-22 | 2005-05-10 | T-Ram, Inc. | Stability in thyristor-based memory device |
US7456439B1 (en) | 2001-03-22 | 2008-11-25 | T-Ram Semiconductor, Inc. | Vertical thyristor-based memory with trench isolation and its method of fabrication |
US6897514B2 (en) | 2001-03-28 | 2005-05-24 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
US6492662B2 (en) | 2001-04-16 | 2002-12-10 | Ibm Corporation | T-RAM structure having dual vertical devices and method for fabricating the same |
US6759282B2 (en) | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
DE10128718B4 (de) | 2001-06-13 | 2005-10-06 | Infineon Technologies Ag | Grabenkondensator einer DRAM-Speicherzelle mit metallischem Collarbereich und nicht-metallischer Leitungsbrücke zum Auswahltransistor |
US6906354B2 (en) | 2001-06-13 | 2005-06-14 | International Business Machines Corporation | T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same |
JP3647777B2 (ja) | 2001-07-06 | 2005-05-18 | 株式会社東芝 | 電界効果トランジスタの製造方法及び集積回路素子 |
JP2003030980A (ja) | 2001-07-13 | 2003-01-31 | Toshiba Corp | 半導体記憶装置 |
US6593624B2 (en) | 2001-09-25 | 2003-07-15 | Matrix Semiconductor, Inc. | Thin film transistors with vertically offset drain regions |
US6841813B2 (en) | 2001-08-13 | 2005-01-11 | Matrix Semiconductor, Inc. | TFT mask ROM and method for making same |
US6744094B2 (en) | 2001-08-24 | 2004-06-01 | Micron Technology Inc. | Floating gate transistor with horizontal gate layers stacked next to vertical body |
US6815781B2 (en) | 2001-09-25 | 2004-11-09 | Matrix Semiconductor, Inc. | Inverted staggered thin film transistor with salicided source/drain structures and method of making same |
WO2003041170A1 (fr) | 2001-11-07 | 2003-05-15 | Shindengen Electric Manufacturing Co., Ltd. | Dispositif semi-conducteur de protection contre la surtension |
US7081663B2 (en) | 2002-01-18 | 2006-07-25 | National Semiconductor Corporation | Gate-enhanced junction varactor with gradual capacitance variation |
US6872645B2 (en) | 2002-04-02 | 2005-03-29 | Nanosys, Inc. | Methods of positioning and/or orienting nanostructures |
US7042749B2 (en) | 2002-05-16 | 2006-05-09 | Micron Technology, Inc. | Stacked 1T-nmemory cell structure |
US6940748B2 (en) | 2002-05-16 | 2005-09-06 | Micron Technology, Inc. | Stacked 1T-nMTJ MRAM structure |
JP2004003398A (ja) | 2002-05-31 | 2004-01-08 | Shin Caterpillar Mitsubishi Ltd | 建設機械 |
US6781907B2 (en) | 2002-06-06 | 2004-08-24 | Micron Technology, Inc. | Temperature compensated T-RAM memory device and method |
US6764774B2 (en) | 2002-06-19 | 2004-07-20 | International Business Machines Corporation | Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same |
US6914286B2 (en) | 2002-06-27 | 2005-07-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices using sidewall spacers |
US7224024B2 (en) | 2002-08-29 | 2007-05-29 | Micron Technology, Inc. | Single transistor vertical memory gain cell |
US6838723B2 (en) | 2002-08-29 | 2005-01-04 | Micron Technology, Inc. | Merged MOS-bipolar capacitor memory cell |
TWI320571B (en) | 2002-09-12 | 2010-02-11 | Qs Semiconductor Australia Pty Ltd | Dynamic nonvolatile random access memory ne transistor cell and random access memory array |
US6953953B1 (en) | 2002-10-01 | 2005-10-11 | T-Ram, Inc. | Deep trench isolation for thyristor-based semiconductor device |
US6690039B1 (en) | 2002-10-01 | 2004-02-10 | T-Ram, Inc. | Thyristor-based device that inhibits undesirable conductive channel formation |
US6965129B1 (en) | 2002-11-06 | 2005-11-15 | T-Ram, Inc. | Thyristor-based device having dual control ports |
US7710771B2 (en) | 2002-11-20 | 2010-05-04 | The Regents Of The University Of California | Method and apparatus for capacitorless double-gate storage |
JP3813123B2 (ja) | 2002-12-25 | 2006-08-23 | 株式会社沖データ | 半導体装置及びledヘッド |
US6768156B1 (en) | 2003-02-10 | 2004-07-27 | Micron Technology, Inc. | Non-volatile random access memory cells associated with thin film constructions |
US6812504B2 (en) | 2003-02-10 | 2004-11-02 | Micron Technology, Inc. | TFT-based random access memory cells comprising thyristors |
US6713810B1 (en) | 2003-02-10 | 2004-03-30 | Micron Technology, Inc. | Non-volatile devices, and electronic systems comprising non-volatile devices |
JP2004247545A (ja) | 2003-02-14 | 2004-09-02 | Nissan Motor Co Ltd | 半導体装置及びその製造方法 |
US6845034B2 (en) | 2003-03-11 | 2005-01-18 | Micron Technology, Inc. | Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons |
CN100394603C (zh) | 2003-04-03 | 2008-06-11 | 株式会社东芝 | 相变存储装置 |
US20040228168A1 (en) | 2003-05-13 | 2004-11-18 | Richard Ferrant | Semiconductor memory device and method of operating same |
US6958513B2 (en) | 2003-06-06 | 2005-10-25 | Chih-Hsin Wang | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells |
JP3933608B2 (ja) | 2003-06-30 | 2007-06-20 | 株式会社東芝 | 半導体記憶装置及び半導体集積回路 |
US8125003B2 (en) | 2003-07-02 | 2012-02-28 | Micron Technology, Inc. | High-performance one-transistor memory cell |
US6921692B2 (en) | 2003-07-07 | 2005-07-26 | Micron Technology, Inc. | Methods of forming memory circuitry |
US7018873B2 (en) | 2003-08-13 | 2006-03-28 | International Business Machines Corporation | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate |
US7205185B2 (en) | 2003-09-15 | 2007-04-17 | International Busniess Machines Corporation | Self-aligned planar double-gate process by self-aligned oxidation |
US7195959B1 (en) | 2004-10-04 | 2007-03-27 | T-Ram Semiconductor, Inc. | Thyristor-based semiconductor device and method of fabrication |
US7180135B1 (en) | 2003-10-06 | 2007-02-20 | George Mason Intellectual Properties, Inc. | Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load |
US6888199B2 (en) | 2003-10-07 | 2005-05-03 | International Business Machines Corporation | High-density split-gate FinFET |
JP4044510B2 (ja) | 2003-10-30 | 2008-02-06 | 株式会社東芝 | 半導体集積回路装置 |
JP2005150156A (ja) | 2003-11-11 | 2005-06-09 | Toshiba Corp | 磁気記憶装置 |
US7268373B1 (en) | 2003-11-12 | 2007-09-11 | T-Ram Semiconductor, Inc. | Thyristor-based memory and its method of operation |
US7304327B1 (en) | 2003-11-12 | 2007-12-04 | T-Ram Semiconductor, Inc. | Thyristor circuit and approach for temperature stability |
US7015092B2 (en) | 2003-12-18 | 2006-03-21 | Infineon Technologies North America Corp. | Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts |
US6878991B1 (en) | 2004-01-30 | 2005-04-12 | Micron Technology, Inc. | Vertical device 4F2 EEPROM memory |
US7075146B2 (en) | 2004-02-24 | 2006-07-11 | Micron Technology, Inc. | 4F2 EEPROM NROM memory arrays with vertical devices |
US6995456B2 (en) | 2004-03-12 | 2006-02-07 | International Business Machines Corporation | High-performance CMOS SOI devices on hybrid crystal-oriented substrates |
US7049654B2 (en) | 2004-03-31 | 2006-05-23 | Intel Corporation | Memory with split gate devices and method of fabrication |
JP4429798B2 (ja) | 2004-05-12 | 2010-03-10 | 富士通マイクロエレクトロニクス株式会社 | フィン型チャネルfetを用いたシステムlsi及びその製造方法 |
US7112997B1 (en) | 2004-05-19 | 2006-09-26 | Altera Corporation | Apparatus and methods for multi-gate silicon-on-insulator transistors |
US8399934B2 (en) | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
US7141476B2 (en) | 2004-06-18 | 2006-11-28 | Freescale Semiconductor, Inc. | Method of forming a transistor with a bottom gate |
CN101010793B (zh) | 2004-06-30 | 2011-09-28 | Nxp股份有限公司 | 制造具有通过纳米线接触的导电材料层的电子器件的方法 |
US7518182B2 (en) | 2004-07-20 | 2009-04-14 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
US20060034116A1 (en) | 2004-08-13 | 2006-02-16 | Lam Chung H | Cross point array cell with series connected semiconductor diode and phase change storage media |
US7145186B2 (en) | 2004-08-24 | 2006-12-05 | Micron Technology, Inc. | Memory cell with trenched gated thyristor |
US7365385B2 (en) | 2004-08-30 | 2008-04-29 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
US7259415B1 (en) | 2004-09-02 | 2007-08-21 | Micron Technology, Inc. | Long retention time single transistor vertical memory gain cell |
US7271052B1 (en) | 2004-09-02 | 2007-09-18 | Micron Technology, Inc. | Long retention time single transistor vertical memory gain cell |
CN1606170A (zh) | 2004-09-24 | 2005-04-13 | 中国科学院物理研究所 | 基于双势垒隧道结共振隧穿效应的晶体管 |
US7566974B2 (en) | 2004-09-29 | 2009-07-28 | Sandisk 3D, Llc | Doped polysilicon via connecting polysilicon layers |
US7476939B2 (en) | 2004-11-04 | 2009-01-13 | Innovative Silicon Isi Sa | Memory cell having an electrically floating body transistor and programming technique therefor |
ATE420461T1 (de) | 2004-11-09 | 2009-01-15 | Soitec Silicon On Insulator | Verfahren zum herstellen von zusammengesetzten wafern |
US7326969B1 (en) | 2004-12-02 | 2008-02-05 | T-Ram Semiconductor, Inc. | Semiconductor device incorporating thyristor-based memory and strained silicon |
US7173312B2 (en) | 2004-12-15 | 2007-02-06 | International Business Machines Corporation | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
KR100702011B1 (ko) | 2005-03-16 | 2007-03-30 | 삼성전자주식회사 | 다중 게이트 트랜지스터들을 채택하는 씨모스 에스램 셀들및 그 제조방법들 |
KR100663359B1 (ko) | 2005-03-31 | 2007-01-02 | 삼성전자주식회사 | 리세스 채널 트랜지스터 구조를 갖는 단일 트랜지스터플로팅 바디 디램 셀 및 그 제조방법 |
US7816728B2 (en) | 2005-04-12 | 2010-10-19 | International Business Machines Corporation | Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications |
KR100702014B1 (ko) | 2005-05-03 | 2007-03-30 | 삼성전자주식회사 | 수직 채널 트랜지스터 구조를 갖는 단일 트랜지스터 플로팅바디 디램 소자들 및 그 제조방법들 |
US7279740B2 (en) | 2005-05-12 | 2007-10-09 | Micron Technology, Inc. | Band-engineered multi-gated non-volatile memory device with enhanced attributes |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
JP4696964B2 (ja) | 2005-07-15 | 2011-06-08 | ソニー株式会社 | メモリ用の半導体装置 |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7776715B2 (en) | 2005-07-26 | 2010-08-17 | Micron Technology, Inc. | Reverse construction memory cell |
US7538000B2 (en) | 2005-07-28 | 2009-05-26 | Freescale Semiconductor, Inc. | Method of forming double gate transistors having varying gate dielectric thicknesses |
US7511332B2 (en) | 2005-08-29 | 2009-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical flash memory |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7227233B2 (en) | 2005-09-12 | 2007-06-05 | International Business Machines Corporation | Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM |
KR100660881B1 (ko) | 2005-10-12 | 2006-12-26 | 삼성전자주식회사 | 수직 채널 트랜지스터를 구비한 반도체 소자 및 그 제조방법 |
KR100663368B1 (ko) | 2005-12-07 | 2007-01-02 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 데이터 라이트 및 리드방법 |
US7786505B1 (en) | 2005-12-16 | 2010-08-31 | T-Ram Semiconductor, Inc. | Reduction of charge leakage from a thyristor-based memory cell |
JP5011748B2 (ja) | 2006-02-24 | 2012-08-29 | 株式会社デンソー | 半導体装置 |
US7439594B2 (en) | 2006-03-16 | 2008-10-21 | Micron Technology, Inc. | Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors |
US8008144B2 (en) | 2006-05-11 | 2011-08-30 | Micron Technology, Inc. | Dual work function recessed access device and methods of forming |
JP2008010503A (ja) | 2006-06-27 | 2008-01-17 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
KR100745934B1 (ko) | 2006-06-30 | 2007-08-02 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 형성 방법 |
US7589995B2 (en) | 2006-09-07 | 2009-09-15 | Micron Technology, Inc. | One-transistor memory cell with bias gate |
US7410856B2 (en) | 2006-09-14 | 2008-08-12 | Micron Technology, Inc. | Methods of forming vertical transistors |
US7851859B2 (en) | 2006-11-01 | 2010-12-14 | Samsung Electronics Co., Ltd. | Single transistor memory device having source and drain insulating regions and method of fabricating the same |
US7592209B2 (en) | 2006-11-13 | 2009-09-22 | Intel Corporation | Integration of a floating body memory on SOI with logic transistors on bulk substrate |
US7619917B2 (en) | 2006-11-28 | 2009-11-17 | Qimonda North America Corp. | Memory cell with trigger element |
US8217435B2 (en) | 2006-12-22 | 2012-07-10 | Intel Corporation | Floating body memory cell having gates favoring different conductivity type regions |
JP2008177273A (ja) | 2007-01-17 | 2008-07-31 | Toshiba Corp | 半導体記憶装置及び半導体記憶装置の製造方法 |
US8368137B2 (en) | 2007-06-26 | 2013-02-05 | Sandisk Technologies Inc. | Dual bit line metal layers for non-volatile memory |
US8159035B2 (en) | 2007-07-09 | 2012-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gates of PMOS devices having high work functions |
US7816216B2 (en) | 2007-07-09 | 2010-10-19 | Micron Technology, Inc. | Semiconductor device comprising transistor structures and methods for forming same |
US7969808B2 (en) | 2007-07-20 | 2011-06-28 | Samsung Electronics Co., Ltd. | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same |
KR100881825B1 (ko) | 2007-07-27 | 2009-02-03 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US9129845B2 (en) | 2007-09-19 | 2015-09-08 | Micron Technology, Inc. | Buried low-resistance metal word lines for cross-point variable-resistance material memories |
US7439149B1 (en) | 2007-09-26 | 2008-10-21 | International Business Machines Corporation | Structure and method for forming SOI trench memory with single-sided strap |
US20090108351A1 (en) | 2007-10-26 | 2009-04-30 | International Business Machines Corporation | Finfet memory device with dual separate gates and method of operation |
KR101019336B1 (ko) | 2007-10-29 | 2011-03-07 | 재단법인서울대학교산학협력재단 | 관성 센서를 이용한 안정화 제어 시스템 및 방법 |
US7719869B2 (en) | 2007-11-19 | 2010-05-18 | Qimonda Ag | Memory cell array comprising floating body memory cells |
KR20090054245A (ko) | 2007-11-26 | 2009-05-29 | 삼성전자주식회사 | 플로팅 바디 디램 소자 및 그 제조 방법 |
DE102007057728B4 (de) | 2007-11-30 | 2014-04-30 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterbauelements mit einer Kurzschlusstruktur |
US7940558B2 (en) | 2007-12-21 | 2011-05-10 | Qimonda Ag | Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor |
KR100950472B1 (ko) | 2007-12-28 | 2010-03-31 | 주식회사 하이닉스반도체 | 4f2 트랜지스터를 갖는 반도체 소자의 제조방법 |
US8558220B2 (en) | 2007-12-31 | 2013-10-15 | Sandisk 3D Llc | Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same |
US20090173984A1 (en) | 2008-01-08 | 2009-07-09 | Qimonda Ag | Integrated circuit and method of manufacturing an integrated circuit |
US7795691B2 (en) | 2008-01-25 | 2010-09-14 | Cree, Inc. | Semiconductor transistor with P type re-grown channel layer |
US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
US7742324B2 (en) | 2008-02-19 | 2010-06-22 | Micron Technology, Inc. | Systems and devices including local data lines and methods of using, making, and operating the same |
US20090246952A1 (en) | 2008-03-28 | 2009-10-01 | Tokyo Electron Limited | Method of forming a cobalt metal nitride barrier film |
US8030634B2 (en) | 2008-03-31 | 2011-10-04 | Macronix International Co., Ltd. | Memory array with diode driver and method for fabricating the same |
US7910451B2 (en) | 2008-04-04 | 2011-03-22 | International Business Machines Corporation | Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor |
US7646847B2 (en) | 2008-05-01 | 2010-01-12 | Bruker Axs Inc. | Handheld two-dimensional X-ray diffractometer |
KR20090132872A (ko) | 2008-06-23 | 2009-12-31 | 삼성전자주식회사 | 반도체 소자 및 반도체 기판 |
CN101621036B (zh) | 2008-07-02 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | 具有非晶硅mas存储单元结构的半导体器件及其制造方法 |
KR101498873B1 (ko) | 2008-07-08 | 2015-03-04 | 삼성전자주식회사 | 디램 및 비휘발성 메모리 특성을 갖는 메모리 소자의 구동방법 |
KR101159879B1 (ko) | 2008-07-14 | 2012-06-25 | 에스케이하이닉스 주식회사 | 고집적 반도체 기억 장치 |
US20100044670A1 (en) | 2008-08-19 | 2010-02-25 | Peiching Ling | Semiconductor device structures having single-crystalline switching device on conducting lines and methods thereof |
US8130537B2 (en) | 2008-09-09 | 2012-03-06 | Qimonda Ag | Phase change memory cell with MOSFET driven bipolar access device |
KR20100070835A (ko) | 2008-12-18 | 2010-06-28 | 삼성전자주식회사 | 사이리스터를 갖는 메모리 셀 및 그것을 포함한 메모리 장치 |
US8614131B2 (en) | 2009-02-03 | 2013-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned static random access memory (SRAM) on metal gate |
KR101554531B1 (ko) | 2009-02-12 | 2015-09-21 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US8405121B2 (en) | 2009-02-12 | 2013-03-26 | Infineon Technologies Ag | Semiconductor devices |
KR101073643B1 (ko) | 2009-02-19 | 2011-10-14 | 서울대학교산학협력단 | 고성능 단일 트랜지스터 플로팅 바디 dram 소자 및 그 제조 방법 |
US7929343B2 (en) | 2009-04-07 | 2011-04-19 | Micron Technology, Inc. | Methods, devices, and systems relating to memory cells having a floating body |
US8148780B2 (en) | 2009-03-24 | 2012-04-03 | Micron Technology, Inc. | Devices and systems relating to a memory cell having a floating body |
KR101077453B1 (ko) | 2009-03-31 | 2011-10-26 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
US8508994B2 (en) | 2009-04-30 | 2013-08-13 | Micron Technology, Inc. | Semiconductor device with floating gate and electrically floating body |
US8183126B2 (en) | 2009-07-13 | 2012-05-22 | Seagate Technology Llc | Patterning embedded control lines for vertically stacked semiconductor elements |
US10566462B2 (en) | 2009-07-30 | 2020-02-18 | Infineon Technologies Austria Ag | Bipolar semiconductor device and manufacturing method |
US8836036B2 (en) | 2010-01-05 | 2014-09-16 | Globalfoundries Singapore Pte. Ltd. | Method for fabricating semiconductor devices using stress engineering |
US8507966B2 (en) | 2010-03-02 | 2013-08-13 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
US8513722B2 (en) | 2010-03-02 | 2013-08-20 | Micron Technology, Inc. | Floating body cell structures, devices including same, and methods for forming same |
US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
US9608119B2 (en) | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US8288795B2 (en) | 2010-03-02 | 2012-10-16 | Micron Technology, Inc. | Thyristor based memory cells, devices and systems including the same and methods for forming the same |
KR20110102738A (ko) | 2010-03-11 | 2011-09-19 | 삼성전자주식회사 | 수직 채널 트랜지스터 및 그의 제조방법 |
KR101670451B1 (ko) | 2010-03-12 | 2016-10-31 | 삼성전자주식회사 | 도전막 매립형 기판, 그 형성 방법, 반도체 소자 및 그 제조 방법 |
US8598621B2 (en) | 2011-02-11 | 2013-12-03 | Micron Technology, Inc. | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
US8435859B2 (en) | 2011-02-16 | 2013-05-07 | Micron Technology, Inc. | Methods of forming electrical contacts |
US8952418B2 (en) | 2011-03-01 | 2015-02-10 | Micron Technology, Inc. | Gated bipolar junction transistors |
US8519431B2 (en) | 2011-03-08 | 2013-08-27 | Micron Technology, Inc. | Thyristors |
US8518812B2 (en) | 2011-05-23 | 2013-08-27 | Micron Technology, Inc. | Methods of forming electrical contacts |
US8772848B2 (en) | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
US8962465B2 (en) | 2012-10-15 | 2015-02-24 | Micron Technology, Inc. | Methods of forming gated devices |
-
2011
- 2011-02-11 US US13/025,591 patent/US8598621B2/en active Active
-
2012
- 2012-01-16 WO PCT/US2012/021438 patent/WO2012108977A2/en active Application Filing
- 2012-02-08 TW TW101104088A patent/TWI460826B/zh active
-
2013
- 2013-10-30 US US14/066,811 patent/US9129983B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020158254A1 (en) * | 2001-04-30 | 2002-10-31 | International Business Machines Corporation | Memory system capable of operating at high temperatures and method for fabricating the same |
US20070080385A1 (en) * | 2005-10-10 | 2007-04-12 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical transistor and method of fabricating the same |
TW200802866A (en) * | 2006-03-29 | 2008-01-01 | Micron Technology Inc | Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions |
Also Published As
Publication number | Publication date |
---|---|
TW201246464A (en) | 2012-11-16 |
WO2012108977A3 (en) | 2012-11-08 |
WO2012108977A2 (en) | 2012-08-16 |
US8598621B2 (en) | 2013-12-03 |
US9129983B2 (en) | 2015-09-08 |
US20120205713A1 (en) | 2012-08-16 |
US20140057398A1 (en) | 2014-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI460826B (zh) | 記憶體單元,記憶體陣列,形成記憶體單元之方法,及形成垂直定向閘流體與垂直定向存取電晶體之共用摻雜半導體區域之方法 | |
US7846798B2 (en) | Methods of forming vertical transistor structures | |
JP4851694B2 (ja) | 半導体装置の製造方法 | |
US6586798B1 (en) | High voltage MOS-gated power device | |
TWI536503B (zh) | 半導體裝置及靜態隨機存取記憶胞內電晶體之形成方法 | |
US9269795B2 (en) | Circuit structures, memory circuitry, and methods | |
US9230968B2 (en) | Methods of forming memory arrays and semiconductor constructions | |
CN107464807A (zh) | 半导体器件 | |
US10504905B2 (en) | Memory arrays | |
US8936990B2 (en) | Manufacturing method of power transistor device with super junction | |
US9875960B1 (en) | Memory arrays | |
CN111200008B (zh) | 超结器件及其制造方法 | |
CN106992182A (zh) | 存储器件及其制造方法及包括该存储器件的电子设备 | |
KR100668511B1 (ko) | 핀 트랜지스터 및 그 제조 방법 | |
US10541241B2 (en) | Semiconductor device having thyristor and metal-oxide semiconductor transistor | |
US20180294268A1 (en) | Apparatuses Containing FinFETS | |
US6329235B1 (en) | Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM | |
TW201349353A (zh) | 電晶體元件及其製造方法 | |
US10217857B2 (en) | Super junction MOSFET and method of manufacturing the same | |
US11600535B2 (en) | Integrated assemblies having conductive material along three of four sides around active regions, and methods of forming integrated assemblies | |
CN103378127B (zh) | 垂直沟道晶体管 | |
CN105789205A (zh) | 静态随机存取存储器与其制造方法 | |
JP2011142208A (ja) | 半導体装置および半導体装置の製造方法 | |
JPH06204474A (ja) | 半導体装置 |