TWI405323B - 使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構及其製造方法 - Google Patents

使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構及其製造方法 Download PDF

Info

Publication number
TWI405323B
TWI405323B TW096140392A TW96140392A TWI405323B TW I405323 B TWI405323 B TW I405323B TW 096140392 A TW096140392 A TW 096140392A TW 96140392 A TW96140392 A TW 96140392A TW I405323 B TWI405323 B TW I405323B
Authority
TW
Taiwan
Prior art keywords
diode
semiconductor substrate
array structure
transient voltage
type
Prior art date
Application number
TW096140392A
Other languages
English (en)
Other versions
TW200828569A (en
Inventor
Bobde Madhur
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW200828569A publication Critical patent/TW200828569A/zh
Application granted granted Critical
Publication of TWI405323B publication Critical patent/TWI405323B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)

Description

使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構及其製造方法
本發明係有關於一種暫態電壓抑制二極體(transient voltage suppressing；TVS)之電路結構及其製造方法。更特別的是，本發明係有關於一種使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構改良的電路結構及其製造方法，用以解決拴鎖效應之技術性上的困難。
傳統技術中，對於暫態電壓抑制二極體(TVS)陣列結構之設計與製造方法一直存在著一種技術性上的困難。此技術性的困難，也就是指在暫態電壓抑制二極體陣列結構中的多個PN接面二極體通常是藉由使用標準的互補式金氧半導體(CMOS)程序步驟來製作於半導體基板上，因此，往往會產生寄生PNP電晶體與寄生NPN電晶體。在靜電放電(electrostatic discharge；ESD)的情況下或發生暫態電壓時，會有較大的電壓施加於暫態電壓抑制二極體陣列結構，寄生NPN電晶體或寄生PNP電晶體就會開啟並觸發拴鎖(latch－up)效應，而導致一種突然且猛烈的電壓驟回(snapback)現象。此突然且猛烈的驟回現象極有可能會對於系統之穩定性產生不可預期的影響或者甚至造成傷害。另外，在暫態電壓抑制二極體陣列結構中寄生NPN電晶體或寄生PNP電晶體的拴鎖效應可能會進一步導致其他突如其然或不可預期的電壓－電流暫態(transient)變化。然而，由暫態電壓抑制二極體陣列結構中寄生NPN電晶體或寄生PNP電晶體的拴鎖現象所造成的技術性困難卻無法輕易地獲得解決。
特別是，暫態電壓抑制二極體通常是應用在積體電路遭受突然的過電壓進入積體電路而產生損害的意外防護。一種積體電路是設計可以於正常範圍的電壓下執行。然而，在許多情況下，譬如靜電放電時，電流會快速地產生暫態變化並且減輕，而高電壓可能就會突如其然且無法控制地對於電路造成衝擊。當發生這種過電壓的情況時，就需要暫態電壓抑制二極體去執行可能會對於積體電路造成傷害之防護功能。隨著構成積體電路之元件數量的不斷提高，積體電路將變得很容易受到過電壓的傷害，而對於暫態電壓抑制二極體之傷害防護的需求也將隨之增加。暫態電壓抑制二極體的典型應用上包含有通用序列匯排流(USB)電源與資料線防護、數位影像介面(Digital video intertace)、高速乙太網路(Ethernet)、筆記型電腦、顯示器以及平面顯示器等方面的應用。
請參照第1A圖與第1B圖，其分別顯示一種暫態電壓抑制二極體元件之電路圖與電流－電壓圖。一種理想的暫態電壓抑制二極體是當輸入電壓Vin小於崩潰電壓Vb時，可以將電流(如零電流(zero－current))全部加以阻擋，用以減少崩潰電流。再者，理想上，當輸入電壓Vin大於崩潰電壓Vb時，暫態電壓抑制二極體在這種情況下將具有接近零的電阻，以致於暫態電壓能夠有效地抑制下來。一種暫態電壓抑制二極體能夠利用具有崩潰電壓之PN接面元件而實現，當暫態輸入電壓超過崩潰電壓時，這種暫態電壓抑制二極體將能夠允許目前的情況而達到暫態電壓之防護。然而，如第1B圖中所示，由於PN接面類型的暫態電壓抑制二極體的高電阻，它不具有少數載子並且其實施效能不佳。同樣地，利用雙極NPN/PNP來實現的暫態電壓抑制二極體係具有雙極電晶體的纍增觸發(avalanche－triggered)之啟動，崩潰的電流會隨著其雙極增益而放大，而基底將會湧進少數載子，且雙極的暫態電壓抑制二極體能夠達到較佳的實施電壓。
由於電子技術的提升，也造成越來越多的元件與應用需要暫態電壓抑制二極體陣列結構來提供靜電放電(ESD)防護，特別是針對於高能隙寬度資料匯流排之防護。請參照第2A圖，其為一種四通道暫態電壓抑制二極體之電路圖；以及第2B圖，其為暫態電壓抑制二極體陣列結構之側面剖視圖，並只有顯示該陣列裝置之核心部份。如第2A圖與第2B圖所示之暫態電壓抑制二極體陣列結構，其包含有以串聯連接之複數高壓側控制二極體(high－side steering diode)與低壓側控制二極體(low－side steering diode)，其中高壓側控制二極體連接到Vcc，且低壓側控制二極體連接到接地電位。進一步而言，高壓側控制與低壓側控制二極體是並聯連接至一主要的齊納二極體(Zener diode)，其中控制二極體比起齊納二極體是小了許多並具有較低的接面電容(junction capacitance)。此外，如第2C圖所示，這樣的實施方法更產生另一個問題，也就是由於寄生NPN電晶體與寄生PNP電晶體所誘導的矽控整流器(SCR)操作產生之拴鎖效應。主要的齊納二極體崩潰會觸發寄生NPN電晶體開啟，更開啟了矽控整流器而造成拴鎖效應。在高溫時，即使寄生NPN電晶體並未開啟，經由寄生NPN電晶體之NP接面的高漏電流可能也會開啟矽控整流器，而導致拴鎖效應。為了抑制由寄生PNP電晶體與寄生NPN電晶體所誘導的矽控整流器操作產生之拴鎖效應，現實上實施在半導體基板上的元件需要側向延伸於基板上一段距離，此距離可以高達10微米或更多，如第2B圖所示，但是其抑制效果通常並不太明顯。
請參照第3A圖與第3B圖，其說明在乙太網路中不同的防護電路透過寄生PNP電晶體之拴鎖效應所造成的特殊困難。在此乙太網路防護電路中，Vcc與接地接點兩者都是以浮置(floating)方式設置的。然而，在這個設計中的寄生的矽控整流器結構並不明顯是弱的，將會導致一種突發電壓之驟回現象，如第3B圖所示。這樣的突發與強烈的驟回現象可能會對於系統的穩定性造成不可預期的影響或者甚至產生傷害。由於寄生PNP電晶體本來就存在於互補式金氧半導體(CMOS)製程中，且實際上Vcc與接地接點浮置會讓拴鎖效應惡化，這些困難並無法輕易地獲得解決。另外，也需要額外的鑲埋層(buried layers)去抑制寄生PNP電晶體的晶粒，如此將造成複雜的元件結構與極高的製程費用。
因此，為了提供一種新的及改良的電路結構與製造方法來解決以上所述的各種困難，在電路與元件製作的這些方面仍然有需要經過特殊設計。尤其是，目前仍然存在著提供新的與改良的暫態電壓抑制二極體電路之需求，以便能夠有效率並容易地防止寄生PNP電晶體或寄生NPN電晶體之拴鎖效應。
為克服前述傳統暫態電壓抑制二極體陣列所造成的諸多困難與限制，本發明一方面在於提供一種嶄新的與改良的暫態電壓抑制二極體陣列結構元件結構，乃使用可以拴鎖隔離之溝槽以防止寄生PNP電晶體或寄生NPN電晶體之拴鎖效應。
本發明之另一方面在於提供一種使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構，將絕緣溝槽設置於數個二極體之間，使得相鄰的二極體之間的側向距離能夠被縮短，而不需要拴鎖的元件。
簡單來說，本發明之一個較佳實施例係揭露一種使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構，其包含複數二極體，形成於一半導體基板上，以作為不同導電類型之複數摻雜區域，用以構成複數PN接面。此暫態電壓抑制二極體陣列結構更包含有一絕緣溝槽，設置於前述二極體之間加以隔離，並用以防止寄生PNP電晶體或寄生NPN電晶體所造成之拴鎖效應(latch－up)。
本發明更揭露一種使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構的製造方法。此製造方法包含將暫態電壓抑制二極體陣列製造於半導體基板之步驟，其藉由摻雜具有不同導電類型之複數摻雜區域之步驟，用以形成複數二極體於這些摻雜區域之間的PN接面之間。此製造方法更包含將絕緣溝槽形成於上述摻雜區域之間，用以隔離摻雜區域，並用以防止在半導體基板上不同導電類型之摻雜區域之間的寄生PNP電晶體或寄生NPN電晶體所引發的拴鎖效應。
以下將可透過閱讀本發明之較佳實施例的詳細描述與說明各個圖式，使本發明之技術思想更被突顯，以了解與獲得本發明之這些和其他目的。
請參照第4圖，係繪示根據本發明所提供之一個嶄新及改良的實施方式之暫態電壓抑制二極體陣列結構的部份之側面剖視圖。如圖所示，此部份的暫態電壓抑制二極體陣列結構100具有兩個通道，兩通道設置於N型基板101之上表面的N型磊晶層105上，而N型基板101之下表面則連接至施以電壓Vcc之陽極端110。並且，暫態電壓抑制二極體陣列結構100之陽極端110設置於下表面，而陰極端120設置在連接至接地電壓的上表面。暫態電壓抑制二極體陣列結構100更包含第一高壓側二極體125與第一低壓側二極體130，連接到第一輸入輸出(IO)端135。另外，暫態電壓抑制二極體陣列結構100更包含第二高壓側二極體140與第二低壓側二極體145，連接到第二輸入輸出(IO)端150。第一高壓側二極體125是形成來作為P型摻雜區域125－P與N型磊晶層105之間的PN接面。第一低壓側二極體130是形成來作為N型摻雜區域135－N與P型主體區域160之間的PN接面，其設置於陰極端120下方，且第一輸入輸出(IO)墊135連接到第一低壓側二極體130之N型摻雜區域135－N，並連接到第一高壓側二極體125之P型摻雜區域125－P。第二低壓側二極體145是形成來作為N型摻雜區域145－N與P型主體區域160之間的PN接面，其設置於陰極端120之下方，且第二輸入輸出(IO)墊150連接到第二低壓側二極體145之N型摻雜區域145－N，並連接到第二高壓側二極體140之P型摻雜區域140－P。較大區域之齊納二極體170形成於P型主體區域160與N型磊晶層105之間而具有一PN接面。NPN電晶體能夠由齊納二極體170所觸發，且NPN電晶體是由N型射極區域155、P型主體區域160與N型基板101所形成，以構成大的暫態電流，而並不需要太多的電阻。另外，暫態電壓抑制二極體陣列結構100更包含第一絕緣溝槽180－1，其形成於第一高壓側二極體125與第一低壓側二極體130之間。暫態電壓抑制二極體陣列結構100更包含第二絕緣溝槽180－2，其形成於第二高壓側二極體140與第二低壓側二極體145之間。此絕緣溝槽係形成於由高壓側與低壓側二極體所形成之多個PN接面之間，可以防止寄生NPN與PNP電晶體所造成的拴鎖效應。
請參照第5圖，係繪示根據本發明所提供之另一個嶄新及改良的實施方式之暫態電壓抑制二極體陣列結構之側面剖視圖。於第5圖之元件100’是小於第4圖之元件100，除此之外，在元件100’中具有額外的複數溝槽，以提供較好的隔離作用。溝槽180’－1與180’－2將低壓側二極體與主要的齊納二極體區域分隔開來，藉此讓側向NPN中斷，而側向NPN是由N型區域155、P型主體區域160與低壓側二極體陰極區域135－N與145－N所構成。
請參照第6圖，係繪示用以說明本發明之一種靜電放電(ESD)防護或暫態電壓抑制二極體操作之電流－電壓(I－V)圖，由於減低了拴鎖效應，而可明顯減輕驟回現象。如電流－電壓圖所示，電流－電壓曲線210顯示出在暫態電壓抑制二極體陣列結構中半導體基板上不同摻雜區域之間所引發的寄生NPN電晶體或寄生PNP電晶體之拴鎖效應，可能將導致以高電壓及電流去開啟寄生NPN電晶體或寄生PNP電晶體，因此引發一種突發之驟回現象。因為絕緣溝槽180－1與180－2的作用，拴鎖效應將獲得減輕，而且驟回現象會大大地減少。如電流－電壓曲線210即是在發生驟回現象時所取得之曲線，其突發的電壓變化會強烈地引起系統的不穩定性。
雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。在不脫離本發明之精神和範圍內，所為之更動與潤飾，均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。
100．．．暫態電壓抑制二極體陣列結構
100’．．．元件
101．．．N型基板
105．．．N型磊晶層
110．．．陽極端
120．．．陰極端
125．．．第一高壓側二極體
125－P．．．P型摻雜區域
130．．．第一低壓側二極體
135．．．第一輸入輸出端
135－N．．．N型摻雜區域
140．．．第二高壓側二極體
140－P．．．P型摻雜區域
145．．．第二低壓側二極體
145－N．．．N型摻雜區域
150．．．第二輸入輸出端
155．．．N型射極區域
160．．．P型主體區域
170．．．齊納二極體
180－1．．．第一絕緣溝槽
180’－1．．．溝槽
180－2．．．第二絕緣溝槽
180’－2．．．溝槽
210．．．電流－電壓曲線
220．．．電流－電壓曲線
第1A圖係繪示一種傳統的暫態電壓抑制二極體元件之電路圖，以及第1B圖係繪示一種電流－電壓(I－V)圖，意即電流對應電壓圖，用以說明暫態電壓抑制二極體元件之逆特性；第2A圖係繪示一種傳統的暫態電壓抑制二極體陣列結構電路圖，此暫態電壓抑制二極體陣列包含複數高壓側二極體與低壓側二極體，且高壓側二極體與低壓側二極體係以並聯連接至具有一主要的齊納二極體之複數輸入/輸出(I/O)墊；第2B圖係繪示根據一種傳統的元件結構說明第2A圖之暫態電壓抑制二極體陣列結構裝置實現的側面剖視圖；第2C圖係繪示用來說明如實施於第2B圖中的元件之電位拴鎖效應的等效電路圖；第3A圖係繪示一種根據如第2B圖所示之結構的乙太網路不同的防護電路之電路圖，其需要都是浮置的Vcc與GND接點，且需要鑲埋層去抑制具有防護電路結構的寄生矽控整流器(SCR)之晶粒；第3B圖係繪示一種用以說明一種靜電放電防護或暫態電壓抑制二極體操作之電流－電壓(I－V)圖，當使用傳統的暫態電壓抑制二極體陣列時，會導致不可預期的突發與強烈的驟回現象之發生；第4圖係繪示根據本發明所提供之一種使用溝槽隔離之暫態電壓抑制二極體陣列結構之側面剖視圖，其明顯減少寄生NPN電晶體或寄生PNP電晶體之拴鎖效應；第5圖係繪示根據本發明所提供之另一種使用溝槽隔離之暫態電壓抑制二極體陣列結構之側面剖視圖，其明顯減少寄生PNP或NPN電晶體之拴鎖效應；以及第6圖係繪示用以說明本發明之一種靜電放電防護或暫態電壓抑制二極體操作之電流－電壓(I－V)圖，由於減少了拴鎖效應，而可明顯減輕驟回現象。
100．．．暫態電壓抑制二極體陣列結構
105．．．N型磊晶層
110．．．陽極端
120．．．陰極端
125．．．第一高壓側二極體
125－P．．．P型摻雜區域
130．．．第一低壓側二極體
135．．．第一輸入輸出端
135－N．．．N型摻雜區域
140．．．第二高壓側二極體
140－P．．．P型摻雜區域
145．．．第二低壓側二極體
145－N．．．N型摻雜區域
150．．．第二輸入輸出端
155．．．N型射極區域
160．．．P型主體區域
170．．．齊納二極體
180－1．．．第一絕緣溝槽
180－2．．．第二絕緣溝槽

Claims (9)

  1. 一種使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體(transient voltage suppressing；TVS)陣列結構，其包含：複數二極體，形成於一半導體基板上，以作為不同導電類型之複數摻雜區域，用以構成複數PN接面(PN junction)；複數絕緣溝槽，設置於該些二極體之間加以隔離，並用以防止寄生PNP電晶體(parasitic PNP transistor)或寄生NPN電晶體(parasitic NPN transistor)在該半導體基板上不同導電類型之該些摻雜區域之間所引發的拴鎖效應(latch-up)，該半導體基板更包含：一N型基板，用以支撐一N型磊晶層，其中該PN接面係於該半導體基板上形成垂直PN接面，該半導體基板具有一陽極與一陰極，該陽極係設置於該半導體基板下表面以連接至一高電壓，該陰極係設置於該半導體基板上表面以連接至一低電壓；以及一P型主體區域，該P型主體區域設置於該N型磊晶層上的二該絕緣溝槽之間，其中該P型主體區域更包圍著一齊納N型摻雜區域，而形成一垂直堆疊PN接面，以構成一齊納二極體於二該絕緣溝槽之間；至少二輸入/輸出(I/O)接觸墊，每一輸入/輸出接觸墊係和二PN接面接觸分別用為一高壓側(high-side)二極體與一低壓側(low-side)二極體，該高壓側二極體與該低壓側二極體藉由一絕緣溝槽和覆蓋該絕緣溝槽之一絕緣層上方的每一該輸入/輸出接觸墊相隔離；以及至少二垂直堆疊PN接面，設置於二該絕緣溝槽之間，並具有較大側向寬度於該半導體基板上，以構成一齊納二極體(Zener diode)。
  2. 如申請專利範圍第1項所述之使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構，其中該些PN接面係於該半導體基板上形成垂直PN接面，該半導體基板具有包含第一導電類型與第二導電類型之複數電極，以分別連接至分別設置於該半導體基板上表面與下表面之一高電壓與一低電壓。
  3. 如申請專利範圍第1項所述之使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構，其中該齊納二極體更藉由二絕緣溝槽加以隔離，該二絕緣溝槽係鄰近該齊納二極體設置並使該齊納二極體和該垂直暫態電壓抑制二極體陣列結構之另一二極體相隔離，藉此防止該拴鎖效應的發生。
  4. 一種使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體(transient voltage suppressing；TVS)陣列結構，係設置於一半導體基板上，且該半導體基板支撐有一第一導電類型之一磊晶層，其中該無閉鎖垂直暫態電壓抑制二極體陣列結構更包含：複數絕緣溝槽，開設於該磊晶層上，且在二該絕緣溝槽之間具有一第二導電類型之一主體區域於該磊晶層上，該主體區域更包含一第一導電類型之低壓側二極體摻雜區域，用以構成一低壓側二極體；以及該磊晶層更包含一第二導電類型之摻雜區域，該摻雜區域係和該磊晶層形成一PN接面而構成一高壓側二極體，用以透過一輸入/輸出(I/O)接觸墊電性連接至該低壓側二極體，又該低壓側二極體與該高壓側二極體藉由位於該輸入/輸出接觸墊下方之一該絕緣溝槽來隔離，該磊晶層更包含複數垂直PN接面所構成的複數二極體並電性連接至第一導電類型與第二導電類型之複數電極，用以分別連接至分別設置於該半導體基板上表面與下表面，該半導體基板更包含一N型磊晶層，用以支撐一N型磊晶層，以形成複數PN接面於該N型磊晶層上作為該半導體基板上之垂直PN接面，且該半導體基板具有一陽極與一陰極，該 陽極係設置於該半導體基板下表面以連接至一高電壓，該陰極係設置於該半導體基板上表面以連接至一低電壓，該主體區域係為一P型主體區域，並設置於該N型磊晶層上的二該絕緣溝槽之間，其中該P型主體區域更包圍著一齊納N型摻雜區域，而形成一垂直堆疊PN接面，以構成一齊納二極體於二該絕緣溝槽之間；以及一齊納摻雜區域，係為該第一導電類型並位於該主體區域上，用以構成一齊納二極體(Zener diode)，該齊納二極體包含垂直堆疊PN接面，用來負載一暫態電流以抑制一暫態電壓，該齊納二極體更藉由二絕緣溝槽加以隔離，該二絕緣溝槽係鄰近該齊納二極體設置並使該齊納二極體和該垂直暫態電壓抑制二極體陣列結構之另一二極體相隔離，藉此防止一拴鎖效應的發生。
  5. 一種垂直暫態電壓抑制二極體(TVS)陣列結構之製造方法，大體上係依照一垂直式半導體功率裝置之製造方法，該方法包含：開設複數絕緣溝槽於一半導體基板上的一第一導電類型之一磊晶層上，並藉由使用一主體遮罩，用以摻雜一具有一第二導電類型之主體區域於二該絕緣溝槽之間；使用一源極遮罩，用以植入該第一導電類型之複數摻雜區域，以構成複數二極體，其中該些絕緣溝槽將該些二極體加以隔離，並用以防止寄生PNP電晶體(parasitic PNP transistor)或寄生NPN電晶體(parasitic NPN transistor)在該半導體基板上不同導電類型之該些摻雜區域之間所引發的拴鎖效應(latch-up)；以及使用一接觸遮罩，以植入遠離該主體區域之該第二導電類型的複數摻雜區域，用以和該磊晶層構成複數高壓側二極體，並用以透過通過該些絕緣溝槽之複數輸入/輸出(I/O)接觸墊來連接至包圍於該主體區域內的低壓側二極體，使該低壓側二極體與該高壓側二極體藉由位於一該輸入/輸出接觸墊下方之一該絕緣溝槽來隔 離。
  6. 如申請專利範圍第5項所述之垂直暫態電壓抑制二極體陣列結構之製造方法，其中該植入該第二導電類型的複數摻雜區域構成該複數二極體之步驟，更包含有一形成一具有較大寬度的齊納摻雜區域之步驟，其中該齊納摻雜區域係和該磊晶層中之該主體區域形成複數垂直堆疊PN接面，用以構成一齊納二極體(Zener diode)。
  7. 如申請專利範圍第6項所述之垂直暫態電壓抑制二極體陣列結構之製造方法，其中該開設複數絕緣溝槽之步驟，更包含一開設複數絕緣溝槽鄰近於該齊納二極體之步驟，將該齊納二極體加以隔離，用以防止不同導電類型之該些摻雜區域之該拴鎖效應的發生。
  8. 如申請專利範圍第5項所述之垂直暫態電壓抑制二極體陣列結構之製造方法，更包含沉積一金屬層於該半導體基板之下表面，用以作為該垂直暫態電壓抑制二極體陣列結構之一電極。
  9. 如申請專利範圍第5項所述之垂直暫態電壓抑制二極體陣列結構之製造方法，更包含沉積一金屬層於該半導體基板之表面，並對於該金屬層進行圖案化，用以作為複數輸入/輸出接觸墊，並作為該垂直暫態電壓抑制二極體陣列結構之一電極，且該電極之導電類型係和形成於該半導體基板之下表面之電極的導電類型相反。
TW096140392A 2006-11-30 2007-10-26 使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構及其製造方法 TWI405323B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/606,602 US7880223B2 (en) 2005-02-11 2006-11-30 Latch-up free vertical TVS diode array structure using trench isolation

Publications (2)

Publication Number Publication Date
TW200828569A TW200828569A (en) 2008-07-01
TWI405323B true TWI405323B (zh) 2013-08-11

Family

ID=39468519

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096140392A TWI405323B (zh) 2006-11-30 2007-10-26 使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構及其製造方法

Country Status (7)

Country Link
US (3) US7880223B2 (zh)
EP (1) EP2089903A2 (zh)
JP (1) JP5333857B2 (zh)
KR (1) KR101394913B1 (zh)
CN (1) CN101506974B (zh)
TW (1) TWI405323B (zh)
WO (1) WO2008066903A2 (zh)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781826B2 (en) * 2006-11-16 2010-08-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
US8218276B2 (en) * 2006-05-31 2012-07-10 Alpha and Omega Semiconductor Inc. Transient voltage suppressor (TVS) with improved clamping voltage
US9793256B2 (en) * 2006-11-30 2017-10-17 Alpha And Omega Semiconductor Incorporated Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)
US9202938B2 (en) * 2006-11-30 2015-12-01 Alpha And Omega Semiconductor Incorporated Latch-up free vertical TVS diode array structure using trench isolation
DE102007024355B4 (de) * 2007-05-24 2011-04-21 Infineon Technologies Ag Verfahren zum Herstellen einer Schutzstruktur
US8217419B2 (en) * 2007-06-15 2012-07-10 Rohm Co., Ltd. Semiconductor device
US7538395B2 (en) * 2007-09-21 2009-05-26 Semiconductor Components Industries, L.L.C. Method of forming low capacitance ESD device and structure therefor
US7579632B2 (en) * 2007-09-21 2009-08-25 Semiconductor Components Industries, L.L.C. Multi-channel ESD device and method therefor
US7666751B2 (en) 2007-09-21 2010-02-23 Semiconductor Components Industries, Llc Method of forming a high capacitance diode and structure therefor
JP5365019B2 (ja) * 2008-02-08 2013-12-11 富士電機株式会社 半導体装置
JP5264597B2 (ja) * 2008-04-03 2013-08-14 三菱電機株式会社 赤外線検出素子及び赤外線固体撮像装置
US7842969B2 (en) * 2008-07-10 2010-11-30 Semiconductor Components Industries, Llc Low clamp voltage ESD device and method therefor
US7955941B2 (en) * 2008-09-11 2011-06-07 Semiconductor Components Industries, Llc Method of forming an integrated semiconductor device and structure therefor
US8089095B2 (en) 2008-10-15 2012-01-03 Semiconductor Components Industries, Llc Two terminal multi-channel ESD device and method therefor
US7812367B2 (en) 2008-10-15 2010-10-12 Semiconductor Components Industries, Llc Two terminal low capacitance multi-channel ESD device
CN101826716B (zh) * 2009-03-05 2014-05-21 万国半导体股份有限公司 设有势垒齐纳二极管的低压瞬时电压抑制器
US8288839B2 (en) * 2009-04-30 2012-10-16 Alpha & Omega Semiconductor, Inc. Transient voltage suppressor having symmetrical breakdown voltages
US8558276B2 (en) * 2009-06-17 2013-10-15 Alpha And Omega Semiconductor, Inc. Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)
FR2953062B1 (fr) * 2009-11-24 2011-12-16 St Microelectronics Tours Sas Diode de protection bidirectionnelle basse tension
US8169000B2 (en) * 2010-07-15 2012-05-01 Amazing Microelectronic Corp. Lateral transient voltage suppressor with ultra low capacitance
US8237193B2 (en) * 2010-07-15 2012-08-07 Amazing Microelectronic Corp. Lateral transient voltage suppressor for low-voltage applications
CN102376702B (zh) 2010-08-20 2014-09-17 半导体元件工业有限责任公司 两端子多通道esd器件及其方法
US8431999B2 (en) * 2011-03-25 2013-04-30 Amazing Microelectronic Corp. Low capacitance transient voltage suppressor
US8664080B2 (en) * 2011-05-25 2014-03-04 Texas Instruments Incorporated Vertical ESD protection device
US8710627B2 (en) 2011-06-28 2014-04-29 Alpha And Omega Semiconductor Incorporated Uni-directional transient voltage suppressor (TVS)
US8698196B2 (en) 2011-06-28 2014-04-15 Alpha And Omega Semiconductor Incorporated Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage
US8304838B1 (en) * 2011-08-23 2012-11-06 Amazing Microelectronics Corp. Electrostatic discharge protection device structure
CN102290419B (zh) * 2011-08-24 2013-02-13 浙江大学 一种基于齐纳二极管的瞬态电压抑制器
CN102290417B (zh) * 2011-08-24 2012-10-24 浙江大学 一种基于dtscr的瞬态电压抑制器
JP5749616B2 (ja) * 2011-09-27 2015-07-15 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
CN102332466B (zh) * 2011-10-18 2012-10-31 宜兴市环洲微电子有限公司 一种用于制作芯片的双台面硅片
TWI456736B (zh) * 2011-11-25 2014-10-11 Amazing Microelectronic Corp 避免漏電流之暫態電壓抑制器
CN102437156B (zh) * 2011-12-13 2014-02-26 杭州士兰集成电路有限公司 超低电容瞬态电压抑制器件及其制造方法
CN102593155B (zh) * 2012-03-01 2014-03-12 浙江大学 一种基于多孔道均流的瞬态电压抑制器
CN103367393B (zh) * 2012-03-28 2016-04-13 上海华虹宏力半导体制造有限公司 瞬态电压抑制器件及制造工艺方法
US8779518B2 (en) * 2012-12-04 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for ESD protection
US9337178B2 (en) * 2012-12-09 2016-05-10 Semiconductor Components Industries, Llc Method of forming an ESD device and structure therefor
CN105051887B (zh) 2013-02-28 2018-04-17 株式会社村田制作所 半导体装置
JP5796692B2 (ja) * 2013-02-28 2015-10-21 株式会社村田製作所 Ｅｓｄ保護デバイス
CN205508776U (zh) 2013-02-28 2016-08-24 株式会社村田制作所 半导体装置
CN205104477U (zh) 2013-04-05 2016-03-23 株式会社村田制作所 Esd保护器件
US9508841B2 (en) * 2013-08-01 2016-11-29 General Electric Company Method and system for a semiconductor device with integrated transient voltage suppression
CN103474427B (zh) * 2013-09-16 2016-01-06 杭州士兰集成电路有限公司 集成式单向超低电容tvs器件及其制造方法
CN104465643A (zh) * 2013-09-17 2015-03-25 立锜科技股份有限公司 瞬时电压抑制元件及其制造方法
KR101592232B1 (ko) 2014-02-17 2016-02-05 주식회사 시지트로닉스 저정전용량 tvs 제조방법 및 그 방법으로 제조된 tvs 소자
US10103540B2 (en) * 2014-04-24 2018-10-16 General Electric Company Method and system for transient voltage suppression devices with active control
TWI563627B (en) * 2014-06-13 2016-12-21 Richtek Technology Corp Transient voltage suppression device and manufacturing method thereof
CN105185783B (zh) * 2015-08-20 2018-08-24 北京燕东微电子有限公司 容性二极管组件及其制造方法
CN105185782B (zh) * 2015-08-20 2018-05-11 北京燕东微电子有限公司 容性二极管组件及其制造方法
TWI580002B (zh) * 2015-08-26 2017-04-21 立錡科技股份有限公司 暫態電壓抑制元件及其製造方法
US9640523B2 (en) 2015-09-08 2017-05-02 Hong Kong Applied Science and Technology Research Institute Company Limited Lateral-diode, vertical-SCR hybrid structure for high-level ESD protection
US10217733B2 (en) 2015-09-15 2019-02-26 Semiconductor Components Industries, Llc Fast SCR structure for ESD protection
CN105489612B (zh) * 2015-12-07 2019-07-23 上海长园维安微电子有限公司 基于soi基底的低漏电低电容tvs阵列及其制备方法
TWI584382B (zh) * 2016-02-01 2017-05-21 力祥半導體股份有限公司 暫態電壓抑制器之二極體元件及其製造方法
US10043793B2 (en) * 2016-02-03 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and circuit
TWI675448B (zh) 2016-04-14 2019-10-21 力智電子股份有限公司 多通道暫態電壓抑制器
CN107346791B (zh) * 2016-05-06 2020-10-16 北大方正集团有限公司 瞬变电压抑制二极管的制备方法和瞬变电压抑制二极管
CN105932010B (zh) * 2016-05-10 2018-09-18 北京燕东微电子有限公司 瞬态电压抑制器
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
CN106169508B (zh) * 2016-08-31 2022-12-20 北京燕东微电子有限公司 一种双向超低电容瞬态电压抑制器及其制作方法
US10347621B2 (en) * 2016-10-12 2019-07-09 Texas Instruments Incorporated Electrostatic discharge guard ring with snapback protection
US10157904B2 (en) 2017-03-31 2018-12-18 Alpha And Omega Semiconductor (Cayman) Ltd. High surge bi-directional transient voltage suppressor
US10062682B1 (en) 2017-05-25 2018-08-28 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance bidirectional transient voltage suppressor
US10211199B2 (en) 2017-03-31 2019-02-19 Alpha And Omega Semiconductor (Cayman) Ltd. High surge transient voltage suppressor
CN107316863B (zh) * 2017-07-12 2019-05-07 新昌县佳良制冷配件厂 瞬态电压抑制器及其制作方法
US10141300B1 (en) 2017-10-19 2018-11-27 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor
TWI737915B (zh) 2018-06-05 2021-09-01 源芯半導體股份有限公司 暫態電壓抑制元件
CN109065541B (zh) * 2018-07-17 2021-04-13 张辉 一种双向瞬态电压抑制器及制备方法
JP6968042B2 (ja) * 2018-07-17 2021-11-17 三菱電機株式会社 ＳｉＣ−ＳＯＩデバイスおよびその製造方法
US10573635B2 (en) 2018-07-23 2020-02-25 Amazing Microelectronics Corp. Transient voltage suppression device with improved electrostatic discharge (ESD) robustness
US10825805B2 (en) * 2018-10-26 2020-11-03 Alpha & Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor including a punch-through silicon controlled rectifier as low-side steering diode
CN109326592B (zh) * 2018-10-26 2020-08-28 南京溧水高新创业投资管理有限公司 瞬态电压抑制器及其制造方法
CN111446691B (zh) * 2019-01-17 2023-12-01 源芯半导体股份有限公司 暂态电压抑制元件
RU2698741C1 (ru) * 2019-01-30 2019-08-29 Акционерное общество "Научно-исследовательский институт молекулярной электроники" Способ изготовления вертикального низковольтного ограничителя напряжения
TWI765166B (zh) * 2019-07-16 2022-05-21 源芯半導體股份有限公司 暫態電壓抑制元件
CN111696982B (zh) * 2020-06-09 2023-10-03 深圳能芯半导体有限公司 一种基体分离n型功率管esd电路和设置方法
US11349017B2 (en) 2020-06-23 2022-05-31 Amazing Microelectronic Corp. Bidirectional electrostatic discharge (ESD) protection device
US12087759B2 (en) 2021-06-30 2024-09-10 Alpha And Omega Semiconductor International Lp Low capacitance two channel and multi-channel TVS with effective inter-connection
US20230168298A1 (en) * 2021-11-29 2023-06-01 Amazing Microelectronic Corp. Diode test module for monitoring leakage current and its method thereof
CN114334956B (zh) * 2022-03-15 2022-06-07 成都市易冲半导体有限公司 具有耐极负电压高压引脚的交流功率开关的隔离防护结构
CN114759026B (zh) * 2022-04-21 2023-04-28 电子科技大学 新型双回滞静电保护器件
CN117174761B (zh) * 2023-11-02 2024-01-05 富芯微电子有限公司 一种电压非对称双向tvs器件及其制造方法
CN117558727A (zh) * 2023-11-13 2024-02-13 深圳市创飞芯源半导体有限公司 一种带esd保护的中压nmos功率器件和制造方法
CN118412276B (zh) * 2024-06-28 2024-09-06 江西萨瑞微电子技术有限公司 一种双向tvs芯片及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862233A (en) * 1986-06-18 1989-08-29 Nissan Motor Company Limited Integrated circuit device having vertical MOS provided with Zener diode
US6265743B1 (en) * 1997-04-11 2001-07-24 Mitsubishi Denki Kabushiki Kaisha Trench type element isolation structure
US20020113293A1 (en) * 2001-02-21 2002-08-22 Semiconductor Components Industries, Llc Semiconductor component and method of manufacturing
US20030173636A1 (en) * 2002-03-12 2003-09-18 Vrej Barkhordarian Compound semiconductor protection device for low voltage and high speed data lines
US20040085691A1 (en) * 2002-11-01 2004-05-06 Ming-Dou Ker Low-voltage triggered PNP for ESD protection in mixed voltage I/O interface
US6867436B1 (en) * 2003-08-05 2005-03-15 Protek Devices, Lp Transient voltage suppression device
US20050062101A1 (en) * 2003-08-29 2005-03-24 Akio Sugi Semiconductor device
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2689317B1 (fr) * 1992-03-26 1994-06-17 Sgs Thomson Microelectronics Circuit integre constituant un reseau de diodes de protection.
JPH06291337A (ja) * 1993-03-31 1994-10-18 Nec Kansai Ltd 定電圧ダイオード
FR2708145B1 (fr) * 1993-07-21 1995-10-06 Sgs Thomson Microelectronics Composant monolithique comprenant une diode de protection en parallèle avec une pluralité de paires de diodes en série.
EP0864178A4 (en) * 1995-10-02 2001-10-10 Siliconix Inc SLIDED GRID MOSFET HAVING AN INTEGRATED TEMPERATURE SENSING DIODE
JP4256544B2 (ja) * 1998-08-25 2009-04-22 シャープ株式会社 半導体集積回路の静電気保護装置、その製造方法および静電気保護装置を用いた静電気保護回路
US6891207B2 (en) * 2003-01-09 2005-05-10 International Business Machines Corporation Electrostatic discharge protection networks for triple well semiconductor devices
JP4423466B2 (ja) * 2004-02-17 2010-03-03 富士電機システムズ株式会社 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862233A (en) * 1986-06-18 1989-08-29 Nissan Motor Company Limited Integrated circuit device having vertical MOS provided with Zener diode
US6265743B1 (en) * 1997-04-11 2001-07-24 Mitsubishi Denki Kabushiki Kaisha Trench type element isolation structure
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture
US20020113293A1 (en) * 2001-02-21 2002-08-22 Semiconductor Components Industries, Llc Semiconductor component and method of manufacturing
US20030173636A1 (en) * 2002-03-12 2003-09-18 Vrej Barkhordarian Compound semiconductor protection device for low voltage and high speed data lines
US20040085691A1 (en) * 2002-11-01 2004-05-06 Ming-Dou Ker Low-voltage triggered PNP for ESD protection in mixed voltage I/O interface
US6867436B1 (en) * 2003-08-05 2005-03-15 Protek Devices, Lp Transient voltage suppression device
US20050062101A1 (en) * 2003-08-29 2005-03-24 Akio Sugi Semiconductor device

Also Published As

Publication number Publication date
WO2008066903A2 (en) 2008-06-05
EP2089903A2 (en) 2009-08-19
US20120168900A1 (en) 2012-07-05
US20070073807A1 (en) 2007-03-29
JP2010512003A (ja) 2010-04-15
KR101394913B1 (ko) 2014-05-27
TW200828569A (en) 2008-07-01
CN101506974B (zh) 2013-04-10
CN101506974A (zh) 2009-08-12
JP5333857B2 (ja) 2013-11-06
US7880223B2 (en) 2011-02-01
US20110127577A1 (en) 2011-06-02
US8461644B2 (en) 2013-06-11
WO2008066903A3 (en) 2008-07-31
KR20090091784A (ko) 2009-08-28

Similar Documents

Publication Publication Date Title
TWI405323B (zh) 使用溝槽隔離之無閉鎖垂直暫態電壓抑制二極體陣列結構及其製造方法
US9461031B1 (en) Latch-up free vertical TVS diode array structure using trench isolation
US7554839B2 (en) Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch
US8338854B2 (en) TVS with low capacitance and forward voltage drop with depleted SCR as steering diode
US8039899B2 (en) Electrostatic discharge protection device
US6236087B1 (en) SCR cell for electrical overstress protection of electronic circuits
US8835977B2 (en) TVS with low capacitance and forward voltage drop with depleted SCR as steering diode
TWI382627B (zh) 製造在絕緣物上矽層中的暫態電壓抑制器的方法
US7868387B2 (en) Low leakage protection device
US20110204415A1 (en) High holding voltage device
US20140159102A1 (en) High holding voltage electrostatic discharge protection device
US8859361B1 (en) Symmetric blocking transient voltage suppressor (TVS) using bipolar NPN and PNP transistor base snatch
KR101392587B1 (ko) 고전압 정전기 방전 보호 소자
EP2846359B1 (en) LVTSCR device
US9991173B2 (en) Bidirectional semiconductor device for protection against electrostatic discharges
JP5529414B2 (ja) 静電破壊保護回路
JP5529436B2 (ja) 静電破壊保護回路
CN112447703A (zh) 静电放电防护元件
CN112117269A (zh) 无回滞效应硅控整流器型esd保护结构及其实现方法
CN117917780A (zh) 单向高电压穿通tvs二极管及制造方法