JP5333857B2 - トレンチ絶縁を用いたラッチアップ現象のない垂直方向tvsダイオードアレイ構造 - Google Patents
トレンチ絶縁を用いたラッチアップ現象のない垂直方向tvsダイオードアレイ構造 Download PDFInfo
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- JP5333857B2 JP5333857B2 JP2009539339A JP2009539339A JP5333857B2 JP 5333857 B2 JP5333857 B2 JP 5333857B2 JP 2009539339 A JP2009539339 A JP 2009539339A JP 2009539339 A JP2009539339 A JP 2009539339A JP 5333857 B2 JP5333857 B2 JP 5333857B2
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- 238000009413 insulation Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 230000003071 parasitic effect Effects 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 230000001052 transient effect Effects 0.000 claims abstract description 16
- 210000000746 body region Anatomy 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000002019 doping agent Substances 0.000 claims description 11
- 230000008878 coupling Effects 0.000 claims 5
- 238000010168 coupling process Methods 0.000 claims 5
- 238000005859 coupling reaction Methods 0.000 claims 5
- 239000002184 metal Substances 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 2
- 239000007943 implant Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000003491 array Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Description
Claims (14)
- 半導体基板に複数のPN接合を構成するために、複数の異なる導電型の複数のドーパント領域として形成された、複数のダイオードと、
寄生PNPもしくはNPNトランジスタを絶縁するために前記複数のダイオードの間に配置され、前記寄生PNPもしくはNPNトランジスタが、前記半導体基板にある複数の異なる導電型の前記複数のドープされた領域の間でラッチアップするのを防止する、絶縁トレンチと、
を含み、
前記複数のPN接合が、前記半導体基板に垂直方向の複数のPN接合として形成され、
第1の電気伝導性タイプの電極および第2の電気伝導性タイプの電極が、前記半導体基板の上表面と、底表面とに別々に配置された高電圧および低電圧へとそれぞれ結合し、
2つの前記絶縁トレンチの間に配置され、前記半導体基板においてより大きな横方向の幅を有する、ツェナーダイオードを構成するための少なくとも2つの垂直方向に積層されたPN接合を、さらに含み、
前記ツェナーダイオードがさらに、前記ツェナーダイオードの直接隣に配置され、前記ツェナーダイオードを前記TVSアレイの別の前記複数のダイオードから絶縁する2つの絶縁トレンチによって絶縁され、それによって前記ラッチアップが防止される、
過渡電圧サプレッサ(TVS)アレイ。 - 少なくも2つの入力/出力(I/O)接合パッドをさらに含み、
ハイサイド・ダイオードおよびローサイド・ダイオードとしてそれぞれ機能し、絶縁トレンチによって絶縁される2つのPN接合と、各接合パッドが結合し、
各前記I/O接合パッドが、前記絶縁トレンチを覆う絶縁層にかぶせられる、
請求項1のTVSアレイ。 - 前記半導体基板がさらに、N型エピタキシャル層を支持するN型基板を含み、ここで、前記複数のPN接合が複数の垂直方向PN接合として前記半導体基板に形成され、
高電圧と結合するための陽極電極が前記基板の底表面に配置され、低電圧と結合するための陰極電極が前記基板の上表面に配置される、
請求項1のTVSアレイ。 - 前記半導体基板がさらに、前記N型エピタキシャル層において、2つの前記絶縁トレンチの間に配置されたP‐ボディ領域を含み、
ここで、前記ボディ領域がさらに、2つの前記絶縁トレンチの間のツェナーダイオードを構成する垂直方向に積層された複数のPN接合を形成するようにツェナーN‐ドープ領域を取り囲む、
請求項3のTVSアレイ。 - 前記半導体基板がさらに、前記N型エピタキシャル層において、2つの前記絶縁トレンチの間に配置されたP‐ボディ領域を含み、
ここで、前記ボディ領域がさらに、前記TVSアレイのローサイド・ダイオードとして機能するために、前記P‐ボディとPN接合を形成するようにN‐ドープ領域を取り囲む、
請求項3のTVSアレイ。 - 第1の導電型のエピタキシャル層を支持する半導体基板の上に配置された、過渡電圧サプレッサ(TVS)アレイであって、
ここで、
前記TVSアレイがさらに、
前記エピタキシャル層に開口された複数の絶縁トレンチであって、2つの前記トレンチの間にある前記エピタキシャル層に第2の導電型のボディ領域を備える、複数の絶縁トレンチと、
過渡電圧を抑制するために過渡電流を運ぶ垂直方向に積層された複数のPN接合を含むツェナーダイオードを構成するための、前記ボディ領域にある、前記第1の導電型のツェナードープ領域と、
を含み、
前記ツェナーダイオードがさらに、前記ツェナーダイオードを前記TVSアレイの別のPN接合から絶縁するために、前記ツェナーダイオードに直接隣接して配置された2つの絶縁トレンチによって絶縁され、それによってラッチアップが防止され、
前記ボディ領域がさらに、ローサイド・ダイオードを構成するために、前記第1の導電型のローサイド・ダイオード・ドープ領域を含み、
前記エピタキシャル層がさらに、前記ローサイド・ダイオードと入力‐出力(I/O)接合パッドを介して電気的に結合するハイサイド・ダイオードを構成するために、前記エピタキシャル層とPN接合を形成する前記第2の導電型のドープ領域を含む、
過渡電圧サプレッサ(TVS)アレイ。 - 前記エピタキシャル層がさらに、
複数のダイオードを構成する複数の垂直方向のPN接合をその中に含み、
前記半導体基板の上表面と、底表面とに別々に配置された、高電圧と低電圧とにそれぞれ結合するための第1および第2の電気伝導性タイプの電極と、電気的に結合する、
請求項6のTVSアレイ。 - 前記半導体基板がさらに、
前記半導体基板の複数の垂直方向PN接合として前記N型エピタキシャル層に複数のPN接合を形成するために、N型エピタキシャル層を支持するN型基板を含み、
高電圧と結合するための陽極電極が前記基板の底表面に配置され、低電圧と結合するための陰極電極が前記基板の上表面に配置される、
請求項6のTVSアレイ。 - 前記ボディ領域が、前記N型エピタキシャル層において、2つの前記絶縁トレンチの間に配置されたP‐ボディ領域であり、
ここで、前記ボディ領域がさらに、2つの前記絶縁トレンチの間のツェナーダイオードを構成する垂直方向に積層された複数のPN接合を形成するようにツェナーN‐ドープ領域を取り囲む、
請求項8のTVSアレイ。 - 前記ボディ領域が、前記N型エピタキシャル層において、2つの前記絶縁トレンチの間に配置されたP‐ボディ領域であり、
ここで、前記ボディ領域はさらに、前記TVSアレイのローサイド・ダイオードとして機能するために、前記P‐ボディとPN接合を形成するようにN‐ドープ領域を取り囲む、
請求項8のTVSアレイ。 - 垂直方向半導体電源装置を製造するための製造処理に実質的に従う、過渡電圧サプレッサ(TVS)アレイを製造するための方法であって、
半導体基板において第1の導電型のエピタキシャル層に複数の絶縁トレンチを開口し、それに続いて、2つの前記絶縁トレンチの間に第2の導電型を有するボディ領域をドープするために、ボディマスクを適用するステップと、
複数のダイオードを構成する前記第1の導電型の複数のドープ領域を注入するために、ソースマスクを適用するステップと、
を含み、
ここで、前記複数の絶縁トレンチは、寄生PNPもしくはNPNトランジスタを絶縁し、前記寄生PNPもしくはNPNトランジスタが複数の異なる導電型の前記複数のドープ領域の間でラッチアップするのを防止し、
前記複数の絶縁トレンチを横断する複数の入力‐出力(IO)接合パッドを用いて、前記ボディ領域に取り囲まれた前記複数のローサイド・ダイオードに結合する、前記エピタキシャル層を備えた複数のハイサイド・ダイオードを構成するために、前記ボディ領域から離して、前記第2の導電型の複数のドープ領域を注入するための接合マスクを適用するステップ、をさらに含み、
複数のダイオードを構成する、前記第1の導電型の複数のドープ領域を注入する前記ステップが、
より大きな幅を有するツェナードープ領域を形成するステップをさらに含み、
ここで、前記ツェナードープ領域は、前記エピタキシャル層にある前記ボディ領域と共にツェナーダイオードとして機能するための垂直方向に積層された複数のPN接合を含む、
方法。 - 複数の絶縁トレンチを開口する前記ステップがさらに、
異なる複数の導電型の前記複数のドープ領域の間の前記ラッチアップを防止するために、前記ツェナーダイオードに直接隣接して、前記ツェナーダイオードを絶縁するための複数の絶縁トレンチを開口するステップ、を含む、
請求項11の方法。 - 前記TVSアレイのための電極として機能するように、前記基板の底表面に金属層を堆積するステップ、
をさらに含む、請求項11の方法。 - 前記基板の上表面に金属層を堆積するステップと、
前記半導体基板の前記底表面に形成された電極とは反対の導電性を持った前記TVSアレイのための電極として働き、複数の入力‐出力接合パッドとして機能する前記金属層をパターニングするステップと、
をさらに含む、
請求項11の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/606,602 US7880223B2 (en) | 2005-02-11 | 2006-11-30 | Latch-up free vertical TVS diode array structure using trench isolation |
US11/606,602 | 2006-11-30 | ||
PCT/US2007/024621 WO2008066903A2 (en) | 2006-11-30 | 2007-11-30 | Latch-up free vertical tvs diode array structure using trench isolation |
Publications (2)
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JP2010512003A JP2010512003A (ja) | 2010-04-15 |
JP5333857B2 true JP5333857B2 (ja) | 2013-11-06 |
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EP (1) | EP2089903A2 (ja) |
JP (1) | JP5333857B2 (ja) |
KR (1) | KR101394913B1 (ja) |
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Families Citing this family (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7781826B2 (en) * | 2006-11-16 | 2010-08-24 | Alpha & Omega Semiconductor, Ltd. | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter |
US8218276B2 (en) * | 2006-05-31 | 2012-07-10 | Alpha and Omega Semiconductor Inc. | Transient voltage suppressor (TVS) with improved clamping voltage |
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DE102007024355B4 (de) * | 2007-05-24 | 2011-04-21 | Infineon Technologies Ag | Verfahren zum Herstellen einer Schutzstruktur |
US8217419B2 (en) * | 2007-06-15 | 2012-07-10 | Rohm Co., Ltd. | Semiconductor device |
US7538395B2 (en) * | 2007-09-21 | 2009-05-26 | Semiconductor Components Industries, L.L.C. | Method of forming low capacitance ESD device and structure therefor |
US7666751B2 (en) * | 2007-09-21 | 2010-02-23 | Semiconductor Components Industries, Llc | Method of forming a high capacitance diode and structure therefor |
US7579632B2 (en) * | 2007-09-21 | 2009-08-25 | Semiconductor Components Industries, L.L.C. | Multi-channel ESD device and method therefor |
JP5365019B2 (ja) * | 2008-02-08 | 2013-12-11 | 富士電機株式会社 | 半導体装置 |
JP5264597B2 (ja) * | 2008-04-03 | 2013-08-14 | 三菱電機株式会社 | 赤外線検出素子及び赤外線固体撮像装置 |
US7842969B2 (en) * | 2008-07-10 | 2010-11-30 | Semiconductor Components Industries, Llc | Low clamp voltage ESD device and method therefor |
US7955941B2 (en) * | 2008-09-11 | 2011-06-07 | Semiconductor Components Industries, Llc | Method of forming an integrated semiconductor device and structure therefor |
US8089095B2 (en) | 2008-10-15 | 2012-01-03 | Semiconductor Components Industries, Llc | Two terminal multi-channel ESD device and method therefor |
US7812367B2 (en) * | 2008-10-15 | 2010-10-12 | Semiconductor Components Industries, Llc | Two terminal low capacitance multi-channel ESD device |
CN101826716B (zh) * | 2009-03-05 | 2014-05-21 | 万国半导体股份有限公司 | 设有势垒齐纳二极管的低压瞬时电压抑制器 |
US8288839B2 (en) * | 2009-04-30 | 2012-10-16 | Alpha & Omega Semiconductor, Inc. | Transient voltage suppressor having symmetrical breakdown voltages |
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FR2953062B1 (fr) * | 2009-11-24 | 2011-12-16 | St Microelectronics Tours Sas | Diode de protection bidirectionnelle basse tension |
US8169000B2 (en) * | 2010-07-15 | 2012-05-01 | Amazing Microelectronic Corp. | Lateral transient voltage suppressor with ultra low capacitance |
US8237193B2 (en) * | 2010-07-15 | 2012-08-07 | Amazing Microelectronic Corp. | Lateral transient voltage suppressor for low-voltage applications |
CN102376702B (zh) | 2010-08-20 | 2014-09-17 | 半导体元件工业有限责任公司 | 两端子多通道esd器件及其方法 |
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US9337178B2 (en) | 2012-12-09 | 2016-05-10 | Semiconductor Components Industries, Llc | Method of forming an ESD device and structure therefor |
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US9508841B2 (en) | 2013-08-01 | 2016-11-29 | General Electric Company | Method and system for a semiconductor device with integrated transient voltage suppression |
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US10043793B2 (en) * | 2016-02-03 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and circuit |
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US10388781B2 (en) | 2016-05-20 | 2019-08-20 | Alpha And Omega Semiconductor Incorporated | Device structure having inter-digitated back to back MOSFETs |
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US10157904B2 (en) | 2017-03-31 | 2018-12-18 | Alpha And Omega Semiconductor (Cayman) Ltd. | High surge bi-directional transient voltage suppressor |
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US10573635B2 (en) | 2018-07-23 | 2020-02-25 | Amazing Microelectronics Corp. | Transient voltage suppression device with improved electrostatic discharge (ESD) robustness |
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US10825805B2 (en) * | 2018-10-26 | 2020-11-03 | Alpha & Omega Semiconductor (Cayman) Ltd. | Low capacitance transient voltage suppressor including a punch-through silicon controlled rectifier as low-side steering diode |
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RU2698741C1 (ru) * | 2019-01-30 | 2019-08-29 | Акционерное общество "Научно-исследовательский институт молекулярной электроники" | Способ изготовления вертикального низковольтного ограничителя напряжения |
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US11349017B2 (en) | 2020-06-23 | 2022-05-31 | Amazing Microelectronic Corp. | Bidirectional electrostatic discharge (ESD) protection device |
US20230168298A1 (en) * | 2021-11-29 | 2023-06-01 | Amazing Microelectronic Corp. | Diode test module for monitoring leakage current and its method thereof |
CN114334956B (zh) * | 2022-03-15 | 2022-06-07 | 成都市易冲半导体有限公司 | 具有耐极负电压高压引脚的交流功率开关的隔离防护结构 |
CN114759026B (zh) * | 2022-04-21 | 2023-04-28 | 电子科技大学 | 新型双回滞静电保护器件 |
CN117174761B (zh) * | 2023-11-02 | 2024-01-05 | 富芯微电子有限公司 | 一种电压非对称双向tvs器件及其制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0685441B2 (ja) * | 1986-06-18 | 1994-10-26 | 日産自動車株式会社 | 半導体装置 |
FR2689317B1 (fr) * | 1992-03-26 | 1994-06-17 | Sgs Thomson Microelectronics | Circuit integre constituant un reseau de diodes de protection. |
JPH06291337A (ja) * | 1993-03-31 | 1994-10-18 | Nec Kansai Ltd | 定電圧ダイオード |
FR2708145B1 (fr) * | 1993-07-21 | 1995-10-06 | Sgs Thomson Microelectronics | Composant monolithique comprenant une diode de protection en parallèle avec une pluralité de paires de diodes en série. |
WO1997013279A1 (en) * | 1995-10-02 | 1997-04-10 | Siliconix Incorporated | Trench-gated mosfet including integral temperature detection diode |
JP3904676B2 (ja) * | 1997-04-11 | 2007-04-11 | 株式会社ルネサステクノロジ | トレンチ型素子分離構造の製造方法およびトレンチ型素子分離構造 |
JP4256544B2 (ja) * | 1998-08-25 | 2009-04-22 | シャープ株式会社 | 半導体集積回路の静電気保護装置、その製造方法および静電気保護装置を用いた静電気保護回路 |
US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US6515345B2 (en) | 2001-02-21 | 2003-02-04 | Semiconductor Components Industries Llc | Transient voltage suppressor with diode overlaying another diode for conserving space |
US6683334B2 (en) | 2002-03-12 | 2004-01-27 | Microsemi Corporation | Compound semiconductor protection device for low voltage and high speed data lines |
TW561608B (en) * | 2002-11-01 | 2003-11-11 | Silicon Integrated Sys Corp | Electrostatic discharge protection apparatus for too-high or too-low input voltage reference level |
US6891207B2 (en) * | 2003-01-09 | 2005-05-10 | International Business Machines Corporation | Electrostatic discharge protection networks for triple well semiconductor devices |
US6867436B1 (en) | 2003-08-05 | 2005-03-15 | Protek Devices, Lp | Transient voltage suppression device |
US7109551B2 (en) * | 2003-08-29 | 2006-09-19 | Fuji Electric Holdings Co., Ltd. | Semiconductor device |
JP4423466B2 (ja) * | 2004-02-17 | 2010-03-03 | 富士電機システムズ株式会社 | 半導体装置 |
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WO2008066903A3 (en) | 2008-07-31 |
US20110127577A1 (en) | 2011-06-02 |
KR101394913B1 (ko) | 2014-05-27 |
KR20090091784A (ko) | 2009-08-28 |
US20070073807A1 (en) | 2007-03-29 |
WO2008066903A2 (en) | 2008-06-05 |
CN101506974B (zh) | 2013-04-10 |
TW200828569A (en) | 2008-07-01 |
US7880223B2 (en) | 2011-02-01 |
EP2089903A2 (en) | 2009-08-19 |
CN101506974A (zh) | 2009-08-12 |
US8461644B2 (en) | 2013-06-11 |
US20120168900A1 (en) | 2012-07-05 |
TWI405323B (zh) | 2013-08-11 |
JP2010512003A (ja) | 2010-04-15 |
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