TWI382627B - 製造在絕緣物上矽層中的暫態電壓抑制器的方法 - Google Patents
製造在絕緣物上矽層中的暫態電壓抑制器的方法 Download PDFInfo
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Description
本發明總體涉及製造暫態電壓抑制器(TVS)的電路結構和方法。更具體地,本發明涉及用於向TVS保護提供低電容的在絕緣物上矽(SOI)層中製造TVS的經改進的電路結構和方法。
設計和製造暫態電壓抑制器(TVS)的常規技術仍然面臨一定的技術難題。尤其是當應用標準CMOS工藝步驟在半導體襯底中的TVS上形成多個PN結二極體時,即會產生固有的PNP和NPN寄生電晶體。在ESD事件中或發生暫態電壓時,隨著施加於TVS陣列的較大的電壓,寄生NPN或PNP電晶體被導通或閉鎖。所述閉鎖可能導致突然和強烈的電壓急變返回。突然和較大的急變返回可能導致系統不穩定甚至損壞的不希望的效應。另外,TVS陣列中的寄生NPN或PNP電晶體的閉鎖還可能導致其他未預料或不需要的電壓電流暫態狀態。在應用TVS保護實現的器件中,由於寄生電容和寄生PNP或NPN閉鎖導致的技術難題不可能很容易解決。
通常,暫態電壓抑制器(TVS)普遍應用於保護積體電路免受由於不經意發生的在積體電路上施加超電壓而造成的損壞。積體電路一般設計成在正常的電壓範圍內運行。然而,在諸如靜電放電(ESD),快速電瞬變和放電的情形下,意外的和不受控制的高電壓可能突然作用到電路
上。因此需要TVS器件提供保護功能以規避在這樣的超電壓情形發生時可能發生的對積體電路造成的損壞。由於越來越多的設備用易於超電壓損壞的積體電路實現,因此對TVS保護的需求也日益增加。TVS的示例性應用在USB電源和資料線保護,數位元視頻界面,高速乙太網,筆記本電腦,監視器和平板顯示器中都能找到。
第1A圖和第1B圖分別顯示TVS器件的電路圖和電流電壓關係圖。當輸入電壓Vin小於擊穿電壓Vb時,理想的TVS完全阻斷電流(也就是零電流)以將漏電流減到最小。而且,理想條件下,在輸入電壓Vin大於擊穿電壓Vb的情況下,TVS接近於零電阻,以使暫態電壓能被有效箝制。TVS能用PN結器件實現,PN結器件具有擊穿電壓,當暫態輸入電壓超過該擊穿電壓時該PN結器件允許電流傳導以實現暫態電壓保護。然而,PN結型的TVS沒有少數載流子,並且由於如第1B圖所示的高電阻而具有較差的箝制性能。現在有應用雙極型電晶體的雪崩觸發導通的雙極型NPN/PNP的TVS實施方案。基極充滿少數載流子,並且因為雪崩電流通過雙極型增益而被放大,雙極型TVS能實現更好的電壓箝制。
隨著電子科技的發展,日益增多的設備和應用需要使用TVS二極體陣列進行ESD保護,尤其用於保護高帶寬資料匯流排。參考第2A圖的四通道TVS的電路圖和第2B圖的僅顯示陣列器件核心的TVS陣列的器件實施方案的側視截面圖。如第2A圖和第2B圖所示的TVS陣列包括若干
串聯的高壓側和低壓側換向二極體,其中高壓側換向二極體連接到Vcc,低壓側換向二極體連接到地電位。另外,這些高壓側和低壓側換向二極體與主齊納二極體並聯,其中該換向二極體較小並且具有較低的結電容。另外,如第2C圖所示,這樣的實施方案還產生另一個由於由寄生PNP和NPN電晶體誘發的可控矽(SCR)作用導致的閉鎖問題。主齊納二極體的擊穿觸發NPN使其導通,NPN的導通進一步使SCR導通而導致閉鎖。在高溫下,即使NPN沒有導通,通過寄生NPN的NP結的高漏電流也可能使SCR導通而導致閉鎖。為了抑制由寄生PNP和NPN電晶體誘發的SCR作用而導致的閉鎖,半導體襯底上的實際器件需要在襯底上的如第2B圖所示的可能直至100微米或更大距離的橫向擴展,並且所述抑制通常還不足夠有效。
因此,在電路設計和器件製造的領域仍然需要提供新穎的和經改進的電路結構和製造方法來解決以上討論的難題。具體地,仍然需要提供能有效和方便地減小電容並且還能防止寄生PNP/NPN電晶體閉鎖的新穎的和經改進的TVS電路。
因此,本發明的一個方面是提供以SOI結構實施TVS以減小寄生電容並且防止寄生PNP-NPN電晶體閉鎖的新穎的和經改進的器件結構,因此可以克服以上討論的常規TVS陣列遭遇的難題和限制。
本發明的另一個方面是在SOI層中形成TVS保護電
路。相鄰二極體之間的側向距離可以被減少而與寄生電容和不經意的閉鎖無關。
簡略地,在優選實施例中,本發明公開了一種半導體襯底上支撐的暫態電壓抑制(TVS)器件。該TVS器件包括設置在由構成絕緣物上矽(SOI)器件上的TVS的絕緣層絕緣的半導體襯底的頂層上的與高壓側和低壓側二極體一起發揮作用以箝制暫態電壓的箝位元二極體。在一個示範性實施例中,該絕緣層還包括厚體氧化物(BOX)層。在另一個特定的示範性實施例中,該絕緣層包括厚體氧化物(BOX)層,該厚體氧化物層具有250埃到1微米範圍內的厚度以承受所施加的高於25伏的擊穿電壓。在另一個示例性實施例中,箝位二極體進一步由P阱包圍,並且該P阱形成在設置於所述絕緣層上方的p-/p+襯底層的頂部。
本發明還公開了一種製造具有集成暫態電壓抑制(TVS)器件的電子器件的方法。該方法包括通過在絕緣層上方形成作為絕緣物上矽(SOI)層的矽層和形成與高壓側和低壓側二極體一起發揮作用以箝制SOI層中的電子器件的暫態電壓的箝位元二極體而在半導體襯底上製造TVS陣列的步驟。在一個示範性實施例中,形成所述絕緣層的工藝還包括在半導體襯底上形成厚體氧化物層的步驟。在一個特定的實施例中,通過在P-晶片的頂表面形成厚氧化物層,然後將兩個晶片的氧化物層面對面鍵合和熔融在一起,最後將襯底研磨成所需要厚度而形成BOX層。在另一個特定的實施例中,該方法還包括深摻雜注入半導體襯底
以將BOX層上方的P-襯底層轉化為P+層的步驟。
結合各個附圖閱讀下文對優選實施例的詳細說明後,本發明的上述和其他目的和優點對於本領域的普通熟練技術人員無疑是顯而易見的。
第3A圖到第3C圖是顯示本發明的形成在絕緣物上矽(SOI)上的TVS的箝位二極體和高壓側/低壓側二極體的截面圖。P型襯底105上澱積厚體氧化物(BOX)層110。BOX層110具有250埃到1微米範圍內的厚度以承受所施加的高於25V的擊穿電壓。BOX的形成可以通過在P-晶片的頂表面上形成厚氧化物層,然後將兩個晶片上的氧化物層面對面鍵合和熔融在一起,最後將襯底研磨成所需要厚度而實現,這是眾所周知的工藝。可選的深摻雜注入可用於將BOX層上方的P-襯底層轉換為P+層。在如第3A圖所示的實施例中,箝位二極體形成在可選的P-/P+襯底層120頂部的P阱(PW)130中。P摻雜區135的分級摻雜分佈向由N+區140和P分級區135之間的結形成的箝位元二極體提供觸發電壓調節。PN結從二極體陰極金屬區150移開以避免在高電流擊穿過程中熔化。P分級區135和P+陽極接觸區165之間的距離向觸發電路中連接的雙極型器件提供所需要的分佈電阻。局部氧化矽(LOCOS)層170將P分級摻雜區135與連接到陽極電極160的P+陽極接觸區165分離。或者,可以使用未具體顯示的淺溝槽隔離(STI)代替LOCOS層170。
在BOX層110包括可選P-/P+襯底層120的同一個襯底105上的同一個工藝過程期間,可以在晶片的不同區域中形成低壓側/高壓側二極體。第3B圖顯示形成在與PW 130同時形成的P阱130'中的低壓側/高壓側二極體。N+區140'和P阱130'之間的二極體與N+區140同時形成。第3C圖顯示高壓側/低壓側二極體,其中高壓側/低壓側二極體可以形成在例如NW區130"的N阱中。高壓側和低壓側二極體由陽極接觸區165'和NW 130"形成。因此,箝位二極體也能形成在N阱NW(未具體顯示)中。
為了改進電壓箝制,在示例性實施例中,如第3D圖所示,在N+陰極摻雜區140,PW 130和P+摻雜區165之間實現雙極型NPN電晶體以替代作為主箝制組件的二極體。第3D圖顯示設置在P阱中的橫向NPN電晶體。具體地,N+區140,P阱130和N+區180形成NPN電晶體。同時N+區140和P阱130還形成觸發二極體,而當暫態電壓到達時,N+140和P阱130之間的結將被首先擊穿並且電流將通過P阱流到通過電極160接地的P+區165。當電流增大到足夠高時,由於P阱130中的分佈電阻導致的電壓降將導通雙極型NPN電晶體,從而提供經改進的箝制功能。第3E圖提供了一個替代實施例,在該實施例中橫向NPN結構還包括N阱190和N阱195。N阱190確保PN結從二極體陰極金屬區150移開以避免在高電流擊穿的過程中熔化。N阱190通過將發射極延伸至更深的深度擴大基極區,從而提供更深的載流子注入以增加高電流處理能力。N
阱190還增加了基極電阻,即使在較低電流的情況下也有利於容易導通雙極型NPN。
參考形成在薄矽層(約1μm)上的TVS的實施例的第4A圖到第4E圖,該實施例中的薄矽層部分耗盡。第4A圖是第3A圖的替代實施例,該實施例中P阱130的底部延伸至BOX層110,並且消除了P-/P+層120。第4B圖到第4E圖對應於第3B圖到第3E圖。除了由於薄矽層的耗盡而消除P-/P+層120之外,第4B圖到第4E圖的器件還用沉阱區175替代如第3B圖到第3E圖中所示的氧化物溝槽以將器件與其他區域隔離。重摻雜沉阱區175提供寄生雙極型電晶體的重摻雜基極區,因此抑制寄生雙極型器件的增益以避免導致閉鎖的急變返回。沉阱的使用還提供調節器件之間的距離的靈活性。
參考應用眾所周知的CMOS技術的方法製造的形成在全耗盡矽層上的TVS的實施例的第5A圖到第5E圖。第5A圖到第5E圖對應於第3A圖到第3E圖中的器件。第5A圖到第5E圖與第3A圖到第3E圖所示的實施例的不同之處在于在很薄的矽層上製造器件。為了在薄矽層上形成TVS器件,所製造的TVS器件中消除了第3A-3E圖中所示的P-/P+層120和P阱層130。由於矽層很薄,因此可以向襯底中注入氧以形成矽注入氧化(SIMOX)薄層替代厚BOX層以減少生產成本。如第5D圖和第5E圖所示,該截面圖分別顯示橫向雙極型電晶體和橫向SCR器件。觸發二極體路徑在第三維中連接(未顯示)。可以理解,基於以上
結構通過簡單變換摻雜類型的極性就可以製造互補的器件。
雖然按照目前的優選實施例描述了本發明,但是應該理解,本文公開的內容不能解釋為對本發明的限制。閱讀了上文的公開內容之後,對本發明的各種變化和修改對於本領域的普通熟練技術人員無疑是顯而易見的。因此,附後的權利要求應被理解為涵蓋落入本發明的真實精神和範圍之內的所有替代和修改。
105‧‧‧襯底
110‧‧‧BOX層
BOX‧‧‧厚體氧化物
120‧‧‧P-/P+襯底層
140、180、140’‧‧‧N+陰極摻雜區
150、PAD‧‧‧二極體陰極金屬區
165、P+‧‧‧P+陽極接觸區
160、GND‧‧‧電極
170‧‧‧局部氧化矽(LOCOS)層
190、195、NW‧‧‧N阱
PW、130、130’、130”‧‧‧P阱
135、PG‧‧‧P摻雜區
175、PS‧‧‧沉阱區
SIMOX‧‧‧矽注入氧化
第1A圖是顯示常規TVS器件的電路圖,第1B圖是用於說明TVS器件的反向特性的I-V圖即電流電壓圖;第2A圖顯示TVS陣列的電路圖,該TVS陣列包括連接到多個輸入/輸出(I/O)區的多個高壓側和低壓側二極體以及主齊納二極體與該高壓側和低壓側二極體並聯;第2B圖是說明根據常規器件結構的第2A圖所示的TVS陣列的器件實施方案的側截面圖。
第2C圖顯示說明如第2B圖實施的器件的潛在閉鎖的等效電路圖。
第3A圖到第3C圖分別是本發明的在具有深氧化物溝槽和半導體襯底上的厚矽的SOI層中形成的TVS的箝位二極體,低壓側/高壓側二極體和低壓側/高壓側二極體的側截面圖。
第3D圖和第3E圖分別是本發明的用橫向NPN和橫向NW NPN構造實現的第3A圖的TVS的側截面圖。
第4A圖到第4C圖分別是本發明的在具有薄矽部分耗盡的半導體襯底的SOI層中形成的TVS的箝位二極體,低壓側/高壓側二極體和低壓側/高壓側二極體的側截面圖。
第4D圖和第4E圖分別是本發明的用橫向NPN和橫向NW NPW構造實現的第4A圖的TVS的側截面圖。
第5A圖到第5C圖分別是本發明的在具有全部耗盡矽半導體襯底的SOI層中形成的TVS的箝位二極體,低壓側/高壓側二極體和低壓側/高壓側二極體的側截面圖。
第5D圖和第5E圖是本發明的用橫向NPN和橫向NW NPN構造實現的第5A圖到第5C圖的TVS的側截面圖。
105‧‧‧襯底
110‧‧‧BOX層
BOX‧‧‧厚體氧化物
120‧‧‧P-/P+襯底層
140、180‧‧‧N+陰極摻雜區
150、PAD‧‧‧二極體陰極金屬區
165‧‧‧P+陽極接觸區
160‧‧‧電極
170‧‧‧局部氧化矽(LOCOS)層
190、195‧‧‧N阱
PW‧‧‧P阱
Claims (12)
- 一種製造具有集成暫態電壓抑制器件的電子器件的方法,其特徵在於,該方法包括:通過在絕緣物上方形成作為絕緣物上矽層的矽層並且形成與高壓側和低壓側二極體一起發揮作用以箝制絕緣物上矽層中的所述電子器件的暫態電壓的箝制元件而在半導體襯底上製造暫態電壓抑制器件;所述形成絕緣物的工藝還包括在半導體襯底中形成厚體氧化物層的步驟,具體包括通過在P-晶片的頂表面上形成厚體氧化物層,然後將兩個晶片的氧化層面對面鍵合和熔融在一起,最後將襯底研磨成所需要厚度而在半導體襯底中形成厚體氧化物層。
- 如申請專利範圍第1項所述的方法,其特徵在於,該方法還包括:深摻雜注入半導體襯底以使厚體氧化物層上方的P-襯底層轉變為P+層。
- 如申請專利範圍第1項所述的方法,其特徵在於,所述厚體氧化物層具有250埃到1微米範圍內的厚度以承受所施加的高於25伏的擊穿電壓。
- 如申請專利範圍第1項所述的方法,其特徵在於,所述箝制元件由P阱進一步包圍。
- 如申請專利範圍第1項所述的方法,其特徵在於,所述箝制元件由所述絕緣層上方設置的P-/P+襯底層的頂部上的P阱進一步包圍。
- 如申請專利範圍第1項所述的方法,其特徵在於,所述箝制元件還包括齊納二極體。
- 如申請專利範圍第6項所述的方法,其特徵在於,所述齊納二極體還包括分級摻雜區域。
- 如申請專利範圍第1項所述的方法,其特徵在於,所述箝制元件還包括由二極體觸發的雙極型電晶體。
- 如申請專利範圍第8項所述的方法,其特徵在於,所述雙極電晶體還包括用於擴大基極區的延伸發射極區,通過提供更深的載流子注入增強高電流處理能力。
- 如申請專利範圍第1項所述的方法,其特徵在於,所述絕緣物還包括矽注入氧化薄層。
- 如申請專利範圍第1項所述的方法,其特徵在於,該暫態電壓抑制器件還包括:將箝制元件與其他功能器件隔離的重摻雜沉阱。
- 如申請專利範圍第1項所述的方法,其特徵在於,該暫態電壓抑制器件還包括:填充溝槽以將箝制元件與其他功能器件隔離的電介質材料。
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