US20160064573A1 - Semiconductor device including zener diode and method of manufacturing thereof - Google Patents
Semiconductor device including zener diode and method of manufacturing thereof Download PDFInfo
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- US20160064573A1 US20160064573A1 US14/473,365 US201414473365A US2016064573A1 US 20160064573 A1 US20160064573 A1 US 20160064573A1 US 201414473365 A US201414473365 A US 201414473365A US 2016064573 A1 US2016064573 A1 US 2016064573A1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- Zener diodes are widely used, in applications including rectifiers and voltage regulators, for protecting other semiconductor devices from suffering from an undesired pulse.
- a zener diode When a zener diode is reverse-biased, it has the ability to hold the voltage on a certain value, thereby having voltage-stabilizing characteristics.
- Zener diodes are also widely used trimming techniques, which are used to make adjustments to an integrated circuit after fabrication. Trimming techniques typically include laser trimming of thin-film resistors and “zener zap” anti-fuse trimming. Zener zap trimming has gained wide acceptance because it is field programmable and is less costly to implement.
- the zener zap method uses zener diodes having a low to moderate breakdown voltage as trim devices.
- a trim circuit includes a string of zener diodes and a string of corresponding resistive elements where each zener diode is connected in parallel to one of the resistive elements. Zener diodes are biased so that they behave as an open circuit as fabricated. When trimming is performed, the zener diode is zapped and the junction is short-circuited. By shorting out selective zener diodes and the associated resistive elements, a desired change in resistance can be obtained.
- FIGS. 1A-1G illustrate cross-sectional views of a semiconductor device containing a zener diode at various stages of the manufacturing process, in accordance with some embodiments.
- FIGS. 2A-D illustrate cross-sectional views of a semiconductor device at various stages of the manufacturing process, in accordance with some embodiments.
- FIG. 3 illustrate a cross-sectional view of a semiconductor device in accordance with some embodiments.
- An exemplary embodiment of the present disclosure provides a semiconductor device.
- the semiconductor device includes an insulator formed on a top surface of a semiconductor substrate.
- the semiconductor device also includes a semiconductor layer, which contains a first region of a first conductivity type and is formed on the insulator layer.
- the first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer.
- the semiconductor device further includes a second region of a second conductivity type in direct contact with the first region, forming a P-N junction with the first region.
- the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.
- An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor device.
- the method includes forming an insulator on a semiconductor substrate.
- the method also includes depositing a semiconductor layer over the insulator and the semiconductor substrate.
- the method further includes performing a first implantation process on the semiconductor layer to give it a first conductivity type.
- the method includes patterning the semiconductor layer such that the semiconductor layer is isolated with the semiconductor substrate by the insulator.
- the method further includes forming a photoresist layer over the semiconductor substrate, and the photoresist layer has an opening exposing a portion of the semiconductor layer.
- the method further includes performing a second implantation process on the exposed portion of the semiconductor layer, through the opening, to form a region of a second conductivity type in the semiconductor layer.
- An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor device.
- the method includes forming an insulator on a semiconductor substrate.
- the method also includes depositing a semiconductor layer over the insulator and the semiconductor substrate.
- the method further includes performing a first implantation process on the semiconductor layer to give it a first conductivity type.
- the method includes patterning the semiconductor layer such that the semiconductor layer is partially located on the insulator and has an extension portion in direct contact with the semiconductor layer.
- the method includes forming a photoresist layer over the semiconductor substrate.
- the photoresist layer has an opening exposing a portion of extension portion of the semiconductor layer and a portion of the semiconductor substrate.
- the method further includes performing a second implantation process on the semiconductor substrate, through the opening, to form a region of a second conductivity type in the semiconductor substrate. The region of the second conductivity type is partially covered by the semiconductor layer.
- first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes.
- additional processes may be performed between the first and second processes.
- Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity.
- formation of a first feature over or on a second feature in the description may include embodiments in which the first and second features are formed in direct or indirect contact.
- FIGS. 1A-1G illustrate cross-sectional views of a semiconductor device containing a zener diode at various stages of the manufacturing process, in accordance with some embodiments.
- the semiconductor device 100 includes a semiconductor substrate 102 .
- the semiconductor substrate 102 may be a silicon substrate doped with a P-type dopant such as boron, in which case the substrate 102 is a P-type substrate.
- the semiconductor substrate 102 could be another suitable semiconductor material.
- the semiconductor substrate 102 may be a silicon substrate doped with an N-type dopant such as phosphorous or arsenic, in which case the substrate is an N-type substrate.
- the semiconductor substrate 102 may include other elementary semiconductor materials such as germanium or diamond.
- the semiconductor substrate 102 may optionally include a compound substrate and/or an alloy semiconductor. Further, the semiconductor substrate 102 may include an epitaxial layer (epi layer), being strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure.
- epi layer epitaxial layer
- SOI silicon-on-insulator
- an insulator 104 is formed on a top surface of the semiconductor substrate 102 .
- the insulator 104 may have a first width W 1 ranging from about 1 ⁇ m to about 20 ⁇ m.
- the insulator 104 includes a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof.
- LOC local oxidation of silicon
- the insulator 104 may have a top surface that is higher than a top surface of the semiconductor substrate 102 .
- the insulator 104 includes silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, other suitable materials, or a combination thereof.
- the insulator 104 is formed by thermal-growing an oxide material through on the semiconductor substrate 102 .
- a semiconductor layer 106 is deposited over the insulator 104 .
- the semiconductor layer 106 includes silicon, either in polycrystalline or amorphous form.
- the semiconductor layer 106 includes GaN, GaAs or other suitable III-V semiconductor materials (i.e., comprising a combination of one or more group III elements with one or more group V elements).
- the III-V semiconductor materials are particularly suitable for high-power devices because they have better thermal conductivity and can sustain higher temperature than silicon can.
- the semiconductor layer 106 has a thickness of about 2000 angstroms to about 15000 angstroms.
- a first implantation process 108 is performed on the semiconductor layer 106 such that the semiconductor layer 106 has a first conductivity type, such as an N-type or a P-type.
- the semiconductor layer 106 may have a heavy doping concentration, such as in a range from about 5e13 atoms/cm 2 to about 5e15 atoms/cm 2 .
- the semiconductor layer 106 is entirely implanted without using a mask (e.g., photoresist).
- the first implantation process 108 uses an ion energy ranging from about 5 KeV to about 250 KeV.
- an N+ semiconductor layer 106 is shown in FIG. 1D although it may be also formed as a P+ semiconductor layer.
- the semiconductor layer 106 is patterned to a semiconductor layer 106 a that has a second width W 2 smaller than the first width W 1 of the insulator 104 .
- the second width W 2 may be in a range from about 1 ⁇ m to about 18 ⁇ m.
- the semiconductor layer 106 a is disposed on the insulator 104 and physically and electrically isolated with the semiconductor substrate 102 by the insulator 104 .
- a patterned photoresist layer 110 is formed over the semiconductor substrate 102 .
- the patterned photoresist layer 110 has an opening 112 exposing a portion of the semiconductor layer 106 a .
- the exposed portion of the semiconductor layer 106 is adjacent to a sidewall of the semiconductor layer 106 a .
- a second implantation process 114 is performed on the exposed portion of the semiconductor layer 106 through the opening 112 .
- the second implantation process 114 implants dopants of a second conductivity type into the exposed portion of the semiconductor layer 106 a .
- the second conductivity type is opposite to the first conductivity type.
- the second conductivity type is P-type when the first conductivity type is N-type, or vice versa.
- the patterned photoresist layer 110 may be removed after the second implantation process 114 is done.
- the semiconductor layer 106 a contains a first region 106 a 1 of the first conductivity type and a second region 106 a 2 of the second conductivity type.
- the second region 106 a 2 has a doping concentration lighter than that of the first region 106 a 1 .
- the second region 106 a 2 may have a doping concentration ranging from about 1e13 atoms/cm 2 to about 1e15 atoms/cm 2 .
- the first region 106 a 1 of the first conductivity type has a volume of over 50-80% of the volume of the semiconductor layer 106 a while the second region 106 a 2 occupies the remaining volume of the semiconductor layer 106 a .
- the second region 106 a 2 is partially or entirely surrounded by the first region 106 a 1 .
- the first and second regions 106 a 1 and 106 a 2 of the semiconductor layer 106 a are in direct contact with each other and form a P-N junction 107 .
- the first and second regions 106 a 1 and 106 a 2 of the semiconductor layer 106 a may function as a zener diode. This kind of device is used in trimming circuits and in particular a zener-like trimming device.
- the depth of the second region 106 a 2 of the semiconductor layer 106 a is substantially the same as or less than of the thickness of the semiconductor layer 106 a .
- a P region 106 a 2 is shown in FIG. 1F although it may be also formed as an N region.
- an inter-layer dielectric (ILD) layer 116 is formed over the semiconductor substrate 102 .
- a first metallization contact 118 and a second metallization contact 120 are formed through the ILD layer 116 to be in electrical contact with the first region 106 a 1 and the second region 106 a 2 of the semiconductor layer 106 a , respectively.
- the ILD layer 116 includes a low-k dielectric material, silicon oxide layer or a combination thereof.
- the low-k dielectric material has a dielectric constant less than about 3.0.
- low-k dielectric materials may be employed to form the low-k dielectric layer, including fluorinated silicon glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other future developed low-k dielectric materials.
- the ILD layer 116 is formed by chemical vapor deposition (CVD), spin-on coating or other suitable techniques.
- the first and second metallization contacts 118 and 120 are formed of a metal, which may be titanium, titanium nitride, tungsten, aluminum, tantalum, titanium nitride, or a combination thereof.
- the semiconductor device 100 containing a zener diode can be manufactured easily.
- the semiconductor layer 106 a includes only two regions 106 a 1 and 106 a 2 (e.g., the P regions and the N+ region as shown in FIG. 1G ).
- the semiconductor layer 106 a does not include a third region other than the first and second regions 106 a 1 and 106 a 2 . Accordingly, during the process of manufacturing the zener diode, only two implantation processes 108 and 114 are needed to be performed on the semiconductor layer 106 , and only one mask (e.g., the photoresist layer 110 ) is needed in these two implantation processes 108 and 114 .
- FIGS. 2A-D illustrate cross-sectional views of a semiconductor device at various stages of manufacturing processes, in accordance with some embodiments.
- a semiconductor device 200 similar to the semiconductor device 100 as shown in FIG. 1 D is provided, including the semiconductor substrate 102 , the insulator 104 and the semiconductor layer 106 of the first conductivity type.
- the insulator 104 has the first width W 1 .
- the semiconductor layer 106 is patterned to a semiconductor layer 106 b that has a third width W 3 which is greater than the first width W 1 of the insulator 104 .
- the third width W 3 of the semiconductor layer 106 b may be in a range from about 2 ⁇ m to about 25 ⁇ m. Accordingly, the semiconductor layer 106 b has an extension portion that extends over a sidewall of the insulator 104 and is in direct contact with the semiconductor substrate 102 .
- a patterned photoresist layer 210 which is formed over the semiconductor substrate 102 , has an opening 212 exposing at least a portion of the extension portion of the semiconductor layer 106 b and a portion of the semiconductor substrate 102 adjacent to the semiconductor layer 106 b .
- the opening 212 also exposes a sidewall of semiconductor layer 106 b.
- a second implantation process 214 is then performed on the semiconductor substrate 102 through the opening 212 .
- the second implantation process 214 implants dopants of the second conductivity type into the semiconductor substrate 102 .
- a region 202 2 of the second conductivity type is formed in the semiconductor substrate 102 , near the top surface of the semiconductor substrate 102 .
- the second region 202 2 is partially covered by (i.e., under) the semiconductor layer 106 b .
- the second region 202 2 has a doping concentration heavier than that of the semiconductor layer 106 b .
- the region 202 2 may have a doping concentration ranging from about 5e13 atoms/cm 2 to about 8e15 atoms/cm 2 .
- the second implantation process 214 uses an ion energy ranging from about 5 KeV to about 200 KeV, such that the dopants may penetrate the semiconductor layer 106 b to reach the semiconductor substrate 102 and forms the second region 202 2 near the top surface of the semiconductor substrate 102 .
- An annealing process may be performed after the second implantation process.
- the patterned photoresist layer 210 may be removed after the second implantation process 214 is done.
- the semiconductor layer 106 b and the region 202 2 may form a P-N junction 207 and function as a zener diode.
- a P++ region 202 2 is shown in FIG. 2C although it may be also formed as an N++ region.
- the inter-layer dielectric (ILD) layer 116 is formed over the semiconductor substrate 102 and the patterned semiconductor layer 106 b .
- the first metallization contact 118 is formed through the ILD layer 116 to be in electrical contact with the semiconductor layer 106 b .
- a second metallization contact 220 is formed through the ILD layer 116 to in electrical contact a portion of the second region 202 2 that is not covered by the semiconductor layer 106 b .
- the second metallization contact 220 does not penetrate the semiconductor layer 106 b but has a horizontal gap G between itself and the semiconductor layer 106 b .
- the horizontal gap G may be in a range from 0.5 ⁇ m to about 7 ⁇ m.
- the semiconductor device 200 containing a zener diode can be easily manufactured. For example, during the processes of manufacturing the zener diode, only two implantation processes 108 and 214 are needed to be performed on the semiconductor layer 106 b , and only one mask (e.g., the patterned photoresist layer 210 ) is needed in these two implantation processes 108 and 214 .
- FIG. 3 illustrate a cross-sectional view of a semiconductor device in accordance with some embodiments.
- a semiconductor device 300 that is similar to the semiconductor device 100 , except that the insulator 304 is an STI structure, is provided.
- the formation of the isolation structure 304 includes patterning the semiconductor substrate 100 by a photolithography process, etching a recess, such as a trench, in the semiconductor substrate 102 (for example, by using a dry etching, wet etching, other applicable etching processes, or a combination thereof), and filling the recess (for example, by using chemical vapor deposition).
- the insulator 304 may have the first width W 1 .
- the insulator 304 may have a top surface level with that of the semiconductor substrate 102 .
- the semiconductor substrate 102 may provide a flat surface for forming the semiconductor layer 306 a on it.
- the semiconductor layer 306 a may be made of the same material and by the same formation method as the semiconductor layer 106 a described above.
- the semiconductor layer 306 a may have the second width W 2 while the second region 306 a 2 is located in the semiconductor layer, although the semiconductor layer 306 a may have the third width W 3 while the second region is a position like the second region 202 2 as shown in FIG. 2D (in the semiconductor substrate).
- the first region 306 a 1 and the second region 306 a 2 form a P-N junction 307 therebetween and may function as a zener diode.
Abstract
An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.
Description
- Zener diodes are widely used, in applications including rectifiers and voltage regulators, for protecting other semiconductor devices from suffering from an undesired pulse. When a zener diode is reverse-biased, it has the ability to hold the voltage on a certain value, thereby having voltage-stabilizing characteristics.
- Zener diodes are also widely used trimming techniques, which are used to make adjustments to an integrated circuit after fabrication. Trimming techniques typically include laser trimming of thin-film resistors and “zener zap” anti-fuse trimming. Zener zap trimming has gained wide acceptance because it is field programmable and is less costly to implement. The zener zap method uses zener diodes having a low to moderate breakdown voltage as trim devices. Typically, a trim circuit includes a string of zener diodes and a string of corresponding resistive elements where each zener diode is connected in parallel to one of the resistive elements. Zener diodes are biased so that they behave as an open circuit as fabricated. When trimming is performed, the zener diode is zapped and the junction is short-circuited. By shorting out selective zener diodes and the associated resistive elements, a desired change in resistance can be obtained.
- For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.
-
FIGS. 1A-1G illustrate cross-sectional views of a semiconductor device containing a zener diode at various stages of the manufacturing process, in accordance with some embodiments. -
FIGS. 2A-D illustrate cross-sectional views of a semiconductor device at various stages of the manufacturing process, in accordance with some embodiments. -
FIG. 3 illustrate a cross-sectional view of a semiconductor device in accordance with some embodiments. - An exemplary embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer, which contains a first region of a first conductivity type and is formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region, forming a P-N junction with the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.
- An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes forming an insulator on a semiconductor substrate. The method also includes depositing a semiconductor layer over the insulator and the semiconductor substrate. The method further includes performing a first implantation process on the semiconductor layer to give it a first conductivity type. In addition, the method includes patterning the semiconductor layer such that the semiconductor layer is isolated with the semiconductor substrate by the insulator. The method further includes forming a photoresist layer over the semiconductor substrate, and the photoresist layer has an opening exposing a portion of the semiconductor layer. The method further includes performing a second implantation process on the exposed portion of the semiconductor layer, through the opening, to form a region of a second conductivity type in the semiconductor layer.
- An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes forming an insulator on a semiconductor substrate. The method also includes depositing a semiconductor layer over the insulator and the semiconductor substrate. The method further includes performing a first implantation process on the semiconductor layer to give it a first conductivity type. In addition, the method includes patterning the semiconductor layer such that the semiconductor layer is partially located on the insulator and has an extension portion in direct contact with the semiconductor layer. The method includes forming a photoresist layer over the semiconductor substrate. The photoresist layer has an opening exposing a portion of extension portion of the semiconductor layer and a portion of the semiconductor substrate. The method further includes performing a second implantation process on the semiconductor substrate, through the opening, to form a region of a second conductivity type in the semiconductor substrate. The region of the second conductivity type is partially covered by the semiconductor layer.
- The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
- It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description may include embodiments in which the first and second features are formed in direct or indirect contact.
- Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is understood that additional steps can be provided before, during, and after the method, and some of the steps described can be replaced or eliminated for other embodiments of the method.
-
FIGS. 1A-1G illustrate cross-sectional views of a semiconductor device containing a zener diode at various stages of the manufacturing process, in accordance with some embodiments. Referring toFIG. 1A , thesemiconductor device 100 includes asemiconductor substrate 102. Thesemiconductor substrate 102 may be a silicon substrate doped with a P-type dopant such as boron, in which case thesubstrate 102 is a P-type substrate. Alternatively, thesemiconductor substrate 102 could be another suitable semiconductor material. For example, thesemiconductor substrate 102 may be a silicon substrate doped with an N-type dopant such as phosphorous or arsenic, in which case the substrate is an N-type substrate. Thesemiconductor substrate 102 may include other elementary semiconductor materials such as germanium or diamond. Thesemiconductor substrate 102 may optionally include a compound substrate and/or an alloy semiconductor. Further, thesemiconductor substrate 102 may include an epitaxial layer (epi layer), being strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure. - Referring to
FIG. 1B , aninsulator 104 is formed on a top surface of thesemiconductor substrate 102. Theinsulator 104 may have a first width W1 ranging from about 1 μm to about 20 μm. In some embodiments, theinsulator 104 includes a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof. Theinsulator 104 may have a top surface that is higher than a top surface of thesemiconductor substrate 102. In some embodiments, theinsulator 104 includes silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, other suitable materials, or a combination thereof. In some embodiments, theinsulator 104 is formed by thermal-growing an oxide material through on thesemiconductor substrate 102. - Referring to
FIG. 1C , asemiconductor layer 106 is deposited over theinsulator 104. In some embodiments, thesemiconductor layer 106 includes silicon, either in polycrystalline or amorphous form. In alternative embodiments, thesemiconductor layer 106 includes GaN, GaAs or other suitable III-V semiconductor materials (i.e., comprising a combination of one or more group III elements with one or more group V elements). The III-V semiconductor materials are particularly suitable for high-power devices because they have better thermal conductivity and can sustain higher temperature than silicon can. In some embodiments, thesemiconductor layer 106 has a thickness of about 2000 angstroms to about 15000 angstroms. - Referring to
FIG. 1D , afirst implantation process 108 is performed on thesemiconductor layer 106 such that thesemiconductor layer 106 has a first conductivity type, such as an N-type or a P-type. After performing thefirst implantation process 108, thesemiconductor layer 106 may have a heavy doping concentration, such as in a range from about 5e13 atoms/cm2 to about 5e15 atoms/cm2. In some embodiments, in thefirst implantation process 108, thesemiconductor layer 106 is entirely implanted without using a mask (e.g., photoresist). In some embodiments, thefirst implantation process 108 uses an ion energy ranging from about 5 KeV to about 250 KeV. For the sake of illustration, anN+ semiconductor layer 106 is shown inFIG. 1D although it may be also formed as a P+ semiconductor layer. - Afterwards, referring to
FIG. 1E , thesemiconductor layer 106 is patterned to asemiconductor layer 106 a that has a second width W2 smaller than the first width W1 of theinsulator 104. The second width W2 may be in a range from about 1 μm to about 18 μm. In some embodiments, thesemiconductor layer 106 a is disposed on theinsulator 104 and physically and electrically isolated with thesemiconductor substrate 102 by theinsulator 104. - Afterwards, referring to
FIG. 1F , a patternedphotoresist layer 110 is formed over thesemiconductor substrate 102. The patternedphotoresist layer 110 has anopening 112 exposing a portion of thesemiconductor layer 106 a. The exposed portion of thesemiconductor layer 106 is adjacent to a sidewall of thesemiconductor layer 106 a. Asecond implantation process 114 is performed on the exposed portion of thesemiconductor layer 106 through theopening 112. Thesecond implantation process 114 implants dopants of a second conductivity type into the exposed portion of thesemiconductor layer 106 a. The second conductivity type is opposite to the first conductivity type. For example, the second conductivity type is P-type when the first conductivity type is N-type, or vice versa. The patternedphotoresist layer 110 may be removed after thesecond implantation process 114 is done. - After performing the
second implantation process 114, thesemiconductor layer 106 a contains afirst region 106 a 1 of the first conductivity type and asecond region 106 a 2 of the second conductivity type. In some embodiments, thesecond region 106 a 2 has a doping concentration lighter than that of thefirst region 106 a 1. For example, thesecond region 106 a 2 may have a doping concentration ranging from about 1e13 atoms/cm2 to about 1e15 atoms/cm2. In some embodiments, thefirst region 106 a 1 of the first conductivity type has a volume of over 50-80% of the volume of thesemiconductor layer 106 a while thesecond region 106 a 2 occupies the remaining volume of thesemiconductor layer 106 a. Thesecond region 106 a 2 is partially or entirely surrounded by thefirst region 106 a 1. The first andsecond regions semiconductor layer 106 a are in direct contact with each other and form aP-N junction 107. The first andsecond regions semiconductor layer 106 a may function as a zener diode. This kind of device is used in trimming circuits and in particular a zener-like trimming device. In some embodiments, the depth of thesecond region 106 a 2 of thesemiconductor layer 106 a is substantially the same as or less than of the thickness of thesemiconductor layer 106 a. For the sake of illustration, aP region 106 a 2 is shown inFIG. 1F although it may be also formed as an N region. - Afterwards, referring to
FIG. 1G , an inter-layer dielectric (ILD)layer 116 is formed over thesemiconductor substrate 102. Afirst metallization contact 118 and asecond metallization contact 120 are formed through theILD layer 116 to be in electrical contact with thefirst region 106 a 1 and thesecond region 106 a 2 of thesemiconductor layer 106 a, respectively. In some embodiments, theILD layer 116 includes a low-k dielectric material, silicon oxide layer or a combination thereof. The low-k dielectric material has a dielectric constant less than about 3.0. A wide variety of low-k dielectric materials may be employed to form the low-k dielectric layer, including fluorinated silicon glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other future developed low-k dielectric materials. In some embodiments, theILD layer 116 is formed by chemical vapor deposition (CVD), spin-on coating or other suitable techniques. In some embodiments, the first andsecond metallization contacts - The
semiconductor device 100 containing a zener diode can be manufactured easily. For example, thesemiconductor layer 106 a includes only tworegions 106 a 1 and 106 a 2 (e.g., the P regions and the N+ region as shown inFIG. 1G ). Thesemiconductor layer 106 a does not include a third region other than the first andsecond regions implantation processes semiconductor layer 106, and only one mask (e.g., the photoresist layer 110) is needed in these twoimplantation processes -
FIGS. 2A-D illustrate cross-sectional views of a semiconductor device at various stages of manufacturing processes, in accordance with some embodiments. Referring toFIG. 2A , a semiconductor device 200 similar to thesemiconductor device 100 as shown inFIG. 1 D is provided, including thesemiconductor substrate 102, theinsulator 104 and thesemiconductor layer 106 of the first conductivity type. In some embodiments, theinsulator 104 has the first width W1. - Afterwards, referring to
FIG. 2B , thesemiconductor layer 106 is patterned to asemiconductor layer 106 b that has a third width W3 which is greater than the first width W1 of theinsulator 104. The third width W3 of thesemiconductor layer 106 b may be in a range from about 2 μm to about 25 μm. Accordingly, thesemiconductor layer 106 b has an extension portion that extends over a sidewall of theinsulator 104 and is in direct contact with thesemiconductor substrate 102. - Afterwards, referring to
FIG. 2C , a patternedphotoresist layer 210, which is formed over thesemiconductor substrate 102, has anopening 212 exposing at least a portion of the extension portion of thesemiconductor layer 106 b and a portion of thesemiconductor substrate 102 adjacent to thesemiconductor layer 106 b. In some embodiments, theopening 212 also exposes a sidewall ofsemiconductor layer 106 b. - A
second implantation process 214 is then performed on thesemiconductor substrate 102 through theopening 212. Thesecond implantation process 214 implants dopants of the second conductivity type into thesemiconductor substrate 102. A region 202 2 of the second conductivity type is formed in thesemiconductor substrate 102, near the top surface of thesemiconductor substrate 102. The second region 202 2 is partially covered by (i.e., under) thesemiconductor layer 106 b. In some embodiments, the second region 202 2 has a doping concentration heavier than that of thesemiconductor layer 106 b. For example, the region 202 2 may have a doping concentration ranging from about 5e13 atoms/cm2 to about 8e15 atoms/cm2. In some embodiments, thesecond implantation process 214 uses an ion energy ranging from about 5 KeV to about 200 KeV, such that the dopants may penetrate thesemiconductor layer 106 b to reach thesemiconductor substrate 102 and forms the second region 202 2 near the top surface of thesemiconductor substrate 102. An annealing process may be performed after the second implantation process. The patternedphotoresist layer 210 may be removed after thesecond implantation process 214 is done. Thesemiconductor layer 106 b and the region 202 2 may form aP-N junction 207 and function as a zener diode. For the sake of illustration, a P++ region 202 2 is shown inFIG. 2C although it may be also formed as an N++ region. - Afterwards, referring to
FIG. 2D , the inter-layer dielectric (ILD)layer 116 is formed over thesemiconductor substrate 102 and the patternedsemiconductor layer 106 b. Thefirst metallization contact 118 is formed through theILD layer 116 to be in electrical contact with thesemiconductor layer 106 b. Asecond metallization contact 220 is formed through theILD layer 116 to in electrical contact a portion of the second region 202 2 that is not covered by thesemiconductor layer 106 b. Thesecond metallization contact 220 does not penetrate thesemiconductor layer 106 b but has a horizontal gap G between itself and thesemiconductor layer 106 b. The horizontal gap G may be in a range from 0.5 μm to about 7 μm. - The semiconductor device 200 containing a zener diode can be easily manufactured. For example, during the processes of manufacturing the zener diode, only two
implantation processes semiconductor layer 106 b, and only one mask (e.g., the patterned photoresist layer 210) is needed in these twoimplantation processes -
FIG. 3 illustrate a cross-sectional view of a semiconductor device in accordance with some embodiments. A semiconductor device 300 that is similar to thesemiconductor device 100, except that theinsulator 304 is an STI structure, is provided. The formation of theisolation structure 304 includes patterning thesemiconductor substrate 100 by a photolithography process, etching a recess, such as a trench, in the semiconductor substrate 102 (for example, by using a dry etching, wet etching, other applicable etching processes, or a combination thereof), and filling the recess (for example, by using chemical vapor deposition). - The
insulator 304 may have the first width W1. Theinsulator 304 may have a top surface level with that of thesemiconductor substrate 102. Thesemiconductor substrate 102 may provide a flat surface for forming thesemiconductor layer 306 a on it. Thesemiconductor layer 306 a may be made of the same material and by the same formation method as thesemiconductor layer 106 a described above. Thesemiconductor layer 306 a may have the second width W2 while thesecond region 306 a 2 is located in the semiconductor layer, although thesemiconductor layer 306 a may have the third width W3 while the second region is a position like the second region 202 2 as shown inFIG. 2D (in the semiconductor substrate). Thefirst region 306 a 1 and thesecond region 306 a 2 form aP-N junction 307 therebetween and may function as a zener diode. - Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or layer to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims (20)
1. A semiconductor device, comprising:
an insulator formed on a top surface of a semiconductor substrate;
a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region and has a volume of over 50-80% of the volume of the semiconductor layer;
a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region;
a first metallization region in electrical contact with the first region; and
a second metallization region in electrical contact with the second region.
2. The semiconductor device as claimed in claim 1 , wherein the second region is formed in the semiconductor layer and is surrounded by the first region.
3. The semiconductor device as claimed in claim 2 , wherein the semiconductor layer does not include a third region other than the first region and the second region.
4. The semiconductor device as claimed in claim 2 , wherein the semiconductor layer is electrically and physically isolated with the semiconductor substrate by the insulator.
5. The semiconductor device as claimed in claim 1 , wherein the second region is the semiconductor substrate and partially covered by the semiconductor layer.
6. The semiconductor device as claimed in claim 5 , wherein semiconductor layer has an extension portion extending over a sidewall of the insulator and in direct contact with the semiconductor substrate.
7. The semiconductor device as claimed in claim 5 , wherein second metallization contact is physical contact with a portion of the second region that is not covered by the semiconductor layer.
8. The semiconductor device as claimed in claim 7 , wherein the second metallization contact has a horizontal gap with the semiconductor layer.
9. The semiconductor device as claimed in claim 1 , wherein the semiconductor layer comprises silicon.
10. The semiconductor device as claimed in claim 1 , wherein the semiconductor layer comprises GaN, GaAs or other III-V semiconductor materials.
11. The semiconductor device as claimed in claim 1 , wherein the insulator comprises a local oxidation of silicon structure.
12. The semiconductor device as claimed in claim 1 , wherein the insulator comprises a shallow trench isolation structure.
13. A method for manufacturing a semiconductor device, comprising:
forming an insulator on a semiconductor substrate;
depositing a semiconductor layer over the insulator and the semiconductor substrate;
performing a first implantation process on the semiconductor layer to give it a first conductivity type;
patterning the semiconductor layer such that the semiconductor layer is isolated with the semiconductor substrate by the insulator;
forming a photoresist layer over the semiconductor substrate, wherein the photoresist layer has an opening exposing a portion of the semiconductor layer; and
performing a second implantation process on the exposed portion of the semiconductor layer, through the opening, to form a region of a second conductivity type in the semiconductor layer.
14. The method as claimed in claim 13 , further comprising:
removing the photoresist layer after performing the second implantation process;
forming an inter-layer dielectric layer over the semiconductor substrate;
forming a first metallization contact and a second metallization contact in electrical contact with the remaining region of the semiconductor layer that has the first conductivity type and the region of the second conductivity type, respectively.
15. The method as claimed in claim 13 , wherein the semiconductor layer is entirely implanted without using a mask in the first implantation process.
16. A method for manufacturing a semiconductor device, comprising:
forming an insulator on a semiconductor substrate;
depositing a semiconductor layer over the insulator and the semiconductor substrate;
performing a first implantation process on the semiconductor layer to give it a first conductivity type;
patterning the semiconductor layer such that the semiconductor layer is partially located on the insulator and has an extension portion in direct contact with the semiconductor substrate;
forming a photoresist layer over the semiconductor substrate, wherein the photoresist layer has an opening exposing a portion of extension portion of the semiconductor layer and a portion of the semiconductor substrate; and
performing a second implantation process on the semiconductor substrate, through the opening, to form a region of a second conductivity type in the semiconductor substrate, wherein the region of the second conductivity type is partially covered by the semiconductor layer.
17. The method as claimed in claim 16 , further comprising:
removing the photoresist layer after performing the second implantation process;
forming an inter-layer dielectric layer over the semiconductor substrate and the semiconductor layer;
forming a first metallization contact and a second metallization contact in electrical contact with the semiconductor layer of the first conductivity type and the region of the second conductivity type, respectively.
18. The method as claimed in claim 16 , wherein the second implantation process uses an ion energy ranging from about 5 KeV to about 250 KeV.
19. The method as claimed in claim 16 , wherein the semiconductor layer is entirely implanted without using a mask in the first implantation process.
20. The method as claimed in claim 16 , wherein the opening of the photoresist layer comprises exposing a sidewall of the semiconductor layer.
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WO2023241772A1 (en) * | 2022-06-13 | 2023-12-21 | Huawei Digital Power Technologies Co., Ltd. | Semiconductor device and method |
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US5913122A (en) * | 1997-01-27 | 1999-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making high breakdown voltage twin well device with source/drain regions widely spaced from FOX regions |
JP3608456B2 (en) | 1999-12-08 | 2005-01-12 | セイコーエプソン株式会社 | Manufacturing method of SOI structure MIS field effect transistor |
JP2002141507A (en) | 2000-10-31 | 2002-05-17 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
US6815797B1 (en) * | 2002-01-08 | 2004-11-09 | National Semiconductor Corporation | Silicide bridged anti-fuse |
US7453107B1 (en) | 2007-05-04 | 2008-11-18 | Dsm Solutions, Inc. | Method for applying a stress layer to a semiconductor device and device formed therefrom |
US20090115018A1 (en) | 2007-11-01 | 2009-05-07 | Alpha & Omega Semiconductor, Ltd | Transient voltage suppressor manufactured in silicon on oxide (SOI) layer |
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US6621138B1 (en) * | 2002-10-21 | 2003-09-16 | Micrel, Inc. | Zener-like trim device in polysilicon |
US20140070344A1 (en) * | 2012-09-08 | 2014-03-13 | The Regents Of The University Of California | Systems and methods for implementing magnetoelectric junctions |
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Owner name: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SULISTYANTO, PRIYONO TRI;KUMAR, MANOJ;LEE, CHIA-HAO;AND OTHERS;SIGNING DATES FROM 20140411 TO 20140423;REEL/FRAME:033647/0315 |
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STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |