CN114551238A - Method for manufacturing burner integrated in semiconductor structure - Google Patents
Method for manufacturing burner integrated in semiconductor structure Download PDFInfo
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- CN114551238A CN114551238A CN202210454789.2A CN202210454789A CN114551238A CN 114551238 A CN114551238 A CN 114551238A CN 202210454789 A CN202210454789 A CN 202210454789A CN 114551238 A CN114551238 A CN 114551238A
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 14
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- 239000002184 metal Substances 0.000 abstract description 26
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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Abstract
The invention provides a method for manufacturing a burner integrated in a semiconductor structure. Specifically, a substrate layer used for forming a PN junction of the zener diode in the subsequent step is formed on the surface of the semiconductor substrate corresponding to the shallow trench isolation structure with the isolation function by depending on the process conditions of the existing CMOS platform, then the substrate layer is subjected to ion implantation twice to form the PN junction of the zener diode in the substrate layer, and then the zener diode is used as the burner integrated in the semiconductor structure provided by the invention. The structure of the burner is the Zener diode which has the characteristic of permanent unrecoverable, so the burner formed by the invention can avoid the problem that in the prior art, a metal fuse wire needs to be windowed on the surface of a chip during burning to ensure the purpose of one-time data reading and writing of the burner, and further needs an additional process.
Description
Technical Field
The invention relates to the technical field of programming, in particular to a manufacturing method of a programmer integrated in a semiconductor structure.
Background
A burner is a device capable of recording burning information, which can record information to be written and read it. There are many types of conventional Fuse programming devices, and at present, there are two types of Metal fuses (Metal fuses) and polysilicon fuses (Poly fuses) mainly on the market. Specifically, the principle of using a Metal Fuse (Metal Fuse) and a polysilicon Fuse (Poly Fuse) as a burner is to use an electromigration technique to break a Metal layer in the Metal Fuse (Metal Fuse) and a polysilicon layer in the polysilicon Fuse (Poly Fuse) so as to achieve the purpose of changing the resistance of the burner.
However, in practical applications, in order to ensure that a large current for burning the Metal Fuse (Metal Fuse) and the polysilicon Fuse (Poly Fuse) serving as the burner is satisfied, a chip area of the Metal Fuse (Metal Fuse) and the polysilicon Fuse (Poly Fuse) needs to be designed to be large, which results in that the Metal Fuse (Metal Fuse) and the polysilicon Fuse (Poly Fuse) serving as the burner cannot satisfy design requirements of gradual integration and small size of a semiconductor process. In addition, Metal fuses (Metal fuses) and polysilicon fuses (Poly fuses) have a large back growth phenomenon, and Metal fuses (Metal fuses) need to be windowed on the surface of a chip during burning in order to ensure the purpose of one-time data reading and writing of a burner.
Disclosure of Invention
The invention aims to provide a method for manufacturing a burner integrated in a semiconductor structure, which aims to provide a novel burner which can solve the problems of large chip area and high current demand of the traditional burner to the greatest extent without adjusting any parameter on the basis of the existing CMOS process platform, thereby finally realizing the purposes of maximally reducing the user cost and enhancing the product reliability.
In a first aspect, to solve the above technical problem, the present invention provides a method for manufacturing a burner integrated in a semiconductor structure, including:
providing a semiconductor substrate, wherein a shallow trench isolation structure and a semiconductor device area defined by the shallow trench isolation structure are formed in the semiconductor substrate.
And forming a substrate layer of the burner on the surface of the semiconductor substrate corresponding to the shallow trench isolation structure.
And carrying out an ion implantation process on the substrate layer of the burner so as to form a first doped region and a second doped region which are different in doping type in the substrate layer of the burner, wherein the first doped region and the second doped region are exposed on the surface of the substrate layer of the burner, the first doped region and the second doped region are transversely arranged and are connected with each other, so that the connected region of the first doped region and the second doped region forms a PN junction serving as a Zener diode of the burner.
Further, the material of the substrate layer of the burner can comprise polysilicon.
Further, the doping ions of the first doping region may be N-type ions, and the doping ions of the second doping region may be P-type ions.
Further, the step of forming the first doped region and the second doped region may include:
and forming a first photoresist layer for shielding half of the surface of the substrate layer of the burner on the surface of the substrate layer of the burner, and carrying out N-type or P-type ion implantation on the other half of the exposed surface of the substrate layer of the burner by taking the first photoresist layer as a mask to form a first doped region.
And forming a second photoresist layer on the surface of the substrate layer of the burner, which is exposed after the first photoresist layer is removed, by shielding the surface of the substrate layer of the burner, and performing P-type or N-type ion implantation on the other half surface of the exposed substrate layer of the burner by taking the second photoresist layer as a mask to form a second doped region.
Further, at least one MOS transistor may be formed in the semiconductor device region.
In a second aspect, based on the same inventive concept, the invention further provides a burner, wherein the burner can be prepared by the above method for manufacturing a burner integrated in a semiconductor structure.
In a third aspect, based on the same inventive concept, the present invention further provides a burning system of a burner, and specifically, the burning system of a burner provided by the present invention may include a burner manufactured by the above-mentioned method for manufacturing a burner integrated in a semiconductor structure.
In a third aspect, based on the same inventive concept as the method for manufacturing the burner integrated in the semiconductor structure provided by the present invention, the present invention further provides a layout structure of the burner, and the specific layout structure may include:
a first doped region.
The second doping area is transversely arranged with the first doping area and is connected with the first doping area.
And the PN junction area is arranged in the connection area of the first doped area and the second doped area, and part of width is respectively delayed towards the first doped area and the second doped area, so that the PN junction of the Zener diode formed by the connection area of the first doped area and the second doped area is used as a burner.
Further, the first doped region and the second doped region may be a polysilicon layer doped with N-type ions or P-type ions.
Further, the layout structure of the burner provided by the present invention may further include:
a metal normalizer pattern overlying the PN junction region surface.
A plurality of metal patterns, one of the metal patterns is overlapped on the surface of the first doping region, and the other of the metal patterns is overlapped on the surface of the second doping region, so that the metal patterns and the metal regular patterns are arranged at intervals in a transverse direction without connection.
A plurality of contact patterns, at least two of which are disposed on a surface of each of the metal patterns.
Further, the contact pattern may be a metal plug layer.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
according to the manufacturing method of the burner integrated in the semiconductor structure, provided by the invention, a substrate layer used for forming a PN junction of a Zener diode in the subsequent step is formed on the surface of a semiconductor substrate corresponding to a shallow trench isolation structure with an isolation effect by depending on the process conditions of the existing CMOS platform, then the substrate layer is subjected to ion implantation twice to form the PN junction of the Zener diode in the substrate layer, and then the Zener diode is used as the burner integrated in the semiconductor structure provided by the invention. The structure of the burner is the Zener diode which has the characteristic of being not recoverable (once read-write operation), so the burner formed by the invention can avoid the problem that in the prior art, a Metal Fuse (Metal Fuse) needs to be windowed on the surface of a chip during burning to ensure the purpose of once data read-write of the burner, and further needs an additional process.
In addition, the width of the PN junction of the Zener diode can be very narrow according to actual requirements, so that the Zener diode can be used as a burner to ensure the use reliability of a chip product and reduce the area and the manufacturing cost of the chip, thereby better meeting the design requirements of gradual integration and small size of a semiconductor process.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a burner integrated in a semiconductor structure according to an embodiment of the present invention.
Fig. 2 is a schematic device structure diagram of a burner formed by the method for manufacturing the burner integrated in the semiconductor structure shown in fig. 1 according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a layout structure of a burner provided in an embodiment of the present invention.
Detailed Description
As described in the background art, in practical applications, in order to ensure that a large burning current of a Metal Fuse (Metal Fuse) and a polysilicon Fuse (Poly Fuse) serving as a burner is satisfied, a chip area of the Metal Fuse (Metal Fuse) and the polysilicon Fuse (Poly Fuse) needs to be designed to be large, which results in that the Metal Fuse (Metal Fuse) and the polysilicon Fuse (Poly Fuse) serving as the burner cannot meet design requirements of gradual integration and small size of a semiconductor process. In addition, Metal fuses (Metal fuses) and polysilicon fuses (Poly fuses) have a large back growth phenomenon, and Metal fuses (Metal fuses) need to be windowed on the surface of a chip during burning in order to ensure the purpose of one-time data reading and writing of a burner.
Therefore, the invention provides a manufacturing method of a burner integrated in a semiconductor structure and a layout structure thereof, and provides a novel burner which can solve the problems of large chip area and high current demand of the traditional burner to the greatest extent without adjusting any parameter on the basis of the existing CMOS process platform, thereby finally realizing the purposes of maximally reducing the user cost and enhancing the product reliability.
The following describes the method for manufacturing a burner integrated in a semiconductor structure and the layout structure thereof in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
The method for manufacturing the burner integrated in the semiconductor structure according to the present invention will be described first. Referring to fig. 1 in conjunction with fig. 2, fig. 1 is a schematic flow chart illustrating a method for manufacturing a burner integrated in a semiconductor structure according to the present invention; fig. 2 is a schematic device structure diagram of a burner formed by the method for manufacturing the burner integrated in the semiconductor structure shown in fig. 1 according to an embodiment of the present invention. Specifically, the method for manufacturing the burner integrated in the semiconductor structure may include the following steps:
step S100, providing a semiconductor substrate 100, wherein a shallow trench isolation structure 101 and a semiconductor device region M defined by the shallow trench isolation structure 101 are formed in the semiconductor substrate 100.
In this embodiment, an invention idea of using a zener diode as a burner is provided, and according to practical application of the burner, the burner is usually disposed in each unit of the memory as a redundant circuit of the memory, so that when the memory is damaged, the damaged memory is temporarily replaced as the memory to perform data read/write operation only once. Therefore, in the embodiment of the present invention, the zener diode as the burner is integrated into the semiconductor structure formed by the CMOS process, wherein the semiconductor structure may be any memory existing in the prior art, and the present invention is not limited in particular. For convenience of understanding and simplification of the drawings, the present invention will take the semiconductor structure as a MOS transistor as an example to show how to form the zener diode as a burner proposed by the present invention on an existing CMOS process platform, for example, as shown in fig. 2, a MOS transistor having a source S, a drain D and a gate S in a semiconductor device region M.
Step S200, forming a substrate layer 110 of a burner on the surface of the semiconductor substrate 100 corresponding to the shallow trench isolation structure 101.
In this embodiment, the substrate layer 110 of the burner may be made of a polysilicon material or a polysilicon material with a certain doping concentration, wherein N-type or P-type ion implantation is performed on the polysilicon layer according to actual requirements.
Step 300, performing an ion implantation process on the substrate layer 110 of the burner to form a first doped region a and a second doped region B with different doping types in the substrate layer 110 of the burner, wherein the first doped region a and the second doped region B are exposed on the surface of the substrate layer 110 of the burner, the first doped region a and the second doped region B are transversely arranged and are connected with each other, so that a connecting region AB of the first doped region a and the second doped region B forms a PN junction of a zener diode serving as the burner.
The doping ions of the first doping region a may be N-type ions, and the doping ions of the second doping region B may be P-type ions.
In this embodiment, a first photoresist layer (not shown) for shielding half of the surface of the substrate layer 110 of the burner may be formed on the surface of the substrate layer 110 of the burner, and N-type or P-type ion implantation is performed on the exposed other half surface of the substrate layer 110 of the burner by using the first photoresist layer as a mask to form a first doped region a; then, a second photoresist layer (not shown) is formed on the surface of the substrate layer 110 of the burner to shield the surface of the substrate layer of the burner exposed after the first photoresist layer is removed, and P-type or N-type ion implantation is performed on the other half surface of the substrate layer of the burner exposed by using the second photoresist layer as a mask to form a second doped region B.
The structure of the burner is the Zener diode which has the characteristic of being not recoverable (once read-write operation), so the burner formed by the invention can avoid the problem that in the prior art, a Metal Fuse (Metal Fuse) needs to be windowed on the surface of a chip during burning to ensure the purpose of once data read-write of the burner, and further needs an additional process. In addition, the width of the PN junction of the Zener diode can be very narrow according to actual requirements, so that the Zener diode can be used as a burner to ensure the use reliability of a chip product and reduce the area and the manufacturing cost of the chip, thereby better meeting the design requirements of gradual integration and small size of a semiconductor process.
In addition, based on the same inventive concept as the above-mentioned method for manufacturing the burner integrated in the semiconductor structure, that is, using the zener diode (using the zener breakdown property of the zener diode) which has no permanent recovery and no extra process requirement, the reliability of the chip product in use can be ensured, the present invention also provides a burner, wherein the burner provided by the present invention can be specifically manufactured by using the method for manufacturing the burner integrated in the semiconductor structure as shown in fig. 1, and the description thereof is omitted.
Similarly, based on the same inventive concept as the above-mentioned method for manufacturing the burner integrated in the semiconductor structure, the present invention further provides a burner system, which specifically includes a burner manufactured by the method for manufacturing the burner integrated in the semiconductor structure as shown in fig. 1, and the description thereof is omitted here.
Further, as shown in fig. 3, fig. 3 is a schematic structural diagram of a layout structure of a burner provided in an embodiment of the present invention, and the present invention further provides a layout structure of a burner, which may specifically include:
the first doped region a.
The second doping area B is transversely arranged with the first doping area A and is connected with the first doping area A.
And the PN junction area AB is arranged in the connection area of the first doped area A and the second doped area B, and delays partial widths of the first doped area A and the second doped area B respectively so as to enable the PN junction of the Zener diode formed by the connection area of the first doped area A and the second doped area B to be used as a burner.
Optionally, the first doped region a and the second doped region B may be polysilicon layers doped with N-type ions or P-type ions.
Furthermore, the layout structure of the burner provided by the invention may further include:
a metal gauge pattern C overlapped on the surface of the PN junction region AB;
a plurality of metal patterns D, one of which is overlapped on the surface of the first doped region a and one of which is overlapped on the surface of the second doped region B, so that the metal patterns D and the metal regular patterns C are arranged at intervals without being connected in the transverse direction;
a plurality of contact patterns E, at least two of which are disposed on a surface of each of the metal patterns E.
Wherein the contact pattern E may be a metal plug layer.
In summary, in the method for manufacturing the burner integrated in the semiconductor structure provided by the present invention, depending on the process conditions of the existing CMOS platform, a substrate layer for forming the PN junction of the zener diode in the subsequent step is formed on the surface of the semiconductor substrate corresponding to the shallow trench isolation structure having the isolation function, then the substrate layer is subjected to ion implantation twice to form the PN junction of the zener diode in the substrate layer, and then the zener diode is used as the burner integrated in the semiconductor structure provided by the present invention. The structure of the burner is the Zener diode which has the characteristic of being not recoverable (once read-write operation), so the burner formed by the invention can avoid the problem that in the prior art, a Metal Fuse (Metal Fuse) needs to be windowed on the surface of a chip during burning to ensure the purpose of once data read-write of the burner, and further needs an additional process.
In addition, the width of the PN junction of the Zener diode can be very narrow according to actual requirements, so that the Zener diode can be used as a burner to ensure the use reliability of a chip product and reduce the area and the manufacturing cost of the chip, thereby better meeting the design requirements of gradual integration and small size of a semiconductor process.
The embodiment of the invention also provides electronic equipment which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,
a memory for storing a computer program.
The processor is used for realizing the manufacturing method of the burner integrated in the semiconductor structure provided by the embodiment of the invention when the processor executes the program stored on the memory.
In addition, the other implementation manners of the method for manufacturing the burner integrated in the semiconductor structure, which is implemented by the processor executing the program stored in the memory, are the same as the implementation manners mentioned in the foregoing method embodiment portions, and are not described herein again.
The communication bus mentioned above for the control terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In another embodiment of the present invention, a computer-readable storage medium is further provided, where instructions are stored, and when the instructions are executed on a computer, the computer is made to execute any one of the above-mentioned methods for manufacturing a burner integrated in a semiconductor structure.
In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus, the electronic device, and the computer-readable storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and in relation to the description, reference may be made to some portions of the description of the method embodiments.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A method of making a burner integrated into a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a shallow trench isolation structure and a semiconductor device area defined by the shallow trench isolation structure are formed in the semiconductor substrate;
forming a substrate layer of a burner on the surface of the semiconductor substrate corresponding to the shallow trench isolation structure;
and carrying out an ion implantation process on the substrate layer of the burner so as to form a first doped region and a second doped region which are different in doping type in the substrate layer of the burner, wherein the first doped region and the second doped region are exposed on the surface of the substrate layer of the burner, the first doped region and the second doped region are transversely arranged and are connected with each other, so that the connected region of the first doped region and the second doped region forms a PN junction serving as a Zener diode of the burner.
2. The method of claim 1, wherein a material of a substrate layer of the burner comprises polysilicon.
3. The method as claimed in claim 1, wherein the first doped region has N-type doped ions and the second doped region has P-type doped ions.
4. The method of claim 3, wherein the step of forming the first doped region and the second doped region comprises:
forming a first photoresist layer for shielding half of the surface of the substrate layer of the burner on the surface of the substrate layer of the burner, and carrying out N-type or P-type ion implantation on the other half of the exposed surface of the substrate layer of the burner by taking the first photoresist layer as a mask to form a first doped region;
and forming a second photoresist layer on the surface of the substrate layer of the burner, which is exposed after the first photoresist layer is removed, by shielding the surface of the substrate layer of the burner, and performing P-type or N-type ion implantation on the other half surface of the exposed substrate layer of the burner by taking the second photoresist layer as a mask to form a second doped region.
5. The method of claim 1, wherein at least one MOS transistor is formed in the semiconductor device region.
6. A burner manufactured by the method of any one of claims 1 to 5 integrated in a semiconductor structure.
7. A burning system of burner, comprising a burner manufactured by the method of manufacturing burner integrated in semiconductor structure as claimed in any one of claims 1 to 5.
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| CN202210454789.2A CN114551238A (en) | 2022-04-28 | 2022-04-28 | Method for manufacturing burner integrated in semiconductor structure |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0054740A2 (en) * | 1980-12-23 | 1982-06-30 | American Microsystems, Incorporated | Zener diode burn prom |
| US6621138B1 (en) * | 2002-10-21 | 2003-09-16 | Micrel, Inc. | Zener-like trim device in polysilicon |
| CN101452938A (en) * | 2007-11-30 | 2009-06-10 | 上海华虹Nec电子有限公司 | Programmable non-volatile memory chip unit |
| CN101764133A (en) * | 2008-12-24 | 2010-06-30 | 上海华虹Nec电子有限公司 | Fast memory construction by using tunneling diode as selection switch tube |
| CN103377703A (en) * | 2012-04-13 | 2013-10-30 | 拉碧斯半导体株式会社 | Non-volatile memory and semiconductor device |
| CN104157629A (en) * | 2014-08-22 | 2014-11-19 | 中国电子科技集团公司第五十八研究所 | Zener diode anti-fuse structure and manufacturing method of Zener diode anti-fuse structure |
| CN104300000A (en) * | 2014-10-29 | 2015-01-21 | 深圳市可易亚半导体科技有限公司 | Power device with electrostatic protection structure and manufacturing method thereof |
| US20160064573A1 (en) * | 2014-08-29 | 2016-03-03 | Vanguard International Semiconductor Corporation | Semiconductor device including zener diode and method of manufacturing thereof |
-
2022
- 2022-04-28 CN CN202210454789.2A patent/CN114551238A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0054740A2 (en) * | 1980-12-23 | 1982-06-30 | American Microsystems, Incorporated | Zener diode burn prom |
| US6621138B1 (en) * | 2002-10-21 | 2003-09-16 | Micrel, Inc. | Zener-like trim device in polysilicon |
| CN101452938A (en) * | 2007-11-30 | 2009-06-10 | 上海华虹Nec电子有限公司 | Programmable non-volatile memory chip unit |
| CN101764133A (en) * | 2008-12-24 | 2010-06-30 | 上海华虹Nec电子有限公司 | Fast memory construction by using tunneling diode as selection switch tube |
| CN103377703A (en) * | 2012-04-13 | 2013-10-30 | 拉碧斯半导体株式会社 | Non-volatile memory and semiconductor device |
| CN104157629A (en) * | 2014-08-22 | 2014-11-19 | 中国电子科技集团公司第五十八研究所 | Zener diode anti-fuse structure and manufacturing method of Zener diode anti-fuse structure |
| US20160064573A1 (en) * | 2014-08-29 | 2016-03-03 | Vanguard International Semiconductor Corporation | Semiconductor device including zener diode and method of manufacturing thereof |
| CN104300000A (en) * | 2014-10-29 | 2015-01-21 | 深圳市可易亚半导体科技有限公司 | Power device with electrostatic protection structure and manufacturing method thereof |
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