CN101425519A - 制造在绝缘物上硅层中的瞬时电压抑制器 - Google Patents
制造在绝缘物上硅层中的瞬时电压抑制器 Download PDFInfo
- Publication number
- CN101425519A CN101425519A CNA200810165893XA CN200810165893A CN101425519A CN 101425519 A CN101425519 A CN 101425519A CN A200810165893X A CNA200810165893X A CN A200810165893XA CN 200810165893 A CN200810165893 A CN 200810165893A CN 101425519 A CN101425519 A CN 101425519A
- Authority
- CN
- China
- Prior art keywords
- transient voltage
- spare
- layer
- voltage suppresser
- tvs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001052 transient effect Effects 0.000 title claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 title claims description 20
- 239000010703 silicon Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 206010003497 Asphyxia Diseases 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 claims description 3
- 239000002800 charge carrier Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 230000001960 triggered effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract 3
- 230000003071 parasitic effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- 229920001296 polysiloxane Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Abstract
本发明涉及一种制造在绝缘物上硅层中的瞬时电压抑制器。在半导体衬底上支撑的瞬时电压抑制器件被用于保护电子器件免受瞬时电压的伤害。该瞬时电压抑制器件包括设置在由构成绝缘物上硅层中的瞬时电压抑制器件的绝缘层绝缘的半导体衬底的顶层上的与高压侧和低压侧二极管一起发挥作用以箝制瞬时电压的箝位二极管。在示例性实施例中,所述绝缘层还包括厚体氧化物层,该体氧化物层具有250埃到1微米范围内的厚度,用以承受所施加的高于25伏的击穿电压。在另一个示例性实施例中,箝位二极管由P阱进一步包围,该P阱形成在所述绝缘层上方设置的P-/P+衬底层的顶部。
Description
技术领域
本发明总体涉及制造瞬时电压抑制器(TVS)的电路结构和方法。更具体地,本发明涉及用于向TVS保护提供低电容的在绝缘物上硅(SOI)层中制造TVS的经改进的电路结构和方法。
背景技术
设计和制造瞬时电压抑制器(TVS)的常规技术仍然面临一定的技术难题。尤其是当应用标准CMOS工艺步骤在半导体衬底中的TVS上形成多个PN结二极管时,即会产生固有的PNP和NPN寄生晶体管。在ESD事件中或发生瞬时电压时,随着施加于TVS阵列的较大的电压,寄生NPN或PNP晶体管被导通或闭锁。所述闭锁可能导致突然和强烈的电压急变返回。突然和较大的急变返回可能导致系统不稳定甚至损坏的不希望的效应。另外,TVS阵列中的寄生NPN或PNP晶体管的闭锁还可能导致其他未预料或不需要的电压电流瞬时状态。在应用TVS保护实现的器件中,由于寄生电容和寄生PNP或NPN闭锁导致的技术难题不可能很容易解决。
通常,瞬时电压抑制器(TVS)普遍应用于保护集成电路免受由于不经意发生的在集成电路上施加超电压而造成的损坏。集成电路一般设计成在正常的电压范围内运行。然而,在诸如静电放电(ESD),快速电瞬变和放电的情形下,意外的和不受控制的高电压可能突然作用到电路上。因此需要TVS器件提供保护功能以规避在这样的超电压情形发生时可能发生的对集成电路造成的损坏。由于越来越多的设备用易于超电压损坏的集成电路实现,因此对TVS保护的需求也日益增加。TVS的示例性应用在USB电源和数据线保护,数字视频接口,高速以太网,笔记本电脑,监视器和平板显示器中都能找到。
图1A和1B分别显示TVS器件的电路图和电流电压关系图。当输入电压Vin小于击穿电压Vb时,理想的TVS完全阻断电流(也就是零电流)以将漏电流减到最小。而且,理想条件下,在输入电压Vin大于击穿电压Vb的情况下,TVS接近于零电阻,以使瞬时电压能被有效箝制。TVS能用PN结器件实现,PN结器件具有击穿电压,当瞬时输入电压超过该击穿电压时该PN结器件允许电流传导以实现瞬时电压保护。然而,PN结型的TVS没有少数载流子,并且由于如图1B所示的高电阻而具有较差的箝制性能。现在有应用双极型晶体管的雪崩触发导通的双极型NPN/PNP的TVS实施方案。基极充满少数载流子,并且因为雪崩电流通过双极型增益而被放大,双极型TVS能实现更好的电压箝制。
随着电子科技的发展,日益增多的设备和应用需要使用TVS二极管阵列进行ESD保护,尤其用于保护高带宽数据总线。参考图2A的四通道TVS的电路图和图2B的仅显示阵列器件核心的TVS阵列的器件实施方案的侧视截面图。如图2A和图2B所示的TVS阵列包括若干串联的高压侧和低压侧换向二极管,其中高压侧换向二极管连接到Vcc,低压侧换向二极管连接到地电位。另外,这些高压侧和低压侧换向二极管与主齐纳二极管并联,其中该换向二极管较小并且具有较低的结电容。另外,如图2C所示,这样的实施方案还产生另一个由于由寄生PNP和NPN晶体管诱发的可控硅(SCR)作用导致的闭锁问题。主齐纳二极管的击穿触发NPN使其导通,NPN的导通进一步使SCR导通而导致闭锁。在高温下,即使NPN没有导通,通过寄生NPN的NP结的高漏电流也可能使SCR导通而导致闭锁。为了抑制由寄生PNP和NPN晶体管诱发的SCR作用而导致的闭锁,半导体衬底上的实际器件需要在衬底上的如图2B所示的可能直至100微米或更大距离的横向扩展,并且所述抑制通常还不足够有效。
因此,在电路设计和器件制造的领域仍然需要提供新颖的和经改进的电路结构和制造方法来解决以上讨论的难题。具体地,仍然需要提供能有效和方便地减小电容并且还能防止寄生PNP/NPN晶体管闭锁的新颖的和经改进的TVS电路。
发明内容
因此,本发明的一个方面是提供以SOI结构实施TVS以减小寄生电容并且防止寄生PNP-NPN晶体管闭锁的新颖的和经改进的器件结构,因此可以克服以上讨论的常规TVS阵列遭遇的难题和限制。
本发明的另一个方面是在SOI层中形成TVS保护电路。相邻二极管之间的侧向距离可以被减少而与寄生电容和不经意的闭锁无关。
简略地,在优选实施例中,本发明公开了一种半导体衬底上支撑的瞬时电压抑制(TVS)器件。该TVS器件包括设置在由构成绝缘物上硅(SOI)器件上的TVS的绝缘层绝缘的半导体衬底的顶层上的与高压侧和低压侧二极管一起发挥作用以箝制瞬时电压的箝位二极管。在一个示范性实施例中,该绝缘层还包括厚体氧化物(BOX)层。在另一个特定的示范性实施例中,该绝缘层包括厚体氧化物(BOX)层,该厚体氧化物层具有250埃到1微米范围内的厚度以承受所施加的高于25伏的击穿电压。在另一个示例性实施例中,箝位二极管进一步由P阱包围,并且该P阱形成在设置于所述绝缘层上方的p-/p+衬底层的顶部。
本发明还公开了一种制造具有集成瞬时电压抑制(TVS)器件的电子器件的方法。该方法包括通过在绝缘层上方形成作为绝缘物上硅(SOI)层的硅层和形成与高压侧和低压侧二极管一起发挥作用以箝制SOI层中的电子器件的瞬时电压的箝位二极管而在半导体衬底上制造TVS阵列的步骤。在一个示范性实施例中,形成所述绝缘层的工艺还包括在半导体衬底上形成厚体氧化物层的步骤。在一个特定的实施例中,通过在P-晶片的顶表面形成厚氧化物层,然后将两个晶片的氧化物层面对面键合和熔融在一起,最后将衬底研磨成所需要厚度而形成BOX层。在另一个特定的实施例中,该方法还包括深掺杂注入半导体衬底以将BOX层上方的P-衬底层转化为P+层的步骤。
结合各个附图阅读下文对优选实施例的详细说明后,本发明的上述和其他目的和优点对于本领域的普通熟练技术人员无疑是显而易见的。
附图说明
图1A是显示常规TVS器件的电路图,图1B是用于说明TVS器件的反向特性的I-V图即电流电压图;
图2A显示TVS阵列的电路图,该TVS阵列包括连接到多个输入/输出(I/O)区的多个高压侧和低压侧二极管以及主齐纳二极管与该高压侧和低压侧二极管并联;
图2B是说明根据常规器件结构的图2A所示的TVS阵列的器件实施方案的侧截面图;
图2C显示说明如图2B实施的器件的潜在闭锁的等效电路图;
图3A到图3C分别是本发明的在具有深氧化物沟槽和半导体衬底上的厚硅的SOI层中形成的TVS的箝位二极管,低压侧/高压侧二极管和低压侧/高压侧二极管的侧截面图;
图3D和图3E分别是本发明的用横向NPN和横向NW NPN构造实现的图3A的TVS的侧截面图;
图4A到图4C分别是本发明的在具有薄硅部分耗尽的半导体衬底的SOI层中形成的TVS的箝位二极管,低压侧/高压侧二极管和低压侧/高压侧二极管的侧截面图;
图4D和图4E分别是本发明的用横向NPN和横向NW NPW构造实现的图4A的TVS的侧截面图;
图5A到图5C分别是本发明的在具有全部耗尽硅半导体衬底的SOI层中形成的TVS的箝位二极管,低压侧/高压侧二极管和低压侧/高压侧二极管的侧截面图;
图5D和5E是本发明的用横向NPN和横向NW NPN构造实现的图5A到5C的TVS的侧截面图。
具体实施方式
图3A到图3C是显示本发明的形成在绝缘物上硅(SOI)上的TVS的箝位二极管和高压侧/低压侧二极管的截面图。P型衬底105上淀积厚体氧化物(BOX)层110。BOX层110具有250埃到1微米范围内的厚度以承受所施加的高于25V的击穿电压。BOX的形成可以通过在P-晶片的顶表面上形成厚氧化物层,然后将两个晶片上的氧化物层面对面键合和熔融在一起,最后将衬底研磨成所需要厚度而实现,这是众所周知的工艺。可选的深掺杂注入可用于将BOX层上方的P—衬底层转换为P+层。在如图3A所示的实施例中,箝位二极管形成在可选的P-/P+衬底层120顶部的P阱(PW)130中。P掺杂区135的分级掺杂分布向由N+区140和P分级区135之间的结形成的箝位二极管提供触发电压调节。PN结从二极管阴极金属区150移开以避免在高电流击穿过程中熔化。P分级区135和P+阳极接触区165之间的距离向触发电路中连接的双极型器件提供所需要的分布电阻。局部氧化硅(LOCOS)层170将P分级掺杂区135与连接到阳极电极160的P+阳极接触区165分离。或者,可以使用未具体显示的浅沟槽隔离(STI)代替LOCOS层170。
在BOX层110包括可选P-/P+衬底层120的同一个衬底105上的同一个工艺过程期间,可以在芯片的不同区域中形成低压侧/高压侧二极管。图3B显示形成在与PW 130同时形成的P阱130′中的低压侧/高压侧二极管。N+区140′和P阱130′之间的二极管与N+区140同时形成。图3C显示高压侧/低压侧二极管,其中高压侧/低压侧二极管可以形成在例如NW区130"的N阱中。高压侧和低压侧二极管由阳极接触区165′和NW 130"形成。因此,箝位二极管也能形成在N阱NW(未具体显示)中。
为了改进电压箝制,在示例性实施例中,如图3D所示,在N+阴极掺杂区140,PW 130和P+掺杂区165之间实现双极型NPN晶体管以替代作为主箝制元件的二极管。图3D显示设置在P阱中的横向NPN晶体管。具体地,N+区140,P阱130和N+区180形成NPN晶体管。同时N+区140和P阱130还形成触发二极管,而当瞬时电压到达时,N+140和P阱130之间的结将被首先击穿并且电流将通过P阱流到通过电极160接地的P+区165。当电流增大到足够高时,由于P阱130中的分布电阻导致的电压降将导通双极型NPN晶体管,从而提供经改进的箝制功能。图3E提供了一个替代实施例,在该实施例中横向NPN结构还包括N阱190和N阱195。N阱190确保PN结从二极管阴极金属区150移开以避免在高电流击穿的过程中熔化。N阱190通过将发射极延伸至更深的深度扩大基极区,从而提供更深的载流子注入以增加高电流处理能力。N阱190还增加了基极电阻,即使在较低电流的情况下也有利于容易导通双极型NPN。
参考形成在薄硅层(约1μm)上的TVS的实施例的图4A到图4E,该实施例中的薄硅层部分耗尽。图4A是图3A的替代实施例,该实施例中P阱130的底部延伸至BOX层110,并且消除了P-/P+层120。图4B到图4E对应于图3B到图3E。除了由于薄硅层的耗尽而消除P-/P+层120之外,图4B到图4E的器件还用沉阱区175替代如图3B到3E中所示的氧化物沟槽以将器件与其他区域隔离。重掺杂沉阱区175提供寄生双极型晶体管的重掺杂基极区,因此抑制寄生双极型器件的增益以避免导致闭锁的急变返回。沉阱的使用还提供调节器件之间的距离的灵活性。
参考应用众所周知的CMOS技术的方法制造的形成在全耗尽硅层上的TVS的实施例的图5A到图5E。图5A到图5E对应于图3A到3E中的器件。图5A到图5E与图3A到3E所示的实施例的不同之处在于在很薄的硅层上制造器件。为了在薄硅层上形成TVS器件,所制造的TVS器件中消除了图3A—3E中所示的P-/P+层120和P阱层130。由于硅层很薄,因此可以向衬底中注入氧以形成硅注入氧化(SIMOX)薄层替代厚BOX层以减少生产成本。如图5D和5E所示,该截面图分别显示横向双极型晶体管和横向SCR器件。触发二极管路径在第三维中连接(未显示)。可以理解,基于以上结构通过简单变换掺杂类型的极性就可以制造互补的器件。
虽然按照目前的优选实施例描述了本发明,但是应该理解,本文公开的内容不能解释为对本发明的限制。阅读了上文的公开内容之后,对本发明的各种变化和修改对于本领域的普通熟练技术人员无疑是显而易见的。因此,附后的权利要求应被理解为涵盖落入本发明的真实精神和范围之内的所有替代和修改。
Claims (16)
1.一种在半导体衬底上支撑的瞬时电压抑制器件,其特征在于,该器件包括:
设置在由构成绝缘物上硅层上的瞬时电压抑制器件的绝缘层绝缘的半导体衬底的顶层上的与高压侧和低压侧二极管一起发挥作用以箝制瞬时电压的箝制元件。
2.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述绝缘层还包括厚体氧化物层。
3.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述绝缘层还包括厚体氧化物层,该厚体氧化物层具有250埃到1微米范围内的厚度以承受所施加的高于25伏的击穿电压。
4.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述箝制元件由P阱进一步包围。
5.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述箝制元件由所述绝缘层上方设置的P-/P+衬底层的顶部上的P阱进一步包围。
6.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述箝制元件还包括齐纳二极管。
7.如权利要求6所述的瞬时电压抑制器件,其特征在于,所述齐纳二极管还包括分级掺杂区域。
8.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述箝制元件还包括由二极管触发的双极型晶体管。
9.如权利要求8所述的瞬时电压抑制器件,其特征在于,所述双极晶体管还包括用于扩大基极区的延伸发射极区,通过提供更深的载流子注入增强高电流处理能力。
10.如权利要求1所述的瞬时电压抑制器件,其特征在于,所述绝缘层还包括硅注入氧化薄层。
11.如权利要求1所述的瞬时电压抑制器件,其特征在于,该瞬时电压抑制器件还包括:
将箝制元件与其他功能器件隔离的重掺杂沉阱。
12.如权利要求1所述的瞬时电压抑制器件,其特征在于,该瞬时电压抑制器件还包括:
填充沟槽以将箝制元件与其他功能器件隔离的电介质材料。
13.一种制造具有集成瞬时电压抑制器件的电子器件的方法,其特征在于,该方法包括:
通过在绝缘物上方形成作为绝缘物上硅层的硅层并且形成与高压侧和低压侧二极管一起发挥作用以箝制绝缘物上硅层中的所述电子器件的瞬时电压的箝位二极管而在半导体衬底上制造瞬时电压抑制器件。
14.如权利要求13所述的方法,其特征在于,所述形成绝缘层的工艺还包括在半导体衬底中形成厚体氧化物层的步骤。
15.如权利要求13所述的方法,其特征在于,所述形成绝缘层的工艺还包括通过在P-晶片的顶表面上形成厚氧化物层,然后将两个晶片的氧化层面对面键合和熔融在一起,最后将衬底研磨成所需要厚度而在半导体衬底中形成厚体氧化层的步骤。
16.如权利要求13所述的方法,其特征在于,该方法还包括:
深掺杂注入半导体衬底以使体氧化物层上方的P-衬底层转变为P+层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/982,557 US20090115018A1 (en) | 2007-11-01 | 2007-11-01 | Transient voltage suppressor manufactured in silicon on oxide (SOI) layer |
US11/982,557 | 2007-11-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101425519A true CN101425519A (zh) | 2009-05-06 |
Family
ID=40587255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA200810165893XA Pending CN101425519A (zh) | 2007-11-01 | 2008-10-06 | 制造在绝缘物上硅层中的瞬时电压抑制器 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20090115018A1 (zh) |
CN (1) | CN101425519A (zh) |
TW (1) | TWI382627B (zh) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102437156A (zh) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | 超低电容瞬态电压抑制器件及其制造方法 |
US8530902B2 (en) | 2011-10-26 | 2013-09-10 | General Electric Company | System for transient voltage suppressors |
CN103354229A (zh) * | 2013-07-11 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | 一种穿通型瞬态电压抑制器 |
CN103413807A (zh) * | 2013-07-15 | 2013-11-27 | 常州子睦半导体有限公司 | 低电容单向瞬态电压抑制器 |
US8987858B2 (en) | 2013-03-18 | 2015-03-24 | General Electric Company | Method and system for transient voltage suppression |
CN105489612A (zh) * | 2015-12-07 | 2016-04-13 | 上海长园维安微电子有限公司 | 基于soi基底的低漏电低电容tvs阵列及其制备方法 |
CN105703345A (zh) * | 2014-11-26 | 2016-06-22 | 鸿富锦精密工业(武汉)有限公司 | Usb静电防护电路 |
CN106057795A (zh) * | 2015-04-07 | 2016-10-26 | 美国亚德诺半导体公司 | 高速接口保护装置 |
CN106486474A (zh) * | 2015-08-31 | 2017-03-08 | 立锜科技股份有限公司 | 瞬时电压抑制元件及其制造方法 |
CN109599397A (zh) * | 2018-08-20 | 2019-04-09 | 晶焱科技股份有限公司 | 改良式瞬时电压抑制装置 |
CN111640740A (zh) * | 2020-06-03 | 2020-09-08 | 捷捷微电(上海)科技有限公司 | 一种tvs器件及其制造方法 |
CN115064585A (zh) * | 2022-08-17 | 2022-09-16 | 杭州致善微电子科技有限公司 | 一种tvs器件及其制作方法 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9793256B2 (en) * | 2006-11-30 | 2017-10-17 | Alpha And Omega Semiconductor Incorporated | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) |
US7679878B2 (en) * | 2007-12-21 | 2010-03-16 | Broadcom Corporation | Capacitor sharing surge protection circuit |
US8896064B2 (en) | 2010-10-18 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection circuit |
US8816476B2 (en) | 2011-04-27 | 2014-08-26 | Alpha & Omega Semiconductor Corporation | Through silicon via processing techniques for lateral double-diffused MOSFETS |
US8710627B2 (en) | 2011-06-28 | 2014-04-29 | Alpha And Omega Semiconductor Incorporated | Uni-directional transient voltage suppressor (TVS) |
US8698196B2 (en) | 2011-06-28 | 2014-04-15 | Alpha And Omega Semiconductor Incorporated | Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage |
TWI496274B (zh) * | 2012-06-08 | 2015-08-11 | Richtek Technology Corp | 暫態電壓抑制器電路及用於其中之二極體元件製造方法 |
CN103515940B (zh) * | 2012-06-18 | 2016-05-18 | 立锜科技股份有限公司 | 瞬时电压抑制器电路与用于其中的二极管元件及其制造方法 |
US8860082B2 (en) * | 2012-07-15 | 2014-10-14 | Richtek Technology Corporation, R.O.C. | Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof |
WO2014020372A1 (en) * | 2012-08-03 | 2014-02-06 | Freescale Semiconductor, Inc. | A semiconductor device comprising an esd protection device, an esd protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device |
US8791723B2 (en) * | 2012-08-17 | 2014-07-29 | Alpha And Omega Semiconductor Incorporated | Three-dimensional high voltage gate driver integrated circuit |
US9019667B2 (en) | 2012-11-08 | 2015-04-28 | Freescale Semiconductor Inc. | Protection device and related fabrication methods |
US9502890B2 (en) | 2013-05-22 | 2016-11-22 | Freescale Semiconductor, Inc. | Protection device and related fabrication methods |
US9129806B2 (en) | 2013-05-22 | 2015-09-08 | Freescale Semiconductor Inc. | Protection device and related fabrication methods |
US9438034B2 (en) | 2014-01-15 | 2016-09-06 | Nanya Technology Corporation | Transient voltage suppressor |
US9287255B2 (en) | 2014-07-09 | 2016-03-15 | Freescale Semiconductor Inc. | ESD protection device and related fabrication methods |
US20160064573A1 (en) | 2014-08-29 | 2016-03-03 | Vanguard International Semiconductor Corporation | Semiconductor device including zener diode and method of manufacturing thereof |
TWI557925B (zh) * | 2014-10-28 | 2016-11-11 | 世界先進積體電路股份有限公司 | 半導體裝置及其製造方法 |
US20170179226A1 (en) * | 2015-12-18 | 2017-06-22 | Microchip Technology Incorporated | Ultrasound t/r isoltation disolator with fast recovery time on soi |
US10978869B2 (en) | 2016-08-23 | 2021-04-13 | Alpha And Omega Semiconductor Incorporated | USB type-C load switch ESD protection |
JP6838504B2 (ja) * | 2017-06-16 | 2021-03-03 | 富士電機株式会社 | 半導体装置および半導体回路装置 |
US10242979B1 (en) * | 2018-06-26 | 2019-03-26 | Nxp Usa, Inc. | Dynamic substrate biasing for extended voltage operation |
US10825805B2 (en) * | 2018-10-26 | 2020-11-03 | Alpha & Omega Semiconductor (Cayman) Ltd. | Low capacitance transient voltage suppressor including a punch-through silicon controlled rectifier as low-side steering diode |
CN110098161A (zh) * | 2019-05-15 | 2019-08-06 | 苏州达晶微电子有限公司 | 浪涌保护器件 |
US20230010423A1 (en) * | 2021-07-06 | 2023-01-12 | Amazing Microelectronic Corp. | Multi-channel transient voltage suppression device |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4099998A (en) * | 1975-11-03 | 1978-07-11 | General Electric Company | Method of making zener diodes with selectively variable breakdown voltages |
US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
US5477078A (en) * | 1994-02-18 | 1995-12-19 | Analog Devices, Incorporated | Integrated circuit (IC) with a two-terminal diode device to protect metal-oxide-metal capacitors from ESD damage |
US6015993A (en) * | 1998-08-31 | 2000-01-18 | International Business Machines Corporation | Semiconductor diode with depleted polysilicon gate structure and method |
US6573565B2 (en) * | 1999-07-28 | 2003-06-03 | International Business Machines Corporation | Method and structure for providing improved thermal conduction for silicon semiconductor devices |
JP3675303B2 (ja) * | 2000-05-31 | 2005-07-27 | セイコーエプソン株式会社 | 静電気保護回路が内蔵された半導体装置及びその製造方法 |
US6489660B1 (en) * | 2001-05-22 | 2002-12-03 | General Semiconductor, Inc. | Low-voltage punch-through bi-directional transient-voltage suppression devices |
US6696731B2 (en) * | 2002-07-26 | 2004-02-24 | Micrel, Inc. | ESD protection device for enhancing reliability and for providing control of ESD trigger voltage |
US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US6888710B2 (en) * | 2003-01-03 | 2005-05-03 | Micrel, Incorporated | Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors |
FR2855908B1 (fr) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince |
US7453122B2 (en) * | 2005-02-08 | 2008-11-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | SOI MOSFET device with reduced polysilicon loading on active area |
US7919817B2 (en) * | 2008-05-16 | 2011-04-05 | Alpha & Omega Semiconductor Ltd. | Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies |
-
2007
- 2007-11-01 US US11/982,557 patent/US20090115018A1/en not_active Abandoned
-
2008
- 2008-10-06 CN CNA200810165893XA patent/CN101425519A/zh active Pending
- 2008-10-07 TW TW097138609A patent/TWI382627B/zh active
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8530902B2 (en) | 2011-10-26 | 2013-09-10 | General Electric Company | System for transient voltage suppressors |
US8765524B2 (en) | 2011-10-26 | 2014-07-01 | General Electric Company | Method and system for transient voltage suppressors |
CN102437156B (zh) * | 2011-12-13 | 2014-02-26 | 杭州士兰集成电路有限公司 | 超低电容瞬态电压抑制器件及其制造方法 |
CN102437156A (zh) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | 超低电容瞬态电压抑制器件及其制造方法 |
US8987858B2 (en) | 2013-03-18 | 2015-03-24 | General Electric Company | Method and system for transient voltage suppression |
CN103354229B (zh) * | 2013-07-11 | 2016-04-27 | 江苏艾伦摩尔微电子科技有限公司 | 一种穿通型瞬态电压抑制器 |
CN103354229A (zh) * | 2013-07-11 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | 一种穿通型瞬态电压抑制器 |
CN103413807A (zh) * | 2013-07-15 | 2013-11-27 | 常州子睦半导体有限公司 | 低电容单向瞬态电压抑制器 |
CN103413807B (zh) * | 2013-07-15 | 2015-11-25 | 常州子睦半导体有限公司 | 低电容单向瞬态电压抑制器 |
CN105703345A (zh) * | 2014-11-26 | 2016-06-22 | 鸿富锦精密工业(武汉)有限公司 | Usb静电防护电路 |
CN106057795A (zh) * | 2015-04-07 | 2016-10-26 | 美国亚德诺半导体公司 | 高速接口保护装置 |
CN106057795B (zh) * | 2015-04-07 | 2019-08-27 | 美国亚德诺半导体公司 | 高速接口保护装置 |
CN106486474A (zh) * | 2015-08-31 | 2017-03-08 | 立锜科技股份有限公司 | 瞬时电压抑制元件及其制造方法 |
CN106486474B (zh) * | 2015-08-31 | 2019-06-04 | 立锜科技股份有限公司 | 瞬时电压抑制元件及其制造方法 |
CN105489612A (zh) * | 2015-12-07 | 2016-04-13 | 上海长园维安微电子有限公司 | 基于soi基底的低漏电低电容tvs阵列及其制备方法 |
CN105489612B (zh) * | 2015-12-07 | 2019-07-23 | 上海长园维安微电子有限公司 | 基于soi基底的低漏电低电容tvs阵列及其制备方法 |
CN109599397A (zh) * | 2018-08-20 | 2019-04-09 | 晶焱科技股份有限公司 | 改良式瞬时电压抑制装置 |
CN109599397B (zh) * | 2018-08-20 | 2020-12-22 | 晶焱科技股份有限公司 | 改良式瞬时电压抑制装置 |
CN111640740A (zh) * | 2020-06-03 | 2020-09-08 | 捷捷微电(上海)科技有限公司 | 一种tvs器件及其制造方法 |
CN115064585A (zh) * | 2022-08-17 | 2022-09-16 | 杭州致善微电子科技有限公司 | 一种tvs器件及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI382627B (zh) | 2013-01-11 |
US20090115018A1 (en) | 2009-05-07 |
TW200922067A (en) | 2009-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101425519A (zh) | 制造在绝缘物上硅层中的瞬时电压抑制器 | |
US8461644B2 (en) | Latch-up free vertical TVS diode array structure using trench isolation | |
CN101517727B (zh) | 使用双极晶体管基极撷取的对称阻隔的瞬态电压抑制器 | |
US8338854B2 (en) | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode | |
US8835977B2 (en) | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode | |
US9461031B1 (en) | Latch-up free vertical TVS diode array structure using trench isolation | |
US8044457B2 (en) | Transient over-voltage clamp | |
US8743516B2 (en) | Sharing stacked BJT clamps for system level ESD protection | |
US9438033B2 (en) | Apparatus and method for protecting RF and microwave integrated circuits | |
US8823128B2 (en) | Semiconductor structure and circuit with embedded Schottky diode | |
US20090267154A1 (en) | Mos comprising substrate potential elevating circuitry for esd protection | |
CN101930975B (zh) | 在低电容瞬时电压抑制器(tvs)内整合控向二极管的优化配置 | |
CN106057781A (zh) | 静电放电保护器件的制造方法 | |
US8598625B2 (en) | ESD protection device with tunable design windows | |
US8859361B1 (en) | Symmetric blocking transient voltage suppressor (TVS) using bipolar NPN and PNP transistor base snatch | |
CN112447703A (zh) | 静电放电防护元件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20090506 |