TWI329918B - Semiconductor multi-package module having wire bond interconnection between stacked packages - Google Patents
Semiconductor multi-package module having wire bond interconnection between stacked packages Download PDFInfo
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- TWI329918B TWI329918B TW092125625A TW92125625A TWI329918B TW I329918 B TWI329918 B TW I329918B TW 092125625 A TW092125625 A TW 092125625A TW 92125625 A TW92125625 A TW 92125625A TW I329918 B TWI329918 B TW I329918B
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- package
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US41159002P | 2002-09-17 | 2002-09-17 | |
| US10/632,552 US20040061213A1 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US10/632,551 US6838761B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
| US10/632,553 US7053476B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US10/632,549 US7064426B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages |
| US10/632,568 US7205647B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
| US10/632,550 US6972481B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200419765A TW200419765A (en) | 2004-10-01 |
| TWI329918B true TWI329918B (en) | 2010-09-01 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092125625A TWI329918B (en) | 2002-09-17 | 2003-09-17 | Semiconductor multi-package module having wire bond interconnection between stacked packages |
| TW100113640A TWI469301B (zh) | 2002-09-17 | 2003-09-17 | 堆疊封裝間具有線接點互連之半導體多重封裝模組 |
| TW098139252A TWI378548B (en) | 2002-09-17 | 2003-09-17 | Semiconductor multi-package module having wire bond interconnection between stacked packages |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
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| TW100113640A TWI469301B (zh) | 2002-09-17 | 2003-09-17 | 堆疊封裝間具有線接點互連之半導體多重封裝模組 |
| TW098139252A TWI378548B (en) | 2002-09-17 | 2003-09-17 | Semiconductor multi-package module having wire bond interconnection between stacked packages |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1547141A4 (enExample) |
| JP (3) | JP4800625B2 (enExample) |
| KR (1) | KR101166575B1 (enExample) |
| AU (1) | AU2003272405A1 (enExample) |
| TW (3) | TWI329918B (enExample) |
| WO (1) | WO2004027823A2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406377B (zh) * | 2010-12-27 | 2013-08-21 | 力成科技股份有限公司 | 方向指示標記立體化之球格陣列封裝構造及其製造方法 |
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| US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
| US7394148B2 (en) | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
| SG130055A1 (en) | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
| SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
| JP5522561B2 (ja) * | 2005-08-31 | 2014-06-18 | マイクロン テクノロジー, インク. | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
| US8198735B2 (en) | 2006-12-31 | 2012-06-12 | Stats Chippac Ltd. | Integrated circuit package with molded cavity |
| US8124451B2 (en) | 2007-09-21 | 2012-02-28 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
| KR20110124063A (ko) | 2010-05-10 | 2011-11-16 | 하나 마이크론(주) | 적층형 반도체 패키지 |
| KR101688005B1 (ko) * | 2010-05-10 | 2016-12-20 | 삼성전자주식회사 | 이중 랜드를 갖는 반도체패키지 및 관련된 장치 |
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| US9165906B2 (en) | 2012-12-10 | 2015-10-20 | Invensas Corporation | High performance package on package |
| JP6128993B2 (ja) | 2013-06-28 | 2017-05-17 | キヤノン株式会社 | 積層型半導体装置、プリント回路板、電子機器及び積層型半導体装置の製造方法 |
| KR101563910B1 (ko) * | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 이의 제조 방법 |
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| JP6357371B2 (ja) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
| US9666730B2 (en) | 2014-08-18 | 2017-05-30 | Optiz, Inc. | Wire bond sensor package |
| KR101961377B1 (ko) * | 2015-07-31 | 2019-03-22 | 송영희 | 에지에 사이드 패드를 포함하는 lga 반도체 패키지 |
| KR101799668B1 (ko) * | 2016-04-07 | 2017-11-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
| CN110062956B (zh) * | 2016-12-30 | 2023-10-10 | 英特尔公司 | 用于高频通信的利用三维堆叠超薄封装模块设计的微电子器件 |
| KR102283390B1 (ko) | 2019-10-07 | 2021-07-29 | 제엠제코(주) | 멀티칩용 반도체 패키지 및 그 제조방법 |
| KR102325217B1 (ko) | 2020-05-18 | 2021-11-11 | 제엠제코(주) | 멀티 다이 스택 반도체 패키지 |
| CN114361063B (zh) * | 2021-11-24 | 2024-12-13 | 苏州科阳半导体有限公司 | 基板键合方法及基板 |
| US12469765B2 (en) | 2022-09-22 | 2025-11-11 | Apple Inc. | Thermally enhanced chip-on-wafer or wafer-on-wafer bonding |
| CN115410929B (zh) * | 2022-10-09 | 2024-09-24 | 江苏华创微系统有限公司 | 倒装芯片与底层芯片的堆叠结构的制备方法 |
| CN119916090B (zh) * | 2025-04-02 | 2025-07-04 | 杭州广立测试设备有限公司 | 晶圆的电容测试方法、装置、电子设备和存储介质 |
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-
2003
- 2003-09-15 EP EP03754585A patent/EP1547141A4/en not_active Ceased
- 2003-09-15 KR KR1020057004551A patent/KR101166575B1/ko not_active Expired - Fee Related
- 2003-09-15 WO PCT/US2003/028919 patent/WO2004027823A2/en not_active Ceased
- 2003-09-15 AU AU2003272405A patent/AU2003272405A1/en not_active Abandoned
- 2003-09-15 JP JP2004568930A patent/JP4800625B2/ja not_active Expired - Fee Related
- 2003-09-17 TW TW092125625A patent/TWI329918B/zh not_active IP Right Cessation
- 2003-09-17 TW TW100113640A patent/TWI469301B/zh not_active IP Right Cessation
- 2003-09-17 TW TW098139252A patent/TWI378548B/zh not_active IP Right Cessation
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2011
- 2011-06-21 JP JP2011137096A patent/JP5602685B2/ja not_active Expired - Fee Related
-
2013
- 2013-06-12 JP JP2013123601A patent/JP5856103B2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406377B (zh) * | 2010-12-27 | 2013-08-21 | 力成科技股份有限公司 | 方向指示標記立體化之球格陣列封裝構造及其製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005539403A (ja) | 2005-12-22 |
| WO2004027823A3 (en) | 2004-05-21 |
| JP2011181971A (ja) | 2011-09-15 |
| EP1547141A4 (en) | 2010-02-24 |
| AU2003272405A1 (en) | 2004-04-08 |
| JP2013211589A (ja) | 2013-10-10 |
| KR101166575B1 (ko) | 2012-07-18 |
| KR20050044925A (ko) | 2005-05-13 |
| EP1547141A2 (en) | 2005-06-29 |
| TW200419765A (en) | 2004-10-01 |
| TW201017853A (en) | 2010-05-01 |
| AU2003272405A8 (en) | 2004-04-08 |
| JP4800625B2 (ja) | 2011-10-26 |
| TWI378548B (en) | 2012-12-01 |
| TW201131731A (en) | 2011-09-16 |
| JP5856103B2 (ja) | 2016-02-09 |
| WO2004027823A2 (en) | 2004-04-01 |
| JP5602685B2 (ja) | 2014-10-08 |
| TWI469301B (zh) | 2015-01-11 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |