JP4800625B2 - 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール及びその形成方法 - Google Patents

積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール及びその形成方法 Download PDF

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JP4800625B2
JP4800625B2 JP2004568930A JP2004568930A JP4800625B2 JP 4800625 B2 JP4800625 B2 JP 4800625B2 JP 2004568930 A JP2004568930 A JP 2004568930A JP 2004568930 A JP2004568930 A JP 2004568930A JP 4800625 B2 JP4800625 B2 JP 4800625B2
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package
die
substrate
stacked
mpm
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JP2005539403A (ja
JP2005539403A5 (enExample
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マルコス カーネゾス
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Stats Chippac Inc
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Stats Chippac Inc
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Priority claimed from US10/632,568 external-priority patent/US7205647B2/en
Priority claimed from US10/632,551 external-priority patent/US6838761B2/en
Priority claimed from US10/632,552 external-priority patent/US20040061213A1/en
Priority claimed from US10/632,553 external-priority patent/US7053476B2/en
Priority claimed from US10/632,549 external-priority patent/US7064426B2/en
Priority claimed from US10/632,550 external-priority patent/US6972481B2/en
Application filed by Stats Chippac Inc filed Critical Stats Chippac Inc
Publication of JP2005539403A publication Critical patent/JP2005539403A/ja
Publication of JP2005539403A5 publication Critical patent/JP2005539403A5/ja
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2004568930A 2002-09-17 2003-09-15 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール及びその形成方法 Expired - Fee Related JP4800625B2 (ja)

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US10/632,549 2003-08-02
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US10/632,552 US20040061213A1 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,552 2003-08-02
US10/632,550 2003-08-02
US10/632,553 US7053476B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,549 US7064426B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages
US10/632,568 2003-08-02
US10/632,553 2003-08-02
US10/632,568 US7205647B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US10/632,550 US6972481B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
PCT/US2003/028919 WO2004027823A2 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

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