JP2013211589A - 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール - Google Patents
積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール Download PDFInfo
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- JP2013211589A JP2013211589A JP2013123601A JP2013123601A JP2013211589A JP 2013211589 A JP2013211589 A JP 2013211589A JP 2013123601 A JP2013123601 A JP 2013123601A JP 2013123601 A JP2013123601 A JP 2013123601A JP 2013211589 A JP2013211589 A JP 2013211589A
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- 239000004065 semiconductor Substances 0.000 title abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 301
- 229910052751 metal Inorganic materials 0.000 claims description 201
- 239000002184 metal Substances 0.000 claims description 201
- 238000000034 method Methods 0.000 claims description 107
- 238000012360 testing method Methods 0.000 abstract description 21
- 238000013100 final test Methods 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 description 126
- 230000001070 adhesive effect Effects 0.000 description 126
- 229910000679 solder Inorganic materials 0.000 description 96
- 230000008569 process Effects 0.000 description 83
- 239000002775 capsule Substances 0.000 description 55
- 239000012778 molding material Substances 0.000 description 40
- 238000000465 moulding Methods 0.000 description 31
- 150000001875 compounds Chemical class 0.000 description 29
- 238000012545 processing Methods 0.000 description 28
- 125000006850 spacer group Chemical group 0.000 description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 25
- 229910052802 copper Inorganic materials 0.000 description 25
- 239000010949 copper Substances 0.000 description 25
- 239000004020 conductor Substances 0.000 description 21
- 230000002093 peripheral effect Effects 0.000 description 20
- 230000015572 biosynthetic process Effects 0.000 description 18
- 238000005336 cracking Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 239000004593 Epoxy Substances 0.000 description 15
- 230000017525 heat dissipation Effects 0.000 description 14
- 238000013461 design Methods 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 238000007373 indentation Methods 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 9
- 239000012467 final product Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000047 product Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004080 punching Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052728 basic metal Inorganic materials 0.000 description 4
- 150000003818 basic metals Chemical class 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000010953 base metal Substances 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- AOSZTAHDEDLTLQ-AZKQZHLXSA-N (1S,2S,4R,8S,9S,11S,12R,13S,19S)-6-[(3-chlorophenyl)methyl]-12,19-difluoro-11-hydroxy-8-(2-hydroxyacetyl)-9,13-dimethyl-6-azapentacyclo[10.8.0.02,9.04,8.013,18]icosa-14,17-dien-16-one Chemical compound C([C@@H]1C[C@H]2[C@H]3[C@]([C@]4(C=CC(=O)C=C4[C@@H](F)C3)C)(F)[C@@H](O)C[C@@]2([C@@]1(C1)C(=O)CO)C)N1CC1=CC=CC(Cl)=C1 AOSZTAHDEDLTLQ-AZKQZHLXSA-N 0.000 description 2
- 229940126657 Compound 17 Drugs 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 125000003700 epoxy group Chemical group 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- TVTJUIAKQFIXCE-HUKYDQBMSA-N 2-amino-9-[(2R,3S,4S,5R)-4-fluoro-3-hydroxy-5-(hydroxymethyl)oxolan-2-yl]-7-prop-2-ynyl-1H-purine-6,8-dione Chemical compound NC=1NC(C=2N(C(N(C=2N=1)[C@@H]1O[C@@H]([C@H]([C@H]1O)F)CO)=O)CC#C)=O TVTJUIAKQFIXCE-HUKYDQBMSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 229940125851 compound 27 Drugs 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/732—Location after the connecting process
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/732—Location after the connecting process
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- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
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Abstract
【解決手段】積み重ねられた下側および上側パッケージ400,500を有する半導体マルチパッケージモジュール50であって、パッケージ400,500のそれぞれは、基板412,512に取り付けられたダイス414,514を有し、上側および下側基板412,512は、ワイヤボンディング518により相互接続される。
【選択図】図5A
Description
図1は積み重ねられたマルチパッケージモジュール(「MPM」)のボトムパッケージとして用いることができ、産業界でよく確立された標準的なボールグリッドアレイ(「BGA」)パッケージの構造を例示する断面図である。BGAは、一般的に10のように示され、少なくとも1つの金属レイヤを有する基板12の上に取り付けられたダイス14を有している。様々な基板形式のいずれかが用いられ、例えば、1−2の金属レイヤをラミネートしたもの、4−8の金属レイヤを有する基板構造、1−2の金属レイヤを有するフレキシブルポリイミドテープまたはセラミックマルチレイヤ基板が含まれる。図1の例によって示された基板12は、2つの金属レイヤ121,123を有し、適当な回路構成を提供すべくパターンがそれぞれ形成され、バイアス122を経由して互いに接続されている。ダイスは、所定の箇所で基板表面に図1の13で示されるダイス接着エポキシとして一般的に参照される接着剤を用いて取り付けられる。そして、図1の構成において、例え、ダイス接着表面が使用時において特定の方位が必要でなくても、ダイスが取り付けられた基板上の表面は、「上側」表面として参照され、当該表面上のの金属レイヤは、「上側」金属レイヤとして参照される。
単に平面のヒートスプレッダをドロップインモールド処理したり、トップパッケージダイスの上側表面またはトップパッケージ上のスペーサの上側表面に接着剤を適用し、当該接着剤の上に平面のヒートスプレッダを取り付けたりすることにより挿入する。
に記載されているような公知技術によって形成してもよい。パッケージ相互間のz軸相互接続ワイヤボンドは、トップ基板の上側金属レイヤ上のパッド上側表面に溶着または圧着し、そしてそこから下方に向けてワイヤを引き、ボトム基板の上側金属レイヤ上のパッド上に溶融することにより形成しているものとして図5Aに例として示されている。好ましくは、ワイヤボンドは逆の方向に形成することができる。即ち、ボトム基板の上側金属レイヤ上のパッド上側表面に溶着または圧着し、そしてそこから上方に向けてワイヤを引き、トップ基板の上側金属レイヤ上のパッド上に溶融させることにより形成することができる。好ましくは、パッケージ相互間のz軸相互接続のワイヤボンドの構成の選択は、積み重ねられた基板の縁部とそれらの接続面との幾何学的な配置に従って決定される。
トップパッケージ基板、413 接着剤、414 ダイス、415,427 はんだマスク、416 ワイヤボンド、417 モールディングコンパウンド、418 はんだボール、419 ボトムパッケージ上側表面、421,423 金属レイヤ、422 バイアス、424 ボトムパッケージz軸相互接続パッド、426 カプセル体の縁部、500 トップパッケージ、501 縁部、503,513 接着剤、507 モジュールカプセル体、512 トップパッケージ基板、514 ダイス、515,527 はんだマスク、516,518 ワイヤボンド、517 モールディングコンパウンド、519 トップパッケージ上側表面、521,523 金属レイヤ、522 バイアス、524 トップパッケージz軸相互接続パッド、525 上側表面、526 カプセル体の縁部。
Claims (3)
- 積み重ねられた第1および第2パッケージを具備するマルチパッケージモジュールであって、前記パッケージのそれぞれは、基板に取り付けられたダイスを有し、第1および第2の基板は、ワイヤボンディングにより相互接続され、前記第1パッケージは、上向きダイス構成のフリップチップを有するフリップチップボールグリッドアレイパッケージを具備することを特徴とするマルチパッケージモジュール。
- 第1パッケージ基板を有する上向きダイスフリップチップ第1パッケージを供給し、
ダイスおよび第2パッケージ基板を有する第2パッケージを供給し、前記第1パッケージ上に前記第2パッケージを積み重ね、
前記第1パッケージ基板と第2パッケージ基板とをワイヤボンド接続することにより、前記第1および第2パッケージを電気的に相互接続することを特徴とするマルチパッケージモジュールの形成方法。 - 第1基板と、該第1基板上に形成された第1金属レイヤとを有する第1パッケージを供給し、
第2基板と、ダイスと、前記第2基板上に形成された第2金属レイヤと、前記ダイスと前記第2金属レイヤとを電気的に接続する第1ワイヤボンドとを有する第2パッケージを供給し、
前記第1パッケージ上に前記第2パッケージを積み重ね、そして、
第2ワイヤボンドにより前記第1パッケージの第1金属レイヤおよび前記第2パッケージの第2金属レイヤ間の電気的相互接続を形成することを特徴とするマルチパッケージモジュールの形成方法。
Applications Claiming Priority (14)
Application Number | Priority Date | Filing Date | Title |
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US41159002P | 2002-09-17 | 2002-09-17 | |
US60/411,590 | 2002-09-17 | ||
US10/632,550 US6972481B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
US10/632,552 | 2003-08-02 | ||
US10/632,553 US7053476B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
US10/632,551 | 2003-08-02 | ||
US10/632,553 | 2003-08-02 | ||
US10/632,552 US20040061213A1 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
US10/632,568 | 2003-08-02 | ||
US10/632,549 | 2003-08-02 | ||
US10/632,551 US6838761B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US10/632,568 US7205647B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
US10/632,550 | 2003-08-02 | ||
US10/632,549 US7064426B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages |
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JP2011137096A Division JP5602685B2 (ja) | 2002-09-17 | 2011-06-21 | マルチパッケージモジュールおよびその形成方法 |
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JP2013211589A true JP2013211589A (ja) | 2013-10-10 |
JP5856103B2 JP5856103B2 (ja) | 2016-02-09 |
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JP2011137096A Expired - Fee Related JP5602685B2 (ja) | 2002-09-17 | 2011-06-21 | マルチパッケージモジュールおよびその形成方法 |
JP2013123601A Expired - Lifetime JP5856103B2 (ja) | 2002-09-17 | 2013-06-12 | 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール |
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Country Status (6)
Country | Link |
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EP (1) | EP1547141A4 (ja) |
JP (3) | JP4800625B2 (ja) |
KR (1) | KR101166575B1 (ja) |
AU (1) | AU2003272405A1 (ja) |
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- 2003-09-15 KR KR1020057004551A patent/KR101166575B1/ko active IP Right Grant
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- 2003-09-17 TW TW098139252A patent/TWI378548B/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
WO2004027823A2 (en) | 2004-04-01 |
WO2004027823A3 (en) | 2004-05-21 |
EP1547141A4 (en) | 2010-02-24 |
JP4800625B2 (ja) | 2011-10-26 |
AU2003272405A8 (en) | 2004-04-08 |
JP2005539403A (ja) | 2005-12-22 |
AU2003272405A1 (en) | 2004-04-08 |
TW201131731A (en) | 2011-09-16 |
JP5856103B2 (ja) | 2016-02-09 |
EP1547141A2 (en) | 2005-06-29 |
KR20050044925A (ko) | 2005-05-13 |
TW200419765A (en) | 2004-10-01 |
JP5602685B2 (ja) | 2014-10-08 |
TWI469301B (zh) | 2015-01-11 |
KR101166575B1 (ko) | 2012-07-18 |
TW201017853A (en) | 2010-05-01 |
JP2011181971A (ja) | 2011-09-15 |
TWI329918B (en) | 2010-09-01 |
TWI378548B (en) | 2012-12-01 |
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