TWI327779B - Strained dislocation-free channels for cmos and method of manufacture - Google Patents

Strained dislocation-free channels for cmos and method of manufacture Download PDF

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TWI327779B
TWI327779B TW093131406A TW93131406A TWI327779B TW I327779 B TWI327779 B TW I327779B TW 093131406 A TW093131406 A TW 093131406A TW 93131406 A TW93131406 A TW 93131406A TW I327779 B TWI327779 B TW I327779B
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channel
material layer
layer
nfet
pfet
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Dureseti Chidambarrao
Omer H Dokumaci
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Description

1327779 九、發明說明： 【發明所屬之技術領域】 本發明大體上係關於一種半導體裝置及其製造方法，且 更特定言之，本發明係關於在裝置製造期間在裝置中施加 拉伸應力及壓縮應力之半導體裝置及其製造方法。 【先前技術】 半導體裝置基板内之機械應力可調變裝置效能。意即， 已知半導體裝置内的應力可增強半導體裝置特徵。因此， 為改良半導體裝置特徵，在η型裝置（例如NFET)及/或p型裝 置（例如PFET)之通道中產生拉伸及/或壓縮應力，然而，相 同的應力分量（拉伸應力或壓縮應力）會不同地影響η型裝置 及Ρ型裝置之特徵。 為使積體電路（1C)晶片内之nFET與pFET的效能最大化， 對於nFET與pFET而言應不同地設計並施加應力分量。意 即’因為對nFET之效能有益的應力類型大體而言對pFET之 效能不利。更特定言之，當裝置處於拉伸狀態（例如，在平
面裝置中電流之方向上）時’ nFET之效能特徵增強，而pFET 之效能特徵則減弱。為選擇性地在nFET中產生拉伸應力且 在pFET中產生壓縮應力，使用了不同的處理及不同的材料 組合。 舉例而S ’已建議將一渠溝隔離結構用於在㈤叮與pFET 中为別形成合適的應力。當使用此方法時，nFET裝置之隔 離區域包含第一隔離材料，其在縱向上（例如，平行於電流 之方向）及在杈向上（例如，垂直於電流之方向）將第一類型 96246.doc 1327779 之機械應力施加於nFET裝置上。此外，為pFET提供了第一 隔離區域及第二隔離區域，且該pFET裝置之各個隔離區域 在橫向及縱向上將一獨特的機械應力施加於pFET裝置上。 或者，已建議將閘極側壁上之襯墊用以選擇性地在FET 裝置之通道中引發合適應力（舉例而言，參考〇otsuka等人之 IEDM 2000’第575頁）。藉由提供襯墊，可將合適應力比由 於渠溝隔離填充技術而施加之應力更接近地施加至裝置。
儘管此等方法確實提供了具有施加至nFET裝置之拉伸 應力及沿pFET裝置之縱向而施加之壓縮應力的結構，但其 可需要額外的材料及/或更多複雜處理，且因此導致成本更 高。此外’能在此等情況下施加的應力水平通常適度（例 如，大約為100 MPah因此，需要提供更具成本效益且更 簡單之方法以用於在nFET及pFET通道中分別產生很大拉 伸應力及壓縮應力。 【發明内容】
在本發明之第一態樣中，提供了一種用於製造半導體結 構之方法。該方法包括在一基板中形成p型場效電晶體 (pFET)通道及η型場效電晶體（nFET)通道。在pFET通道中提 供一具有與基板之晶格常數不同之晶格常數的第一材料 層’且在nFET通道中提供一具有與基板之晶格常數不同之 晶格常數的第二材料層。在pFET通道中之第一材料層上及 在nFET通道中之第一材料層上形成一蠢晶半導體層。該蟲 晶半導體層具有與基板大體上相同之晶格常數，使得在 pFET通道及nFET通道内產生應力分量。 96246.doc 1327779 在本發明之另一態樣中，提供了一種製造一半導體結構 之方法。該方法包括在諸如Si或絕緣層上覆矽之基板層中 形成pFET與nFET通道。在pFET通道中提供一具有與基板層 之晶格常數不同之晶格常數的第一材料層，且在nFET通道 中提供一具有與基板層之晶格常數不同之晶格常數的第二 材料層。在pFET通道中之第一材料層上及在nFET通道中之 第二材料層上形成一磊晶半導體層。該磊晶半導體層具有 與基板層大體上相同之晶格常數，因此產生了與pFET通道 中之第一材料層的應力分量及nFET通道中之第二材料層的 應力分量相反的應力分量。 在本發明之另一態樣中，一半導體結構包括一 pFET及 nFET通道，其形成於諸如（舉例而言）Si層之基板中。在該 Si層中及在pFET通道中之具有與該Si層之晶格常數不同之 晶格常數的第一材料層中形成淺溝槽隔離結構。nFET通道 中之第二材料層具有與該Si層之晶格常數不同的晶格常 數。在pFET通道中之第一材料層及nFET通道中之第二材料 層上所形成的一磊晶半導體層具有與該Si層大體上相同之 晶格常數，因此在pFET通道與nFET通道中產生了吾人所要 之應力分量。 【實施方式】
本發明係針對一種在CMOS裝置之nFET通道中提供拉伸 應力及在pFET通道中提供壓縮應力的半導體裝置及其製造 方法。在一實施例中，在pFET通道中亦可提供高拉伸應力 以增強裝置效能。在本發明之一實施例中，在nFET與pFET 96246.doc 1327779 之形成區域内的矽層中形成通道。接著使該等通道填充有 矽基材料，該矽基材料具有自然存在並與下面的梦層之晶 格常數不匹配之晶格常數。藉由施加此等材料，拉伸及/或 壓縮力分別在nFET與pFET通道中導致產生一上覆磊晶 層。在一實施例中，可同時形成nFET與pFET通道。藉由使 用本發明之製程，以達到改善之裝置特徵，以及更高之良 率與更低之裝置缺陷。同樣，能以本發明之製程，實現更 低的製造成本。
圖la至If表示形成本發明之裝置之製程。在圖1&中，提 供例如絕緣層上覆矽（SOI)或諸如此類之基板1〇。其包括埋 藏氧化層15及絕緣層上覆矽層20(例如，Si層）。可藉由該技 藝中所熟知的SIMOX或黏著技術來形成該s〇l晶圓。在一實 施例中，Si層20約為300 A至1500人；然而，應瞭解，本發 明根據特定應用，仔細考量Si層20之高度變化。
仍參考圖la’接著使用墊氧化、墊氮化物沉積、以微影 術為基礎之圖案化、由氮化物、氧化物及矽所組成之堆疊 的反應性離子蝕刻（RIE)下至該埋藏氧化層、邊緣氧化、線 層沉積、填補沉積及化學機械研磨之標準技術圖案化該si 層20，以形成淺溝槽隔離特徵（STI)25。該STI形成處理在該 技術中是已知的。接著剝離該墊氮化物。 現參考圖lb，將氧化層32沉積於STI區域25與Si層20經研 磨之表面上。該氧化層32之高度可變化，而且於一實施例 中約為200 A。將任一已知之光阻材料之光阻層35沉積在氧 化層32上》在使用已知遮罩與微影圖案化技術之後，接著 96246.doc 1327779 在光阻層35與氧化層32上執行（例如）反應性離子蝕刻。此步 驟中之反應性離子蝕刻對氧化層而言可具有選擇性。此開 始了同時形成pFET通道40及nFET通道45之處理。在進行了 氧化物蝕刻之後，使用反應性離子蝕刻來選擇地蝕刻以層 20，如圖lc中所示。 在一替代步驟中，視所需蝕刻之深度而定使用2ei4#/cm2 至lel5#/cm2之典型劑量及10匕乂至丨⑽keV範圍内之能量下 的Ge植入來首先非晶化。可使用此可任選的非晶化步驟 以改良蝕刻品質。在任一製造中，在8丨層2〇中形成分別對 應於pFET與nFET之位置的通道4〇及45。在一實行中，在Si 層20中將通道40及45蝕刻成約200 A至400 A之深度。然 而，此深度可視本發明所使用之特定應用而定來變化。 圖Id表示根據本發明之進一步製程。在此等製程中，使 用任何已知之處理來移除光阻材料35。使用任何已知微影 處理在pFET通道40中圖案化硬式遮罩5〇。在一實施例中， 該硬式遮罩為氮化物材料且在接近pFET通道4〇之氧化層32 上被圖案化。SiGe層45a在nFET通道45中磊晶成長為約10〇 A至300A之厚度，但是本發明亦涵蓋其它厚度。 獨特的是，該SiGe通常具有比〜層2〇更大的晶格常數。 意即，SiGe材料之晶格常數與以層2〇之晶格常數不匹配。 然而，在本發明之結構中，歸因KSiGe層45a在nFET通道45 中之成長，SiGe層45a之晶格結構將易於與下面之8丨層2〇的 晶格結構匹配。 因為SiGe層45a(其通常較大）與；5丨層2〇晶格匹配，所以此 96246.doc 1327779 導致SiGe層45a及周圍區域處於壓縮狀態下。但是該以以層 之周圍區域將試圖達到均衡狀態，因而導致SiGe層45a上所 形成磊晶Si層產生拉伸應力(如圖lf中所示）。在一實施例 中义^層453之Ge含量與Si含量之比率可為5%至5〇%。 在圖le中，藉由任何已知之處理來移除硬式遮罩％。使 用任何已知之微影處理在nFET通道45中將硬式遮罩55圖案 化。硬式遮罩55亦在接近nFET通道45之氧化層32上且因此 在所成長之SiGe層45a上被圖案化。再次，在一實施例中， 硬式遮罩55為氮化物材料。接著以:(：層4〇a在pFET之通道4〇 中磊晶成長為約1〇〇 A至300 A之厚度，但是本發明亦涵蓋 了其匕厚度。一般熟習此項技術者應瞭解，圖卜之處理步 驟同樣可先於圖Id中所示之處理步驟而執行。 獨特的是，Si:C通常具有比Si層20更小的晶格常數。意 即’ Si:C材料之晶格常數與8丨層2〇之晶格常數不匹配。然 而’在本發明之結構中，歸因於以:(：層4〇3在]317^1通道4〇 中之成長，Si:C層40a之晶格結構將易於與下面之以層2〇的 晶格結構匹配。 因為Si:C層40a(其通常較小）與si層20晶格匹配，所以此 導致8丨:(：層4(^及周圍區域處於拉伸應力下。與|5丨(36層所發 生的相似，Si:C層40a之周圍區域將試圖達到均衡狀態，因 而導致Si:C層40a上所形成之磊晶Si層產生壓縮應力。在一 實施例中，C含量與Si含量之比率可為〇%至4〇/〇。 圖If展示了 一中間結構。為獲得此結構，以與參考圖le 所描述之方式類似的方式來移除硬式遮罩55。Si磊晶層6〇 96246.doc 1327779 選擇性地分別在pFET與nFET通道中之Si:C層與SiGe層上 成長。在一貫施例中，如上所論述，Si磊晶層6〇與SiGe 45a 或Si:C 40a之周圍結構相稱，且Si絕緣層2〇導致在nFET通道 ·· 45中產生拉伸應力且在pFET通道4〇中產生壓縮應力。應瞭 解’藉由調整SiGe層中Ge含量之濃度，可調整nFET通道45 中之拉伸應力。相似地，藉由調整Si:c層中之c的濃度，接 著可調整pFET通道40中之壓縮應力。此係歸因於此等材料 之晶格常數。 仍參考圖If，接著在選擇性成長之磊晶8丨層6〇上成長犧 % 牲氧化層65。接著使用標準以光阻材料為主之微影技術， 遮罩該pFET’以便執行該nFET通道植入。在剝離該相關之 光阻材料（未顯示於圖lf中）之後，接著遮罩該nFET(再次使 用t準以光阻材料為主之微影技術），且執行該pFET通道植 入，緊接著另一光阻材料剝離。接著，剝離犧牲氧化層65， 且如圖1 f所顯示’成長該閘極氧化層7〇。接著，在ρρΕτ與 nFET區域中形成該閘極多晶矽7〇。執行熟悉此項技術者所 熟知的閘極多晶矽沉積及化學機械研磨，以產生圖丨f所顯 φ 示之結構。 在剝離該鑲嵌氧化層32之後，標準CMOS處理可繼續該處 理。例如，在使用任何已知之處理剝離氧化層32之後，可 執行標準隔片及離子植入處理’以形成該等pFET與nFET之 · 延伸部分、源極與沒極區域。 圖2a至2d表示另一形成本發明之裝置之製程。於圖 中以用於圖la之同一方式’形成該基板與STI»於圖2a中， 96246.doc • 12- 1327779 提供例如絕緣層上覆矽（SOI)或諸如此類之基板〗其包括 埋藏氧化層1 5及絕緣層上覆矽層20〇可藉由該技藝熟知的 SIMOX或黏著技術形成該S〇I晶圓。於一實施例中該以 層20約為300 A至1500 A ;然而’應瞭解，本發明根據特定 應用’仔細考量Si層20之高度變化。 仍參考圖2a ’接著使用墊氧化、墊氮化物沉積、基於微 影術之圖案化、由氮化物、氧化物及直至埋藏氧化物之矽 組成之堆疊的反應性離子蝕刻（RIE)、邊緣氧化、襯墊沉 積、填充沉積及化學機械研磨之標準技術來圖案化“層2〇 以形成淺溝槽隔離特徵（STI)25。該STI形成處理為此項技術 中所熟知。接著剝離該墊氮化物。 現參考圖2b，將氧化層32沉積於STI區域25與Si層20之經 研磨表面上。此氧化層32之高度可變化，且在一實施例中 約為200 A。將可為任何已知光阻材料之光阻層35沉積於氧 化層32上。在使用了已知遮罩與微影圖案化技術之後，接 著在光阻層35與氧化層32上執行（例如）反應性離子蝕刻。此 步驟中之反應性離子蝕刻對氧化層而言可具有選擇性。此 開始了形成nFET通道45之處理。在氧化物蝕刻之後，使用 反應性離子蝕刻來選擇性地蝕刻該Si層20。可執行任選之 非s曰系Si蝕刻以改良蝕刻品質。在一實行中，在“絕緣層2〇 中將通道45蝕刻成約為200 A至400 A之深度。然而 ，視本 發明所使用之特定應用而定此深度可變化。 在一替代步驟中，視所需蝕刻之深度而定，使用2el4#/cm2 至1 el5#/Cm之典型劑量及1〇 keV至1〇〇 keV範圍内之能量下 96246.doc 1327779 的Ge植入來首先非晶化Si。可使用此任選的非晶化步驟以 改良蝕刻品質。在任一製造中，在Si層20中形成通道40及 45以分別對應於pFET與nFET之位置。在一實行中，在Si層 20中將通道40及45蝕刻成約200 A至400 A之深度。然而， 視本發明所使用之特定應用而定此深度可變化。 圖2c代表根據本發明之進一步製程。在此等製程中，gjiGe 層45a在nFET之通道45中成長為約100 A至300 A之高度，但 是本發明亦涵蓋了其它高度。在一實施例中，SiGe之Ge含 量與Si含量之比率可為〇%至50%，較佳為約15。/(^接著，在 nFET通道45中之SiGe層45a上選擇性地成長磊晶Si層60。接 著’ 一犧牲性閘極氧化層在該選擇性地成長之以層6〇上成 長。接著’使用任何熟知之製程來提供nFET遮罩及凹拼植 入。接著，在nFET區域中形成閘極氧化物65a。接著，沉積 閘極多晶矽70a，緊接著進行一般熟習此項技術者所熟知的 化學機械研磨以產生圖2c中所示之結構。 可使用此相同處理以形成裝置之pFET，其可由圖几與〜 同等表示。PFET結構併入了 Si:c而非siGe。在圖2d中展示 了最終產品，其展示了可併入選擇性si:c閘極氧化物65b及 閘極多晶矽70b之pFET。將氧化物32剝離且可使用標準 CMOS處理來繼續該處理。此等包括擴展部分、源極與汲極 區域、矽成形、氮化物蝕刻擋止層、接觸處理、互連等等。 在本發明之另一實施例中，若能在以以材料之通道中達 成比約3 GPa更大的應力水平，則可在1?1^丁與111^丁通道中 使用該SiGe材料。因為此方法需要非鬆弛系統，因此其能 96246.doc 1327779 有助於很大的GE含量。因此，可使用所描述之用於pFET的 SiGe沉積步驟。然而，應瞭解，由於諸如高應力及錯位問 題之競爭需要，該處理（Ge%)窗可較小。因為通道的應力水 平與經嵌入之材料相比相對減小，因此在實施例中經嵌入 之材料應具有比約25%至30%更大的Ge百分數，以應用用於 pFET之此結構。在此方法中，沒有獨立的pFET與nFET控制。 圖3說明了根據本發明之nFET裝置中的應力位置。如圖3 中所示，在nFET通道t存在拉伸應力，其中一非鬆弛以^ 區域處於壓縮狀態下《更特定言之，在本發明之結構中， SiGe層45a之晶格結構將與下面的si絕緣層20之晶格結構 匹配。此導致SiGe層45a及周圍區域將處於壓縮應力下。該 等周圍區域將試圖達到平衡狀態，因而導致SiGe層45a上所 形成之蟲晶石夕層60產生拉伸應力。 圖4說明了根據本發明之PFET裝置中的應力位置。如圖4 中所示’在pFET通道中存在壓縮應力，其中一非鬆弛81:(： 區域處於拉伸狀態。更特定言之，在本發明之結構中，Si:c 層40a之晶格結構將與下面之Si絕緣層20之晶格結構匹 配。此導致Si:C層40a及周圍區域將處於拉伸應力下。如 SiGe層所發生的那樣，Si:C層40a的周圍區域將達到平衡狀 態。然而，此導致Si:C層40a上所形成之磊晶Si層60產生壓 縮應力6 在一實行中，在圖1 f之nFET中之蟲晶石夕60中的縱向應力 分量（在電流自源極至汲極的方向上之應力）的較佳範圍為 拉伸值大於100 MPa，同時在pFET之Si通道中較佳為壓縮值 •15· 96246.doc 1327779 大於 100 MPa。 因此，在本發明之結構中，現在在nFET通道中形成拉伸 應力且在pFET通道中形成壓縮應力。在一實行中，亦可在 pFET中形成咼拉伸應力。藉由允許此等應力，可達成高裝 置效能。此外，藉由本發明之處理，可減少製造成本且產 生更高之良率。 儘管已根據實施例來描述了本發明，但是熟習此項技術 者將瞭解，可以附加之申請專利範圍的精神與範疇内的修 改來實踐本發明。舉例而言，可不難將本發明應用於大量 基板。 【圖式簡單說明】 圖la至If表示用以形成根據本發明之裝置的製程； 圖2a至2d表示用以形成根據本發明之裝置的製程； 圖3說明了根據本發明之nFET裝置中的應力位置；及 圖4說明了根據本發明之pFET裝置中的應力位置。 【主要元件符號說明】 10 基板 15 犧牲氧化層15 20 Si層 25 淺溝槽隔離特徵 32 氧化層 35 光阻層 40 通道 40a Si:c層/選擇性Si:c磊晶層 96246.doc 1327779 45 45a 50 55 60 65 65b 70 70b 通道
SiGe層/選擇性SiGe磊晶 硬式遮罩 硬式遮罩 選擇性Si磊晶層 閘極氧化層 閘極多晶發 閘極多晶石夕 閘極多晶碎 96246.doc

Claims (1)

1327779
第093131406號專利申請案 中文申請專利範圍替換本(99年2月） 十、申請專利範圍： 1. 一種製造一半導體結構之方法，其包含以下步驟： 藉由自一基板之一上表面移除材料而在該基板上形成 一 p型場效電晶體（pFET)通道及一 η型場效電晶體（nFET) 通道； 在該pFET通道中提供一具有與該基板之該晶格常數不 同之一晶格常數的第一材料層； 在該nFET通道中提供一具有與該基板之該晶格常數不 同之一晶格常數的第二材料層； 在該pFET通道中之該第一材料層上及該nFET通道中 之該第二材料層上形成一蟲晶半導體層’該蟲晶半導體 層具有一大體上與該基板相同之晶格常數，因此在該 pFET通道與該nFET通道内產生一應力分量。 2. 如請求項1之方法，其中該pFET通道與該nFET通道係同 時形成。 3. 如請求項1之方法，其中該pFET通道與該nFET通道係個 別形成。 4. 如請求項1之方法，其中該第一材料層為SiGe，其具有的 Ge含量比例大於Si約25%。 5. 如請求項4之方法，其中該第一材料層在該大於3 GPa之 磊晶半導體層内產生一拉伸應力。 6. 如請求項1之方法，其中該第二材料層為SiGe。 7. 如請求項6之方法，其中該第二材料層在該nFET通道之磊 晶半導體層内產生了 一拉伸應力。 96246-990206.doc 8. 8. 9. 10. 11. 12. 13. 14. 15. 16. 如：t項1之方法’其中該第-材料層為Si:C。 “項〗之方法，進-步包括以下步驟： 主：磊B曰半導體層上形成一閘極氧化物結構。 月求項1之方法，其中該nFET及該pFET通道之形成包 將該基板之一以層蝕刻成一約為2〇〇人至4〇〇人之深产。 如請求項1之方法，其中： 又 * 5<nFET通道上置放一硬式遮罩，並在該pFET通 道内成長該第-材料層，以形成該第-材料層；及 藉由在該PFET通道上置放一硬式遮罩，並在該卿丁通 道内成長該第二材料層，以形成該第二材料層。 如凊求項1之方法’進-步包含在該基板⑽錢溝槽結構。 如請求項1之方法，其中該第一材料層與該第二材料層成 長為一約100 A至300 A之高度。 如凊求項1之方法，其中該基板係絕緣層上覆矽之一層。 如請求項1之方法，其中該第一材料層與該第二材料層均 為SiGe材料，其具有之Ge百分比大於應用於該pFET的 百分比約25°/。至30%。 一種製造一半導體結構之方法，其包含以下步驟： 藉由触刻一基板之一上表面而形成一 p型場效電晶體 (pFET)通道及一 n型場效電晶體（nFET)通道； 在該pFET通道中提供一具有與該基板之該晶格常數不 同之一晶格常數的第一材料層； 在該nFET通道中提供一具有與該基板之該晶格常數不 同之一晶格常數的第二材料層；及 96246-990206.doc 1327779 在該pFET導道中之該第一材料層上及該nFET通道中 之該第二材料層上形成一磊晶半導體層，該磊晶半導體 層具有一大體上與該基板相同之晶格常數，因此產生一 與該pFET通道中之該第一材料層及該nFET通道中之該 第一材料層的應力分量相反的應力分量。 17. 18. 19. 20. 21. 22. 23. 如請求項16之方法，其中該PFET通道與該nFET通道係同 時形成。 如請求項16之方法，其中該pFET通道與該nFET通道係個 自形成。 如請求項16之方法，其中該第一材料層為Si:C，且該第二 材料層為SiGe。 如請求項19之方法，其中： 該第一材料層在該pFET通道之磊晶半導體層内產生了 一壓縮應力；及 該第二材料層在該nFET通道之磊晶半導體層内產生了 一拉伸應力。 如請求項16之方法，進一步包含以下步驟： 在该蟲晶半導體層上形成一閘極氧化物結構。 如請求項16之方法，其中： 藉由在該nFET通道上置放一硬式遮罩，並在該PFET通 道内成長該第一材料層，以形成該第一材料層；及 藉由在該pFET通道上置放一硬式遮罩，並在該nFET通 道内成長該第二材料層，以形成該第二材料層。 一種半導體結構，其包含： 96246-990206.doc 1327779 » I 一形成於一基板中之P型場效電晶體（pFET)通道； 一形成於該基板中之η型場效電晶體（nFET)通道； 一形成於該基板中之淺溝槽隔離結構； 一位於該pFET通道中並具有—與該基板之一晶格常數 不同之晶格常數的位在該基板之一 Si層上且與該基板之 該Si層實體接觸之第一材料層； 一位於該nFET通道中並具有一與該基板之該以層之該 晶格常數不同之晶格常數的位在該基板之_ Si層上且與 該基板之該Si層實體接觸之第二材料層；及 一形成於該pFET通道之該第一材料層之上且與該 pFET通道之該第一材料層實體接觸並形成於該nFET通 道之該第二材料層之上且與該nFET通道之該第二材料層 實體接觸之磊晶半導體層’該磊晶半導體層具有一大體 上與该基板之該Si層之該晶格常數相同之晶格常數，因此 於該pFET通道與該nFET通道中產生一希望之應力分量。 24.如請求項23之結構’其中該第一材料層為Si:c，且該第二 材料層為SiGe。 25·如請求項23之結構’其中該第一材料層與第二材料層均 為SiGe，於該pFET通道中產生了一大於約3 GPa之應力水 平。 26.如請求項23之結構，其中： 該第一材料層在該pFET通道之該磊晶半導體層内產生 一壓縮應力；及 該第二材料層在該nFET通道之該磊晶半導體層内產生 一拉伸應力。 96246-990206.doc -4- 1327779 丨”年>月“敝)正替換員丨 第093131406號專利申請案 t文圖式替換頁(99年2月） Η*一、圖式：
S71, 〜25 ^w15 广、^10 墨*/3 nFET 45 pFET 广
STI rSOI 35 32 25 15 10 96246-fig-990206.doc 1327779 β年^月/日修(更)正替換買 第093131406號專利申請案 中文圖式替換頁(99年2月） r sn >^25 /20 SOI M 2a 〆 ^25 1 STI SOI nFET
圖2b 96246-fig-990206.doc
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US20050139930A1 (en) 2005-06-30
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US7495291B2 (en) 2009-02-24
WO2005043590A3 (en) 2006-09-21
CN101095211A (zh) 2007-12-26
TW200525765A (en) 2005-08-01
US20050085022A1 (en) 2005-04-21
KR100910902B1 (ko) 2009-08-05
US7037770B2 (en) 2006-05-02
WO2005043590A2 (en) 2005-05-12
EP1676296A4 (en) 2008-08-20

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