JP2007123896A - チップ、fet製造方法(面内剪断応力を加えるための誘電体ストレッサ要素を有するトランジスタ) - Google Patents
チップ、fet製造方法(面内剪断応力を加えるための誘電体ストレッサ要素を有するトランジスタ) Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
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- 125000001475 halogen functional group Chemical group 0.000 description 4
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】活性半導体領域と、いずれもこの活性半導体領域内に配置されたチャネル領域、ソース領域およびドレイン領域を有する電界効果トランジスタ(「FET」)とを含むチップが提供される。このFETは、チャネル領域の長さの方向である縦方向と、チャネル領域の幅の方向である横方向とを有する。水平に延びる上面を有する第1の誘電体ストレッサ要素は、活性半導体領域の北西部分など、活性半導体領域の1つの部分の下に延びる。水平に延びる上面を有する第2の誘電体ストレッサ要素は、活性半導体領域の南東部分など、活性半導体領域の第2の部分の下に延びる。第1および第2の誘電体ストレッサ要素はそれぞれ活性半導体領域と縁を共有し、この縁は上面から遠ざかる方向に延びる。
【選択図】図1
Description
101 基準系の記号
104 活性半導体領域
105 活性半導体領域の主表面
106 浅いトレンチ分離(STI)領域
108 活性半導体領域の西縁
110 活性半導体領域の東縁
112 PFETの縦方向
114 活性半導体領域の北縁
116 活性半導体領域の南縁
118 PFETの横方向
120 ゲート
121 ゲート導体
122 ソース領域
123 誘電体側壁またはスペーサ
124 ドレイン領域
Claims (20)
- 西縁、東縁、北縁および南縁を有し、前記西縁と前記東縁との間の方向である縦方向と、前記北縁と前記南縁との間の方向である横方向とを有する活性半導体領域と、
いずれも前記活性半導体領域の中に配置されたチャネル領域、ソース領域およびドレイン領域を有し、前記チャネル領域の長さが前記縦方向に配置され、前記チャネル領域の幅が前記横方向に配置された電界効果トランジスタ(「FET」)と、
前記活性半導体領域の前記北縁と前記西縁の間の北西部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第1の誘電体ストレッサ要素と、
前記活性半導体領域の前記南縁と前記東縁の間の南東部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第2の誘電体ストレッサ要素と
を含み、
前記第1の誘電体ストレッサ要素が、第1の方向の第1の応力を前記チャネル領域に加え、前記第2の誘電体ストレッサ要素が、前記第1の方向とは反対の第2の方向の第2の応力を前記チャネル領域に加え、その結果、前記第1の応力と前記第2の応力が互いに協力して、増大された剪断応力を前記チャネル領域に加える
チップ。 - 前記第1の誘電体ストレッサ要素が前記第1の方向の圧縮応力を加え、前記第2の誘電体ストレッサ要素が前記第2の方向の圧縮応力を加える、請求項1に記載のチップ。
- 前記第1の誘電体ストレッサ要素が前記第1の方向の引張応力を加え、前記第2の誘電体ストレッサ要素が前記第2の方向の引張応力を加える、請求項1に記載のチップ。
- 前記活性半導体領域の前記南縁と前記西縁の間の南西部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第3の誘電体ストレッサ要素と、
前記活性半導体領域の前記北縁と前記東縁の間の北東部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第4の誘電体ストレッサ要素と
をさらに含み、
前記第3の誘電体ストレッサ要素が、前記第1および第2の方向のうちの一方の方向の剪断応力を前記チャネル領域に加え、前記第4の誘電体ストレッサ要素が、前記第1および第2の方向のうちの前記一方の方向とは逆の前記第1および第2の方向のうちのもう一方の方向の剪断応力を前記チャネル領域に加える、
請求項2に記載のチップ。 - 前記第3の誘電体ストレッサ要素が、前記第1および第2の方向のうちの前記一方の方向の引張応力を加え、前記第4の誘電体ストレッサ要素が、前記第1および第2の方向のうちの前記もう一方の方向の引張応力を加える、請求項4に記載のチップ。
- 前記活性半導体領域の前記南縁と前記西縁の間の南西部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第3の誘電体ストレッサ要素と、
前記活性半導体領域の前記北縁と前記東縁の間の北東部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第4の誘電体ストレッサ要素と
をさらに含み、
前記第3の誘電体ストレッサ要素が、前記第1および第2の方向のうちの一方の方向の剪断応力を前記チャネル領域に加え、前記第4の誘電体ストレッサ要素が、前記一方の方向とは逆の前記第1および第2の方向のうちのもう一方の方向の剪断応力を前記チャネル領域に加える、
請求項3に記載のチップ。 - 前記第3の誘電体ストレッサ要素が、前記第1および第2の方向のうちの前記一方の方向の圧縮応力を加え、前記第4の誘電体ストレッサ要素が、前記第1および第2の方向のうちの前記もう一方の方向の圧縮応力を加える、請求項6に記載のチップ。
- 前記第1の誘電体ストレッサ要素がトレンチ分離領域と接触し、前記トレンチ分離領域が、前記活性半導体領域と、前記北縁、前記東縁、前記南縁および前記西縁のうちの少なくとも1つを共有する、請求項1に記載のチップ。
- 前記第1および第2の誘電体ストレッサ要素の前記縁が、前記第1および第2の誘電体ストレッサ要素の前記上面から遠ざかる少なくとも概ね垂直な方向に延びる、請求項1に記載のチップ。
- 前記FETがさらに、前記チャネル領域の上に導電性部分を有するゲート導体を含み、前記導電性部分が、垂直方向を向いた第1のゲート縁と、前記第1のゲート縁の反対側の垂直方向を向いた第2のゲート縁とを有し、前記第1の誘電体ストレッサ要素の前記縁が前記第1のゲート縁と整列し、前記第2の誘電体ストレッサ要素の前記縁が前記第2のゲート縁と整列した、請求項1に記載のチップ。
- 前記活性半導体領域の前記北縁、前記東縁、前記南縁および前記西縁がそれぞれ、前記トレンチ分離領域との間で共有され、前記第1の誘電体ストレッサ要素が、前記北縁および前記西縁と、それらの全長よりも実質的に短い長さにわたって接触し、前記第2の誘電体ストレッサ要素が、前記南縁および前記東縁と、それらの全長よりも実質的に短い長さにわたって接触した、請求項8に記載のチップ。
- 西縁、東縁、北縁および南縁を有し、前記西縁と前記東縁との間の方向である縦方向と、前記北縁と前記南縁の間の方向である横方向とを有する活性半導体領域と、
いずれも前記活性半導体領域の中に配置されたチャネル領域、ソース領域およびドレイン領域を有し、前記チャネル領域の長さが前記縦方向に配置され、前記チャネル領域の幅が前記横方向に配置された電界効果トランジスタ(「FET」)と、
前記活性半導体領域の前記南縁と前記西縁の間の南西部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第1の誘電体ストレッサ要素と、
前記活性半導体領域の前記北縁と前記東縁の間の北東部分の下にだけあり、水平に延びる上面を有し、前記活性半導体領域と縁を共有し、前記縁が前記上面から遠ざかる方向に延びる第2の誘電体ストレッサ要素と
を含み、
前記第1の誘電体ストレッサ要素が、第1の方向の第1の応力を前記チャネル領域に加え、前記第2の誘電体ストレッサ要素が、前記第1の方向とは反対の第2の方向の第2の応力を前記チャネル領域に加え、その結果、前記第1の応力と第2の応力が互いに協力して、増大された剪断応力を前記チャネル領域に加える
チップ。 - 前記第1の誘電体ストレッサ要素が前記第1の方向の圧縮応力を加え、前記第2の誘電体ストレッサ要素が前記第2の方向の圧縮応力を加える、請求項12に記載のチップ。
- 前記第1の誘電体ストレッサ要素が前記第1の方向の引張応力を加え、前記第2の誘電体ストレッサ要素が前記第2の方向の引張応力を加える、請求項12に記載のチップ。
- 半導体基板内に、第1の埋込み多孔質半導体領域および第2の埋込み多孔質半導体領域を形成するステップであって、前記第1および第2の埋込み多孔質半導体領域が前記基板の上部半導体部分の下に配置され、前記第1および第2の埋込み多孔質半導体領域が多数のボイドと、前記上部半導体部分の密度よりも実質的に小さい密度とを有するステップと、
前記第1および第2の埋込み多孔質半導体領域を酸化して、第1の誘電体ストレッサ要素および第2の誘電体ストレッサ要素を形成するステップと、
いずれも前記上部半導体部分内に延びるチャネル領域、ソース領域およびドレイン領域を有し、前記第1の誘電体ストレッサ要素の上に部分的に重なり、前記第2の誘電体ストレッサ要素の上に部分的に重なる電界効果トランジスタ(「FET」)を形成するステップと
を含み、
前記第1の誘電体ストレッサ要素が、第1の方向の第1の応力を前記チャネル領域に加え、前記第2の誘電体ストレッサ要素が、前記第1の方向とは反対の第2の方向の第2の応力を前記チャネル領域に加え、その結果、前記第1の応力と第2の応力が互いに協力して、増大された剪断応力を前記チャネル領域に加える
電界効果トランジスタ(「FET」)デバイスの製造方法。 - 前記第1および第2の埋込み多孔質半導体領域を形成する前記ステップが、マスクの第1および第2の開口を通してそれぞれ前記基板の第1および第2の領域にドーパントを注入するステップと、前記基板を陽極処理プロセスに暴露するステップとを含む、請求項15に記載のFET製造方法。
- 前記第1および第2の埋込み多孔質半導体領域を形成する前記ステップがさらに、前記第1および第2の埋込み多孔質半導体領域内の前記ドーパントの濃度を低減させるためのプリベーク・プロセスを含む、請求項16に記載のFET製造方法。
- 前記ドーパントを注入する前記ステップが、前記第1および第2の領域が前記基板の主表面に露出している間に前記第1および第2の領域に前記ドーパントを注入するように実行され、前記方法がさらに、前記基板に前記陽極処理プロセスを施す前に、エピタキシャル層を成長させて、前記上部半導体部分を形成するステップを含む、請求項16に記載のFET製造方法。
- 前記注入ステップが実行されるときに、前記第1および第2の領域が前記上部半導体部分の下に配置されている、請求項15に記載のFET製造方法。
- 前記第1および第2の誘電体ストレッサ要素の縁が、前記注入ステップ中にフォトリソグラフィによって決定される、請求項16に記載のFET製造方法。
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JP2007207992A (ja) * | 2006-02-01 | 2007-08-16 | Toshiba Corp | 半導体装置及びその製造方法 |
US9070881B2 (en) | 2012-10-02 | 2015-06-30 | Samsung Electronics Co., Ltd. | Method of manufacturing an organic semiconductor thin film |
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US7364997B2 (en) * | 2005-07-07 | 2008-04-29 | Micron Technology, Inc. | Methods of forming integrated circuitry and methods of forming local interconnects |
US7476938B2 (en) * | 2005-11-21 | 2009-01-13 | International Business Machines Corporation | Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress |
US7462916B2 (en) * | 2006-07-19 | 2008-12-09 | International Business Machines Corporation | Semiconductor devices having torsional stresses |
US7615840B2 (en) * | 2007-06-21 | 2009-11-10 | Infineon Technologies Ag | Device performance improvement using flowfill as material for isolation structures |
US8216904B2 (en) * | 2008-12-31 | 2012-07-10 | St Microelectronics, Inc. | Strained transistor and method for forming the same |
US8415748B2 (en) | 2010-04-23 | 2013-04-09 | International Business Machines Corporation | Use of epitaxial Ni silicide |
US8962430B2 (en) | 2013-05-31 | 2015-02-24 | Stmicroelectronics, Inc. | Method for the formation of a protective dual liner for a shallow trench isolation structure |
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US6717216B1 (en) | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
US6974981B2 (en) | 2002-12-12 | 2005-12-13 | International Business Machines Corporation | Isolation structures for imposing stress patterns |
US7566482B2 (en) | 2003-09-30 | 2009-07-28 | International Business Machines Corporation | SOI by oxidation of porous silicon |
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