TWI324387B - Resistor random access memory cell device - Google Patents

Resistor random access memory cell device Download PDF

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TWI324387B
TWI324387B TW096100853A TW96100853A TWI324387B TW I324387 B TWI324387 B TW I324387B TW 096100853 A TW096100853 A TW 096100853A TW 96100853 A TW96100853 A TW 96100853A TW I324387 B TWI324387 B TW I324387B
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memory cell
cell device
memory
layer
phase change
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TW200830535A (en
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Erh Kun Lai
Chia Hua Ho
Kuang Yeu Hsieh
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Macronix Int Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of the switching material, e.g. post-treatment, doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors

Description

1324387 九、發明說明： i 【發明所屬之技術領域】 本發明係有關於以相變化記憶材料為基礎之高密度記 憶裝置，以及用以製造此等裝置的方法，其中相變化記憶 材料包括硫屬化物材料與其他材料。 【先前技術】 • 相變化記憶材料係廣泛地用於讀寫光碟中。這些材料 包括有至少兩種固態相，包括如一大部分為非晶態之固態 相，以及一大體上為結晶態之固態相。雷射脈衝係用於讀 寫光碟片中，以在二種相中切換，並讀取此種材料於相變 化之後的光學性質。 如硫屬化物及類似材料之此等相變化記憶材料，可藉 由施加其幅度適用於積體電路中之電流，而致使晶相變 化。大致非晶態之特徵係其電阻高於結晶態，此電阻值可 輕易測量得到而用以作為指示。這種特性則引發使用可程 • 式化電阻材料以形成非揮發性記憶體電路等興趣，此電路 可用於隨機存取讀寫。 從非晶態轉變至結晶態一般係為一低電流步驟。從結 晶態轉變至非晶態（以下指稱為重置（reset))—般係為一高 電流步驟，其包括一短暫的高電流密度脈衝以熔化或破壞 結晶結構，其後此相變化材料會快速冷卻，抑制相變化的 過程，使得至少部份相變化結構得以維持在非晶態。理想 狀態下，致使相變化材料從結晶態轉變至非晶態之重置電 流幅度應越低越好。欲降低重置所需的重置電流幅度，可 1324387 藉由減低在記憶體中的相變化材料元件的尺寸、以及減少 電極與此相變化材料之接觸面積而達成，因此可針對此相 變化材料元件施加較小的絕對電流值而達成較高的電流密 度。 此領域發展的一種方法係致力於在一積體電路結構上 形成微小孔洞’並使用微量可程式化之電阻材料填充這些 微小孔洞。致力於此等微小孔洞的專利包括：於1997年 11月11日公告之美.國專利第5,68 7,112號“Multibit Single Cell Memory Element Having Tapered Contact”、發明人為 Ovshinky;於1998年8月4日公告之美國專利第5,789,277 號 “Method 〇f Making Chalogenide [sic] Memory Device”、發明人為zahorik等；於2000年11月21日公告 之美國專利第 6，150,253 號 “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same”、發明人為 Doan 等。 當以非常微小尺寸製造此等裝置且製程變數必須符合 大尺寸記憶裝置所要求的嚴格製程規範時，會遭遇到問 φ 題。因此，較佳係能提供一種記憶細胞結構與製造此等結 構的方法，其具有微小尺寸與低重置電流。 【發明内容】 本發明之一目的係有關於相變化記憶裝置，其包括一 記憶材料，係可透過能量之應用而在電性狀態間交替。此 記憶細胞裝置具有一底電極與一頂電極，一記憶材料栓塞 接觸至底電極，以及一杯狀導電構件其具有一周緣接觸至 頂電極且在底部具有一開口接觸至記憶材料。藉此，記憶 細胞中的導電路徑係從頂電極穿過杯狀導電構件，並穿過 C S ) 6 1324387 相變化材料栓塞到達底電極。 本發明之一目的，係提供—記憶細胞裝置， 底電極與-頂電極’-記憶材料栓塞接觸至底電極，以 -杯狀導電構件其具有-周緣接觸至頂f極且 一開口接觸至記憶材料。 -、有
本發明之另一目的，係提供製造一記憶細胞裝置 法，藉由提供一基板其在一表面具有一介金屬介電質形 成-第-電極層於介金屬介電質之上，形成—電絕緣層^ 第一電極層之上，形成一停止層於電絕緣層之上，以及圖 案化各層以形成島狀底電極，每個島狀底電極包括一電ς 緣元件與一停止元件；沈積一填充材料於介金屬介電及 此等島狀底電極之上；移除填充材科至停止元件；移除停 止元件，形成工/同，空洞係由分隔層之一側壁與電纟'邑 元件之一外露表面所定義；沈積一導電材料以形成一導雷 薄膜於填充材料、分隔層之侧壁與電絕緣元件之外露表 ，上；沈積一電絕緣襯底材料於導電薄膜之上；進行二 等向性蝕刻，以從分隔層之表面移除絕緣襯底材料及 薄膜，並形成一開口穿過絕緣襯底材料、且穿過導電 沈積-相變化記憶材料於開口中；形成—氧化物覆蓋芦、於 相變化記憶材料之上；以及形成一頂電極於氧化 i芦 以及分隔層之表面上等㈣達成。 增 本發明之方法係直接採用自對準製裎，且可改變其大 /In 〇 ’、 在所生成的記憶細胞建構下，記憶材料係與底 性接觸。一導電構件包括具有—周緣之—侧壁、以及帶有 一開口之一底部。記憶材料接觸底電極並於其開口接觸導 電構件；以及杯狀構件之周緣接觸頂電極。 1324387
【實施方式】 、後續之發明說明將錢I敎結構實施例與方法 甚，本發明之銘，樣托dfc ' J 後躓心W 食狀芏特定結構實施例與方法。 以 例 理解的是，本發明之範疇並非限制於特定所 ，且本發明可利用其他特徵、元件、方法與二 t 實施。在各實施例中的類似元件將以類似標仃 貫參照第1圖’其大體上顯示本發明之 細胞綠構1G。記憶細胞結構1G包括底電極12與頂= 14。電絕緣詹Μ覆蓋於底電極12之上 電 包括形成於絕緣層16上的底部27以及具有—周導 頂電極！4的側^部分29 °電絕緣襯底17形成於底部 之上炎位於杯狀導電襯底is的側壁部分29。相變化° 材料栓塞2〇係穿，絕緣襯底17、杯狀導電襯底18的底； 27以及絕緣襯底Π，形成於―開口内。相 料= 塞20接觸底電極12之表面21的一部分幻化记匕材枓栓 27於開口 28接觸杯狀導電襯底18。電^ = 絕緣襯底17内以及頂電極14盥相變 s b異滿 間。底電極Π、絕緣層14以及、塞20間的空 士士粗h堂on、蒂士 h 久孙狀導電觀底18與相變化 =栓塞20遇有杯狀減⑽包括的其他特徵 雷包圍。填充層U及底電極12係㈣ 狀ί電18 4係位於填充層11上，並接觸杯 側壁的周13 °因此’頂電極係在杯狀概底之 > * ^αλΙ.接杯狀襯底；相變化材料栓塞係於底電極 底却πσ卩分電連接底電極；以及杯狀襯底係於杯狀襯 導雷故二Γ1 口處電連接相變化材料栓塞。如箭頭19略示， 材％從頂電極14穿過杯狀導電襯底18、穿過相變化 才料栓塞20到達底電極12。 1324387 本發明之記憶細胞結構提供許多優勢特徵，如第1圖 所示。相變化材料栓塞與底電極有一小區域的接觸。從頂 電極到相變化材料栓塞之電流（利用杯狀襯底）係偏限於 杯狀襯底之底部接觸相變化材料之開口的一小區域。 第10圖係一記憶陣列的示意圖，記憶陣列可依據在此 所述之方法實施。在第10圖之示意中，共同源極線128、 字元線123以及字元線124係朝Y方向大致呈平行排列。 位元線141及142係朝X方向大致呈平行排列。因此，方 塊145中的Y解碼器與字元線驅動器耦接字元線123、 124。方塊146中的X解碼器與一組感測放大器耦接位元 線141及142。共同源極線128耦接存取電晶體150、15卜 152及153之源極端。存取電晶體150之閘極耦接字元線 123。存取電晶體151之閘極耦接字元線124。存取電晶體 152之閘極耦接字元線123。存取電晶體153之閘極耦接字 元線124。存取電晶體150之汲極耦接記憶細胞135之底 電極構件132，記憶細胞135具有頂電極構件134。頂電極 構件134耦接位元線141。類似地，存取電晶體151之汲 極耦接記憶細胞136之底電極構件133，記憶細胞136具 有頂電極構件137。頂電極構件137耦接位元線141。存取 電晶體152及153亦於位元線142耦接對應的記憶細胞。 從示範配置可知，共用源極線128係由兩列記憶細胞所分 享，其中一列係以γ方向排列，如圖所示。在其他實施例 中，存取電晶體可由二級管或控制陣列中的電流流向某些 特定裝置以讀寫資料之其他結構代替之。 記憶細胞裝置的實施例，包括記憶材料20的相變化記 憶材料，其相變化記憶材料包括硫屬化物材料與其他材 料。相變化合金能在此細胞主動通道區域内依其位置順序 1324387 於材料為一般非晶狀態之第一結構狀態與為一般結晶固體 狀態之第二結構狀態之間切換。這些材料至少為雙穩定 態。此詞彙「非晶」係用以指稱一相對較無次序之結構， 其較之一單晶更無次序性，而帶有可偵測之特徵如較之結 晶態更高之電阻值。此詞彙「結晶態」係用以指稱一相對 較有次序之結構，其較之非晶態更有次序，因此包括有可 偵測的特徵例如比非晶態更低的電阻值。典型地，相變化 材料可電切換至完全結晶態與完全非晶態之間所有可偵測 的不同狀態。其他受到非晶態與結晶態之改變而影響之材 料特中包括，原子次序、自由電子密度、以及活化能。此 材料可切換成為不同的固態、或可切換成為由兩種以上固 態所形成之混合物，提供從非晶態至結晶態之間的灰階部 分。此材料中的電性質亦可能隨之改變。 相變化合金可藉由施加一電脈衝而從一種相態切換至 另一相態。先前觀察指出，一較短、較大幅度的脈衝傾向 於將相變化材料的相態改變成大體為非晶態。一較長、較 低幅度的脈衝傾向於將相變化材料的相態改變成大體為結 晶態。在較短、較大幅度脈衝中的能量夠大，因此足以破 壞結晶結構的鍵結，同時夠短因此可以防止原子再次排列 成結晶態。在沒有不適當實驗的情形下，可以利用實驗方 法決定特別適用於一特定相變化合金的適當脈衝量變曲 線。在本發明中，相變化材料係指GST，且需要知道的是， 本發明亦可使用其他類形的相變化材料。適用於實施在此 所述之記憶裝置之材料為Ge2Sb2Te5。 參照第1圖，如第10圖所述之存取電路可以許多方法 配置，以接觸第一電極12與第二電極14，供控制記憶細 胞的操作，使相變化材料20得以程式化設定為可利用記憶 1料反向實作之兩種固態相的其中一種。舉例言之，利用 =化物材料為主的相變化材料，可將記憶細胞設定為較 :電阻狀態以及較低電阻狀態，其中在較高電阻狀態下電 的導橋的至少—部料非晶態，而在較低電阻狀 ii:路徑中的導橋的至少一部份是結晶態。舉例而 " 適當之較短、尚振幅之電脈衝的應用將導致相變 不 化材料20局部變成大體上為非晶態，如第1圖中的22所 ΤΓΓ· η "
纪憶細胞裝置1〇的製造將參考第2A_9c圖作描述， 八中一不範製程的許多階段係以平面圖（2a、3a 四個記憶細胞之陣列）以及剖面圖（2B、3B等；顯示L個 。存取電路係位於具有—表面介金屬介電 “於上。適用於底電極的導電材料的導電層係 ^於”金屬介電質層221的表面，適用於底電極 :料：,有金屬或以金屬為主或非金屬的材料，比方銅； 及好比氮化鈦（™)、氮氧化鈦（Τ〇η)等以 鈦為主的材料；鈕（Ta)及例如氮化鈕（Tan)之以鈕
的材料；多晶石夕、例如石夕化鎢（WSix)之以鶴為主的材料； 以及針對低熱傳導電極，例如LNO (LaNi〇3)和LSM〇 (LaSrMn〇3)等材料；如氧化物（比方二氧化的電絕 緣層係沈積於底電極層之上；以及好比氮氧切或氮化石夕 之材料的蝕刻停止層，係沈積於絕緣層上。 底電極層可具有例如介於約200埃到約3〇〇〇埃之間的 厚度，通㊉在約500埃。舉例言之，氧化物絕緣層可具 介於約50㈣2000埃之間的厚度，=氧化石夕層通常&約 200埃舉例說明，氮化砍餘刻停止層可具有介於約 埃到3000埃之間的厚度，通常在約 Joi)埃。這‘層接著 IJ24387 被圖樣化並被關，_成底電 每個底電極堆疊或島狀底電極21〇勺"" A島狀底電極21〇, 層（氧化物，比方二氧化矽）216以^底電極212、絕緣 第2A、2B圖中的範例所示。戶2停止層230 ’如 填充層311 (參考下圖）之材& =據絕緣層216及 常適用於層230之材料對於絕緣層的犧牲層；通 性且對層311有較高的CMp選擇性 ^車父向的餘刻選擇 料大多適用於絕緣層材料及導雷展。胃匕，多晶矽或鎢材 中，所示之底電極堆疊已被圖樣：為一；圖) 亦可藉由不同配置的圖樣而形成 t島，其他形狀 10圖所緣示之交叉點的配置（位元綠/字元 =亦可以第 接著，將填充材料沈積於第2入及2 _ )實^。 將此材料移除到钮刻停止層230的 _的結構上’並 (或分隔層）3U。適當的填充材料包括^形成一填充層 二氧化石夕、BPSG、㈣低介電常4數H氧化物^比 擇性之其他材料)，以及氮化物（好比氮化石夕、； 或對層216具有較高的刪擇性、 底電有較1^的CMP率之其他材料）。填充材料圍繞 較佳地提供較良好的電與熱絕緣，為記憶 式胞&供熱與電隔離。填充材料可利用化學機械研磨方法 3歹如回餘，使之平面化，而债測到餘刻停止層230表面 =外露時，即停止研磨或蝕刻。填充材料可透過例如高密 又電漿化學氣相沈積作沈積，在此製程中钱刻停止層會受 到保護。適當的蝕刻停止材料包括例如氮氧化矽（si〇N)、 鶴（W )、多晶石夕、或對絕緣層216有較高的钱刻選擇性以 及對層311有較高CMP率的其他材料；蝕刻停止層具有介 於約200埃到約3000埃之間的厚度，通常約1〇〇〇埃。 12 1324387 接著，触刻停止層可以透過例如選擇性離子#刻或濕 蝕刻（「浸沾」）的方式做移除。第4A及4B圖顯示其結構 之結果。分隔層311包圍底電極212與絕緣（氧化）層216， 大體上如先前圖式所示。只是目前絕緣（氧化）層216的 表面421外露於分隔層之周壁421所定義之空洞422的底 部。 接著，導電材料沈積於第4A、4B圖所示的結構上， 在分隔層上表面、絕緣（氧化）層216表面427、以及周 壁421表面形成導電薄膜518。接著，電絕緣材料沈積於 此結構上，在導電薄膜518的表面上形成襯底層517。第 5A及5B圖顯示這些步驟的結果。襯底層的厚度不會填滿 空洞的整個空間，而會留下一個空隙522。適用於導電薄 膜之材料包括例如氮化鈦、鈦、鎢、銅、多晶石夕；由於較 薄的氮化鈦比較有效，因此氮化鈦較佳作為襯底材料。適 用於絕緣（氧化）襯底層的材料包括例如氮氧化矽（SiON) 及氮化矽（SiN)。 接著進行非等向性蝕刻，從分隔層的表面移除絕緣襯 底材料及導電薄膜材'料，以及蝕刻穿過空洞底部的絕緣（氧 化）襯底材料以及導電薄膜。如第6A、6B圖所示，這導 致導電薄膜518形成杯狀導電襯底18，此亦形成穿過底電 極12之開口 622，並外露許多特徵，其包括：分隔層311 的表面512、杯狀襯底18之周緣13、底電極12表面21的 一小區域23、以及穿過杯狀襯底18之底部27的開口 28。 絕緣襯底材料的一部份留在底部27並在杯狀襯底18的侧 壁部分29内。 適當的非等向性蝕刻可包括許多步驟，一範例包括以 下三個步驟。在此範例中，絕緣襯底517 ( 17)為SiN，導 13 1324387 電薄膜518 ( 18)為如銅的金屬，以及絕緣層216 ( 16)為 氧化矽。在第一步驟中，對於SiN，利用例如80-200W的 高底功率以及比方CH3F或CHF3化合物或其混合物，選 擇性地與氬、氮及氧等其中之一、或兩個或所有之混合物 組合，進行反應性離子蝕刻（RIE)。在第二步驟中，係對 於金屬進行含氯的餘刻，例如利用BC13或C12的化合物或 其混合物，選擇性與氬或氮其中之一、或其混合物組合， 進行RIE。如同第一步驟，在第二步驟中底功率的強度足 夠進行非等向性蝕刻，例如就一 8吋晶圓製程而言係利用 高於100W之底功率。第二步驟蝕刻可透過時間控制或利 用終點偵測而停止；關於終點偵測，C-N信號降低可用以 偵測TiN蝕刻製程。在第三步驟中，對於Si02，利用例如 C4F8或CF 4或CHF3或C4F6化合物或其一或多個混合 物，選擇性與氧或氬或其混合物組合，進行RIE。第三層 (在此為Si02)對第一層（在此為SiN)的選擇性為高選 擇性，以避免在第三蝕刻步驟期間毁損SiN層；蝕刻選擇 性可大於例如約10。蝕刻步驟的參數可以通常之設定而做 調整或協調，以取得最佳性能並最佳化結果蝕刻的實體外 觀。第二及第三步驟之間可進行氧原子電漿剝除，以在空 洞内移除聚合的殘留物。選擇性地，在此三個步驟的每一 步驟之後以及習知氧原子電漿剝除之後，可進行其他的乾 式剝除。 接著，相變化記憶材料沈積於第6A、6B圖所示的結 構上，利用例如回触將沈積材料的上部分移除，以在開口 622的底部留下相變化材料栓塞20,如第7A及7B圖所示。 相變化材料可為GexSbyTez (—種「GST」）化學式的硫屬 化物’其中X = 0-5 ; y = 0-5 ;以及z = 0-10 ’例如其x:y:z = 2的2=Γ雜相變化材料可為一種GST，例如摻雜n
Ti ^GST: 這此材料“用氮、[氛或其類似者或 謂論圍t反應氣體，在介於約1 mtGrr到約 相沈積濺鍍下’透過物理氣 ^ . οσ 徑濺鍍作沈積。利用具有深寬比約1比5 =二或利用介於約10 乂到約1000 乂的範圍内（例 哭ώ ηρ到、歲百伏特）施加DC偏壓、或同時利用準直 隹，、，可改進填充性能。沈積之後，硫屬化物材 产US、“改進結晶態。後沈積退火可在真空或氮環 兄，〉皿又；丨於約l〇(TC到約400。〇的範圍内，在少於3〇 鐘内完成。 刀 石瓜屬化物栓塞的厚度係根據細胞結構的設計而改變。 士致上具有厚度大於約8 nm的硫化物栓塞可顯示相 ;穩定電阻態的特性。沈積的硫化物材料可利用習知金屬 ，刻技術作回蝕’即利用例如C12或CF4化合物或其混 合物，選擇性與氬魏或魏合物之組合騎·; f除空洞外的⑽’需要進行非等向性GST_。咖ί J額外的底功率’例如4〇_1〇〇w，形成第7Β圖所示的結 構。終點偵測可用以停止GST餘刻。 U在利=鍍=沈積記憶材料時，情況可能包括例如 ί t =二Λ的ί合物);若只使用氬氣，標的可能 Λ氮氣時，標的可能是Ν2-㈣Te。 产的：觸回相ί化·v t持相變化材料與杯狀襯底在開口 28 處的接觸。相變化魏㈣錄 並在開口28接觸杯狀導電薄膜。检塞二在=:底 1324387 部，而栓塞（包括栓塞與底電極的接觸區23)的形狀及大 小係由開口 622的底部之形狀及大小與回蝕後的栓塞之高 度定義之。 接著，氧化材料（例如二氧化矽）沈積於第7A、7B 圖的結構上，填充開口 622的一部份中栓塞20上所剩餘的 空間，而氧化材料被平面化以形成覆蓋氧化層26。 接者*適合作頂電極的導電材料沈積在第8A、8B圖 的結構上，並被圖樣化以在記憶細胞構件上形成頂電極， 如第9A、9B及9C所示，此導電材料可為金屬或以金屬為 主或非金屬材料，例如銅；铭；鈦（Ti)和比方氣化鈦（TiN )、 氮氧化鈦（TiON)等以鈦為主的金屬；鈕（Ta)及例如氮 化鈕（TaN)之以组為主的材料；多晶矽、如矽化鎢（WSix) 之以鶴為主的材料，以及有關低熱傳導電極’例如LNO (LaNi03)和LSMO (LaSrMn03)。頂電極可被圖樣成島 狀，如第9A圖之範例所示，或線形（帶形線或位元線）， 如第9C圖之範例所示。頂電極可具有例如介於約200埃到 約5000埃之間的厚度，通常在約2000埃。 第9B圖顯示形成的記憶細胞裝置，以標記表示某些特 徵之尺寸。大致上本發明所製造的記憶細胞中其特徵的剖 面形狀係由分隔層中之空洞的形狀而定義，而分隔層中之 空洞的形狀可根據記憶堆疊或島的形狀定義之。類似地， 相變化材料栓塞的形狀及大小係由非等向性蝕刻所形成的 開口之大小以及相變化材料回蝕的程度定義之。在記憶細 胞的許多特徵的示範實施例中，顯示有許多圓形剖面（在 介金屬介電質表面的平面上），但需要知道的是其他的剖面 形狀也可使用。第9B圖以範例顯示某些可稱做「寬度」的 尺寸，在特徵是圓形的情況下，這個尺寸是指其直徑而言。 16 1324387 、 穿過分隔層的空洞之寬度92可在介於約50 nm到約 400 nm的範圍之間，通常約為1 〇〇 nm。杯狀導電薄膜的側 壁部分之厚度94可在約25埃到約200埃的範圍之内，通 常約為50埃，而杯狀薄膜之底部厚度95可在約25埃到 約200埃的範圍之内，通常約為5〇埃。栓塞與底電極接觸 的區域之寬度98可在約2〇 nm到約260 nm的範圍之内， 通常約為70 nm，提供介於約2〇 nm到約26〇 nm的範圍内 的接觸區域，通常約70 nm。栓塞的高度99係根據杯狀導 電薄膜的底部厚度95與在底電極的接觸區域間絕緣氧化 物之厚度等其他因素而不同；栓塞的高度99可在介於約 2〇nm到約lOOrnn的範圍内，通常約為3〇nm。 、' 記憶細胞裝置10的實施例，包括了記憶材料2〇所使 用的相變化記憶材料，包括硫屬化物材料與其他材料。硫 屬化物包括下列四元素之任一者：氧（〇)、硫（8)、硒（Se)、 以及碲（Te)，形成元素週期表上第VI族的部分。硫屬化 物^括將一硫屬元素與一更為正電性之元素或自由基結合 而付石瓜屬化合物合金包括將硫屬化合物與其他物質如過 φ渡金屬等結合。一硫屬化合物合金通常包括一個以上選自 兀素週期表第六攔的元素，例如鍺（Ge)以及錫（Sn)。 通常，硫屬化合物合金包括下列元素中一個以上的複合 物·’銻（Sb)、鎵（Ga)、銦（in)、以及銀（Ag)。許多以 相變化為基礎之記憶材料已經被描述於技術文件中，包括 下列合金：鎵/銻、銦/銻、銦/栖、銻/碲、鍺/碲、鍺/銻/碲、 銦/錄/碲、鎵/硒/碲、錫/錄/碲、銦/録/錯、銀/銦/録/碲、鍺 /錫/錄/碲、錯/錄/砸/碲、以及蹄/鍺/錄/硫。在錯/録/碲合金 豕族中，可以嘗試大範圍的合金成分。此成分可以下列特 徵式表示：TeaGebSblOO-(a+b)。一位研究員描述了最有用 C S ) 17 1324387 的合金係為，在沈積材料中所包括之平均碲濃度係遠低於 70%，典型地係低於60%，並在一般型態合金中的碲含量 範圍從最低23%至最高58%，且最佳係介於48%至58%之 碑含量。鍺的濃度係高於約5%，且其在材料中的平均範圍 係從最低8%至最高30%，一般係低於50%。最佳地，鍺的 濃度範圍係介於8%至40%。在此成分中所剩下的主要成分 則為錄’上述百分比是指所有組成元素的原子總計為1 〇〇0/〇 的原子百分比。（Ovshinky ‘112專利，欄10〜11 )由另一研 究者所評估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及
GeSb4Te7。（ Noboru Yamada，"Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording，，， SPIE v.3109, pp. 28-37(1997))更一般地，過渡金屬如鉻 (Cr)、鐵(Fe)、鎳（Ni)、銳(Nb)、鈀(Pd)、銘（Pt)、以及上述 之混合物或合金’可與鍺/銻/碲結合以形成一相變化合金其 包括有可程式化的電阻性質。可使用的記憶材料的特殊範 例，係如Ovshinsky ‘112專利中欄11-13所述，其範例在 此係列入參考。 本發明係參照至相變化材料而說明。然而，亦可使用 其他s己憶材料.（有時稱為可程式化材料）。如本發明中所使 用者’記憶材料係為其電氣性質如電阻等，可以藉由施加 能量而改變者。此改變可為階梯性改變或一連續性改變， 或為二者的組合。可使用於本發明其他實施例中的其他可 程式化電阻記憶材料，包括摻雜N2之GST、GexSby、或 其他以不同結晶態轉換來決定電阻之物質；prxCayMn03、 PrSrMnO、ZrOx、或其他利用電脈衝以改變電阻狀態的材 料； 7,7,8,8-tetracyanoquinodimethane (TCNQ)、 methanofullerene 6,6-phenyl C61-butyric acid methyl ester 1324387 (PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、 以其他物質摻雜之TCNQ、或任何其他聚合物材料其包括 有以一電脈衝而控制之雙穩定或多穩定電阻態。可程式化 電阻記憶材料的其他範例，包括GeSbTe、GeSb、NiO、
Nb-SrTi03、Ag-GeTe、PrCaMnO、ZnO、Nb2〇5、Cr-SrTi03。 關於相變化隨機存取記憶裝置的製造、構件材料、使 ^及操作請參考2005年6月17日申請、標題為「薄膜熔 化隨機存取記憶體及其製造方法」、巾請案號為 ，〇67的美國專利案，律師登錄號為Μχΐ(： 1621]。 本發明之間亦包括其他實施例。 【圖式簡單說明】 面圖第1圖麵示本發明之—實施例的記憶細胞裝置之剖 於介㈣分麟示—帶圖樣之底電極堆疊位 電極、氧=質之表面的平面及剖面圖，其中堆疊包括底 虱化物、以及氮化矽層。 2Β圖第所分別繪示沈積與研磨如第2Α及第 ^ 4δ且 真充層之結果的平面及剖面圖。 果之平面圖係分別繪示從堆疊㈣氮化㈣之結 4B圖之結圖係分別繪示沈積一層氮化鈦於第4A、 結果之平i及剖面圖成二氧化敎襯底層於氮化鈥層上之 石夕及圖/系分別繪示非等向性儀刻穿過二氧化 圖。鈦以外路底電極之一區域的結果之平面及剖面 19 1324387 第7A及第7B圖係分別繪示沈積一鍺銻碲（GST)於 第6A、6B圖之結構上以及回蝕該層以形成GST栓塞之結 果的平面及剖面圖。 第8A及第8B圖係分別繪示沈積覆蓋氧化物於第7A、 7B圖之結構以及平面化之結果的平面及剖面圖。 第9A及第9B圖係分別繪示形成頂電極於第8A、8B 圖之結構上之結果以及標示以顯示完成之記憶細胞之某些 特徵之大小的平面及剖面圖。 第9C圖係繪示圖9A之頂電極之另一型態之平面圖。 第10圖係顯示包括相變化記憶構件之記憶陣列之示 意圖。 【主要元件符號說明】 10 記憶細胞結構 11 分隔層 12 底電極 13 周緣 14 頂電極 16 電絕緣層 17 電絕緣襯底 18 杯狀導電襯底 19 箭頭 20 相變化材料栓塞 21 表面 22 非晶態 23 小區域 26 覆蓋氧化物 1324387
27 底部 28 開口 29 側壁 92 .分隔層的空洞寬度 94 杯狀導電薄膜側壁部分之厚度 95 杯狀薄膜之底部厚度 98 栓塞與底電極接觸的區域之寬度 99 栓塞高度 123 、 124 字元線 128 共同源極線 132 、 133 底電極構件 134 頂電極構件 135 > 136 記憶細胞 141 、 142 位元線 145 γ解碼器與字元線驅動器 146 X解碼器與一組感測放大器 150 、 151 、 152 存取電晶體 210 底電極堆疊或島 212 底電極 216 絕緣層 221 表面介金屬介電質層 230 餘刻停止層 311 填充層 421 絕緣層表面 422 空洞 427 絕緣層表面 512 分隔層表面 21 1324387 517 絕緣襯底 518 導電薄膜 522 空隙 622 開口

Claims (1)

  1. I324J8/ 十、申請專利範圍 1. 了種記憶細胞裳置，包括一底電極與一頂電極，一記 憶材料栓塞接觸至該底電極，以及_杯狀導電構件 =緣接觸至該頂電極且在底部具有—開口接觸至該= 材料。 〜 隐細胞裝置，其中該 25 埃（angstrom)至 2.如申請專利範圍第1項所述之記,
    導電構件在該周緣處之厚度係介於約 200埃之間。 … 3. 導 電 ^申請專利範圍第2項所述之記憶細胞裝置，其 構件在該周緣處之厚度係為約5〇埃。 5. 導電利範圍第4項所述之記憶細胞裝置，其中該 牛一該圮憶材料接觸處之厚度係為約5〇埃。 纪情專利範圍第1項所述之記憶細胞裝置，其中該 底電極之接觸區域其寬度係介於約20夺乎 主約260奈米之間。 不木 7 印倍請專利範圍第6項所述之記憶細胞裝置，其中兮 '與該底電極之接觸區域其寬度係為約70奈米。〜 8.如申請專利範圍第Μ所述之記憶細胞裝置，其中該 23 1324387 記憶材料栓塞之高度係介於約2〇奈米至約1〇〇奈米之間。 9. 如申請專利範圍第8項所述之記憶細胞裝置，其中該 έ己憶材料栓塞之高度係為約3〇奈米。 10. 如申請專利範圍第丨項所述之記憶細胞裝置，其中該 記憶材料包括一相變化記憶材料。 y·如申請專利範圍第10項所述之記憶細胞裝置，其中該 •記憶材料包括一硫屬化物（Chalcogenide)材料。 ^2·如申請專利範圍第10項所述之記憶細胞裝置，其中該 . 記憶材料包括一至少雙穩態之合金。 如申請專利範圍第11項所述之記憶細胞裝置，其中該 記憶材料包括一鍺銻碲(GST)材料。 ^4.如申請專利範圍第n項所述之記憶細胞裝置，其中該 φ ί Ϊ材料包括一由化學式GexSbyTez所表示之硫屬化物， -巾 ; 〇^y^5 ;且 〇gz$1〇。 如申叫專利範圍第14項所述之記憶細胞裝置，其中該 鍺錄碲材料係為X:y:z = 2:2:5。 ^6·如申請專利範圍第15項所述之記憶細胞裝置，其中該 記憶材料包括Ge2Sb2Te5。 Π.如申請專利範圍第11項所述之記憶細胞裝置，其中該 24 1324387 記憶材料包括一經掺雜之鍺銻碲。 18. 如申請專利範圍第17項所述之記憶細胞裝置，其中該 記憶材料包括一以氮摻雜之鍺銻碲。 19. 如申請專利範圍第17項所述之記憶細胞裝置，其中該 - 記憶材料包括一以矽摻雜之鍺銻碲。 20. 如申請專利範圍第17項所述之記憶細胞裝置，其中該 參記憶材料包括一以鈦摻雜之鍺銻碲。 21. —種用以製造一記憶細胞裝置之方法，包括： 提供一基板其在一表面具有一介金屬介電質，形成一 第一電極層於該介金屬备電質之上，形成一電絕緣層於該 第一電極層之上，形成一停止層於該電絕緣層之上，以及 圖案化各層以形成島狀底電極，每一該島狀底電極包括一 電絕緣元件與一停止元件； 沈積一填充材料於該介金屬介電質及該些島狀之上； φ 移除該填充材料至該停止元件，剩餘之該填充材料包括一 分隔層； 移除該停止元件，形成一通孔，該通孔係由該分隔層 之一側壁與該電絕緣元件之一外露表面所定義； 沈積一導電材料以形成一導電薄膜於該填充材料、該 分隔層之側壁與該電絕緣元件之外露表面之上； 沈積一電絕緣Μ產材料於該導電薄膜之上； 進行一非等向性蝕刻，以從該分隔層之表面移除該絕 緣襯底材料及該導電薄膜，並形成一開口穿過該絕緣襯底 材料、且穿過該導電薄膜； 25 1324387 沈積一相變化記憶材料於該開口中； 形成一氧化物覆蓋層於該相變化記憶材料之上；以及 形成一頂電極於該氧化物覆蓋層以及該分隔層之表面上。 22. 如申請專利範圍第21項所述之方法，其中該填充層沈 積步驟包括沈積一材料其蝕刻選擇性係高於該停止層。 23. 如申請專利範圍第21項所述之方法，其中該填充層沈 積步驟包括沈積一材料其化學機械研磨（CMP)速率係高於 ^ 該停止層。 24. 如申請專利範圍21像所述之方法，其中該填充層沈積 步驟包括高密度電漿化學氣相沈積。 - 25.如申請專利範圍第21項所述之方法，其中該停止材料 沈積步驟包括沈積一材料其蝕刻選擇性係高於該絕緣層。 26. 如申請專利範圍第21項所述之方法，其中該停止材料 _ 沈積步驟包括沈積一材料其化學機械研磨（CMP)速率係高 於該填充層。 27. 如申請專利範圍第21項所述之方法，其中該非等向性 蝕刻步驟包括，進行一反應性離子蝕刻以移除該絕緣襯底 材料，利用一含氯化合物進行一化學蝕刻以形成穿過該導 電薄膜之該開口，以及利用一含氟化合物進行一反應性離 子蝕刻以形成穿過該絕緣材料層之該開口。 26
TW096100853A 2006-12-28 2007-01-09 Resistor random access memory cell device TWI324387B (en)

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