TWI311346B - - Google Patents
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- TWI311346B TWI311346B TW092120708A TW92120708A TWI311346B TW I311346 B TWI311346 B TW I311346B TW 092120708 A TW092120708 A TW 092120708A TW 92120708 A TW92120708 A TW 92120708A TW I311346 B TWI311346 B TW I311346B
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- wiring
- electrode pads
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 claims abstract description 259
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
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- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
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- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 239000006023 eutectic alloy Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L27/0203—Particular design considerations for integrated circuits
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Design And Manufacture Of Integrated Circuits (AREA)
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•了31192120708號專利申請案 #文說明書修正頁 民國97年12月15日修正 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於半導體裝置及其製造技術,特別是關於 有效應用於具有凸塊電極的半導體裝置及其製造技術的技 術。 【先前技術】 例如如 LCD ( Liquid Crystal Display :液晶顯示器) 驅動器般的多接腳半導體裝置中,由於電極銲墊數的增 加,而存在有晶片尺寸增大的問題。其原因係引出半導體 晶片內的積體電路之電極的電極銲墊的尺寸,由於接合強 度的確保、接合精度或者構裝半導體晶片側的規格等,與 元件或者配線的尺寸縮小相比,無法變得太小之故,因電 極銲墊數目或者尺寸而決定了晶片尺寸。因此,在多接腳 半導體裝置中,例如,逐漸採用將電極銲墊配置在比半導 體晶片更內側的配置元件或者配線等之區域(主動區域) 的方式。 另外,關於具有凸塊電極的半導體裝置,例如在專利 第3022565號公報中有揭露:在電極銲墊的下方配置虛擬 圖案之技術。 【發明內容】 [發明所欲解決之課題] 可是在上述主動區域配置電極銲墊的構造中,由本發 -5- *1311346 (2) 明者首先發現存在以下的新課題。 即在電極銲墊下方形成元件或配線等,由於電極銲墊 下方的構造依各電極銲墊而不同,即使是相鄰的電極銲墊 彼此之間’或者即使凸塊的厚度均勻,由於半導體晶片的 主面內之電極銲墊的高度,即接合於電極銲墊的凸塊電極 的高度變得不均勻的結果,在半導體晶片的電極銲墊和構 裝半導體晶片的構裝體的配線之間,會有產生接合不良的 問題。 本發明之目的在於提供:能夠使半導體晶片的主面內 的多數電極銲墊的高度一致的技術。 由本說明書的敘述以及所附圖面,本發明之上述以及 其他目的和新的特徵理應變得清楚。 [解決課題用的手段] 如簡單說明本案所揭示發明中的代表性者的槪要,則 如下述: 即本發明可使配置在半導體晶片的主面之配置有元件 或配線等之區域的多數電極銲墊的基底構造變得均勻。 【實施方式】 在以下的實施形態中,爲了方便,在有需要時,係分 割爲多數的片段或者實施形態而作說明,除了特別明示的 情形外,彼等並非相互沒有關係,存在有一方爲另一方的 一部份或者全部的變形例、詳細、補足說明等之關係。另 -6- 1311346 (3) 外,在以下的實施形態中,於談及要素的數目等(含個 數、數値、量、範圍等)時,除了特別明示時以及原理上 明確限定爲特定數目之情形等以外,並不限定於該特定數 目,可爲特定數以上或者以下。另外,在以下的實施形態 中,其構成要素(也含要素步驟等)除了特別明示時以及 原理上認爲係必須之情形等以外,不用說並非一定需要。 同樣地,在以下的實施形態中,在言及構成要素的形狀、 位置關係等時,除了特別明示時以及認爲原理上明確並非 如此之情形等以外,設含實質上近似或者類似該形狀等。 此在上述數値以及範圍中也相同。另外,對於說明本實施 形態用的全部圖中之具有相同機能者,賦予相同符號,省 略其之重複說明。另外,在本實施形態所使用的圖面中, 即使爲平面圖,擔是爲了容易觀看圖面,也有賦予剖面線 之情形。以下,依據圖面來說明本發明之實施形態。 (實施形態1 ) 在本實施形態中,於半導體晶片之配置有元件或者配 線的主動區域配置多數電極銲墊(以下,單稱爲銲墊)之 主動區域銲墊構造的半導體裝置中,設上述多數銲墊的各 下層構造都是均勻的。具體爲:第1,配置在各銲墊區域 內的銲墊下層的配線佔有率(配線佔有率)在每一配線層 都成爲均勻。爲此,在同一配線層的多數銲墊區域中,於 配線佔有率和其他銲墊區域的配線佔有率相比爲比較少的 地方配置虛擬配線。另外,在同一配線層的多數銲墊區域 1311346 (4) 中’配線佔有率比其他銲墊區域的配線佔有率多的地方, 於配線形成縫隙(去除配線的一部份之區域)。另外,第 2’在半導體晶片的全部銲墊,即積體電路用銲墊和虛擬 銲墊的下層配置主動區域。 首先’說明上述虛擬配線的配置例。第1圖〜第3圖 係顯示銲墊PD1〜PD3的下層之特定同一配線層的配線 MXa、MXb、MXc、MXd、MXe的重要部位平面圖之一 例。另外,第4圖〜第6圖係顯示第1圖〜第3圖的配線 MXa〜MXe的Y1 — Y1線' Y2 - Y2線以及Y3 — Y3線的 剖面圖。銲墊PD1〜PD3係上述凸塊被接合的部份,配置 在同一半導體晶片的主動區域的不同位置。各銲墊PD1〜 PD3的平面尺寸以及平面形狀係相等。配線MXa、MXb、 MXc、MXd係顯示半導體晶片的積體電路構造上所必要的 訊號或者電源用的配線,配線MXe係顯示半導體晶片的 積體電路構造上不必要的虛擬配線。任何之配線MXa〜 MXe,例如都是介由微影法技術以及蝕刻技術將以鋁等爲 主體的金屬膜或者以鋁等爲主體的金屬膜和其他導體磨的 積層導體膜(例如,由下層依序堆積以鈦(Ti )、氮化鈦 (TiN )、鋁等爲主體的金屬膜以及氮化鈦之積層導體 膜)予以圖案化,形成在絕緣膜IS a上,以絕緣膜IS b所 覆蓋。此處,如第3圖以及第6圖所示般,在銲墊PD3 區域之本來不配置配線的區域配置虛設用的配線MXe。 藉此,銲墊p D 3區域內的下層配線佔有率變成和第1圖 以及第2圖的銲墊PD1、PD2區域內的下層配線佔有率相 1311346 (5) 等。因此,能夠使第1圖〜第3圖之銲墊PD1〜 內的基底絕緣膜ISb之上面的高度如第4圖〜第 般成爲一致。另外,能夠提升各銲墊PD1〜PD3 基底絕緣膜ISb的上面部份的平坦性。 此處,雖然假定第3圖之虛設用配線MXe 配線沒有電性連接的浮置狀態的配線,但是虛擬 以藉由使積體電路構造上所必要的配線(此丨 MXd等)的一部份延伸在需要虛擬配線的配置 形成。在此情形下,配線本身雖非虛擬配線,但 施形態中,係將爲了本實施形態之目的的達成而 有必要配置配線的區域的配線部份當成虛擬配線 第7圖以及第8圖係顯示虛設用的配線之配置變 7圖係顯示與第1圖〜第6圖所示配線爲同一層 重要部位平面圖之一例,第8圖係顯示第7圖 Y4 - Y4線的剖面圖。銲墊PD4係表示配置在第 3圖之銲墊PD1〜PD3所配置的半導體晶片的不 域的銲墊,其平面尺寸以及平面形狀與銲墊PD1 等。配線MXf、MXg係表示半導體晶片之積體 上所必要的訊號或者電源用配線,配線MXh係 配線。在此情形,銲墊PD4區域內的下層的配; MXg的佔有率與第丨圖〜第3圖幾乎相等,由 有率一致的觀點而言,不需要虛擬配線之故,在 的區域內不配置虛擬配線。此處,虛設用的配線 配置在銲墊PD4的外圍附近。如不配置此虛設 P D 3區域 6圖所示 區域內的 係與其他 配線也可 ®,配線 之區域而 是在本實 延伸在沒 。另外, 形例。第 的配線的 的配線之 1圖〜第 同主動區 〜P D 3相 電路構造 表示虛擬 線 MXf、 使配線佔 銲墊 PD4 MXh係 用的配線 1311346 (6) MXh時,在銲墊PD4的外圍附近的絕緣膜ISb的 凹陷而產生段差’但是接合於銲墊PD4的凸塊的 比銲墊P D 4稍微大些,所以上述銲墊P D 4的外圍 絕緣膜I S b上面的段差被反應於凸塊電極上面,有 上邊的平坦性,另外,有時會發生比其他凸塊的上 度還低的情形。因此’藉由在銲墊P D 4的外圍附 虛設用配線MXh,可以防止在銲墊PD4的外圍部 膜ISb上面形成段差,可以提升銲墊PD4上面的平 能夠確保銲墊PD4的高度,可使接合於銲墊PD4 的上邊的高度與其他凸塊的上邊的高度相等。另外 均勻形成凸塊的厚度。即凸塊的厚度偏差幾乎可以 視。 接著,說明上述縫隙的配置例。第9圖〜第] 顯示銲墊 PD5〜PD7的下層之特定同一配線層 MXi、MXj、MXk、MXm的重要部份平面圖的一 外,第12圖〜第14圖係顯示第9圖〜第11圖 MXi、MXj、MXk、MXm 之 Y5— Y5 線、Y6 - Y6 Υ7-Υ7線的剖面圖。銲墊PD 5〜PD 7係與上述銲 〜PD3相同,所以省略說明。配線MXi、MXj、 MXm係表示半導體晶片的積體電路構造所必要的 者電源用配線。配線MXi ' MXj、MXk、MXm的材 形成方法等係與上述配線MXa等相同。此處,
圖、第 Π圖、第13圖以及第14圖所示般, MXk、MXm的一部份形成縫隙SL。縫隙SL可I 上面雖 平面積 附近的 損凸塊 邊的局 近配置 的絕緣 坦性, 之凸塊 ,可以 予以忽 I 1圖係 的配線 例。另 的配線 線以及 墊PD1 MXk、 訊號或 料或者 ®第 10 在配線 由去除 -10- 1311346 (7) 配線MXk、MXm的一部份而形成。藉此,銲墊PD6、 PD7區域內的下層配線的佔有率變成與第9圖的銲墊PD 5 區域內的下層配線的佔有率相等。因此,可使第9圖〜第 11圖的銲墊PD5〜PD7區域內的基底絕緣膜ISb的上面的 高度如第12圖〜第14圖所示般成爲一致。另外,可以提 升各銲墊PD5〜PD7區域內的基底絕緣膜ISb的上面部份 的平坦性。縫隙SL係如第1 0圖所示,也可以形成在配線 MXk的中央,也可以如第1 1圖般,形成爲由配線MXm 的外圍朝向中央延伸。此處,第10圖以及第11圖的縫隙 SL係配合第9圖的MXi、MXj的鄰接間的間隙位置而形 成。藉此,可使銲墊PD5〜PD7的基底狀態更成爲相同狀 態,所以能夠使銲墊P D 5〜P D 7區域內的基底絕緣膜IS b 的上面高度以及平坦性更爲一致。 另外’第15圖以及第16圖係顯示縫隙SL的變形 例。在第1 5圖中,顯示使縫隙SL的配線中央側端部朝第 15圖的下方彎曲而延伸的例子。另外,在第16圖中,顯 示使朝第16圖的上下方向(銲墊PD6的長度方向)延伸 的多數縫隙SL形成爲相互成爲平行之例子。另外第17圖 〜第19圖係顯示銲墊PD8〜pDl〇的下層之特定同一配線 層的配線MXn、MXp、MXq、MXr、MXs的重要部位平面 圖的一例。銲墊PD8〜PD10係與上述銲墊 PD1〜PD3相 同’所以省略說明。配線MXn、MXp、MXq ' MXr、MXs 係表示半導體晶片之積體電路構造所必要的訊號或者電源 用配線’其材料或者形成方法等係與上述配線MXa等相 -11 - 1311346 (8) 同。此處,如第〗8圖以及第19圖所示般,縫隙S L係配 合第17圖的配線MXn、MXp、MXq的鄰接間的間隙位置 而形成。在第19圖中,縫隙SL係形成爲框狀。另外,上 述銲墊PD1〜PD10也可以是半導體晶片之積體電路構造 所必要的訊號或者電源用銲墊的情形,也可以爲上述積體 電路之構造本身所不必要的虛擬婷塾之情形。 在此種本實施形態中,藉由形成虛擬配線或者縫隙, 配置在半導體晶片之主面的全部銲墊區域內的銲墊下層的 配線佔有率,於每一配線成爲均勻。第2 0圖係就銲墊區 域內的下層配線的佔有率,比較本發明者檢討的技術(改 善前)和本實施形態的技術(改善後)而舉例顯示之圖。 在改善前,在第1層配線Μ1、第2層配線M2以及第3 層配線Μ 3之各配線層中,各銲墊P D 1〜P D η區域內的配 線面積佔有率有偏差。或者在銲墊PD〜PDn的下層存在 有主動區域、無主動區域的地方。由這些原因,在每一銲 墊PD1〜PDn而產生基底段差的不同之結果,在銲墊PD1 〜PDn的高度產生偏差。在半導體裝置之製造工程中,例 如爲了良好進行曝光處理或者蝕刻,對於配線的基底絕緣 膜施以蝕刻處理以使之平坦。因此,由對於曝光處理或者 蝕刻之觀點,雖然可以充分獲得基底絕緣膜的上面之平坦 性,但是由銲墊PD 1〜PDn的高度之觀點而言,即使施以 上述之飩刻處理,由於銲墊PD 1〜PDn區域內的配線佔有 面積率的偏差或者主動區域的有無,而有銲墊PD1〜PDn 的高度偏差變大之情形。另外,由於銲墊P D 1〜P D η配 -12- 1311346 (9) 置在主動區域,所以無法採用藉由在銲墊PD1〜PDn的下 層設置貝他配線,以確保基底絕緣膜上面的平坦性之手 法。 相對於此,在本實施形態(改善後)中’在第1層配 線Μ1、第2層配線M2以及第3層配線M3的各配線層 中,各銲墊PD 1〜PDn區域內的配線面積佔有率變得均 勻。另外,在全部的銲墊PD1〜PDn下配置主動區域。藉 此,可使半導體晶片的主面內(在半導體裝置之製造工程 中,爲晶圓的主面內)的多數銲墊的基底狀態幾乎成爲一 致,能夠使多數銲墊的上面之高度幾乎均勻。因此’可使 接合於各銲墊的凸塊(凸塊電極)的上邊之高度幾乎成爲 均勻。另外,能夠提升各銲墊的上面的平坦性,所以能夠 提升接合於此之凸塊的上邊的平坦性。因此,透過凸塊可 以沒有不當地使半導體晶片的多數銲墊和構裝半導體晶片 的構裝體之多數的配線良好連接。另外,各銲墊下層的配 線形狀、尺寸、圖案配置位置以及配置間距等也以相互相 等地形成爲佳。藉此,能夠使多數銲墊的基底狀態更爲一 致,可使多數銲墊的上面的高度以及平坦性更爲均勻,所 以可使接合於各銲墊的凸塊之上邊的高度以及平坦性更爲 均勻。 如此,在本實施形態中,爲了使多數的銲墊上面的高 度以及平坦性更爲均勻,雖然使多數銲墊的基底狀態均勻 一致,但是即使在不完全均勻之情形下,如在某種程度之 誤差範圍內,其效果也不會消失。理想上,各銲墊下的配 -13- (10) 1311346 線佔有率如大約在1 0 %之程度,更好爲5 %程度之範圍內 的誤差,便可使銲墊上面的高度以及平坦性幾乎均勻° 另外,在本實施形態中,雖將各銲墊下的配線層記爲 第1層配線Μ1、第2層配線M2以及第3層配線M3 ’但 是各配線層的配線佔有率已在大約50%以上爲佳。此係在 各銲墊下,絕緣膜多時,上面雖容易產生凹陷、段差’但 是藉由多數配置比絕緣膜硬的金屬層,段差的變動變少, 容易使銲墊上面的高度以及平坦性變得均勻。 接著,說明上述主動區域的配置。第21圖以及第22 圖係顯示銲墊PD11、PD12的下層半導體基板(以下,單 稱爲基板)1S的重要部位平面圖之一例。另外,第23圖 以及第24圖係顯示第21圖以及第22圖的Υ8_ Υ8線以 及Υ9 — Υ9線的剖面圖。在第21圖以及第22圖中,爲了 使圖面容易觀看,在分離部2賦予剖面線。此分離部2例 如係在氧化基板1S而形成的LOCOS ( Local Oxidization of Silicon :區域氧化矽)或者基板IS形成溝,在此溝埋 入絕緣膜而形成的 STI ( Shallow Trench Isolation :淺溝 渠絕緣)等,形成用於絕緣分離各主動區域。銲墊PD 1 1 係半導體晶片之積體電路構造所必要的訊號或者電源用銲 墊。在銲墊PD11的下層配置形成有特定元件的主動區域 La。另一方面,銲墊PD12係半導體晶片之積體電路構造 非必要的虛擬銲墊。此處,以虛設用的銲墊P D 1 2的平面 尺寸係比上述銲墊P D 1 1大爲例。在此虛設用銲墊P D 1 2 的下層也配置主動區域Lb。此主動區域Lb並不是配置爲 -14- (11) 1311346 用於形成特定元件,係如上述般,設置以使半導體晶片的 多數銲墊上面高度(即多數凸塊的上邊的高度)一致用之 虛設用的主動區域。如此,藉由在含虛設用銲墊PD12的 全部銲墊的下層配置主動區域,容易使全部的銲墊之基底 絕緣膜上面的平坦性以及高度變得一致。即可以使多數銲 墊的基底狀態更爲一致,可使多數銲墊的上面高度以及平 坦度更爲均勻,所以可使接合於各銲墊的凸塊的上邊的高 度以及平坦度更爲均句。 接著,說明本實施形態之半導體裝置的具體適用例。 第25圖係顯示構成本實施形態之半導體裝置的半導體晶 片1 C的整體平面圖的一例。此半導體晶片1 C例如具有 形成爲細長方形狀的基板1 S,在其主面例如形成驅動液 晶顯示裝置(LCD: Liquid Crystal Display)的 LCD 驅動 電路。此LCD驅動電路係具有對於LCD的單元陣列之各 畫素供給電壓,以控制液晶分子的面向之機能,係具有: 閘極驅動電路3、源極驅動電路4、液晶驅動電路5、靜 態 RAM ( Random Access Memory :隨機存取記憶體)6 以及周邊電路7。在半導體晶片1C之外圍附近,上述之 多數銲墊PD係沿著半導體晶片1 c的外圍而每隔特定間 隔配置。這些多數銲墊PD係配置在半導體晶片1C之配 置元件或者配線的主動區域上。在這些多數銲墊PD中, 存在積體電路構造所必要的積體電路用銲墊,以及其他積 體電路構造上並不必要的虛擬銲墊。上述銲墊PD係呈鋸 齒狀配置在半導體晶片1 C的1個長邊以及2個短邊附 -15- 1311346 (12) 近。此鋸齒狀配置的多數銲墊主要爲閘極輸出訊號用以及 源極輸出訊號用的銲墊。半導體晶片1 c之長邊的中央而 呈鋸齒狀配置的多數銲墊PD係源極輸出訊號用銲墊’半 導體晶片1 C之長邊的兩角落附近側以及半導體晶片1 C 的兩短邊的鋸齒狀配置之多數銲墊PD係閘極輸出訊號用 銲墊。藉由此種鋸齒狀配置,可以一面抑制半導體晶片 1C的尺寸增加,一面配置需要多數數目的閘極輸出訊號 或源極輸出訊號用銲墊。及可以縮小晶片尺寸,而且增加 銲墊(接腳)數目。另外,在半導體晶片1C的另一長邊 附近排列配置而非鋸齒狀配置的多數銲墊PD係數位輸入 訊號或者類比輸入訊號用銲墊。另外,在半導體晶片1C 的四個角落附近,配置有平面尺寸相對表較大的銲墊 PD。此相對比較大的銲墊PD係角落虛擬銲墊。相對比較 小的銲墊PD的平面尺寸例如爲35//mX50//m之程度。 另外,相對比較大的銲墊PD (角落虛擬銲線)的平面尺 寸例如爲80 # mX80 // m之程度。另外,銲墊PD的鄰接 間距例如爲30 // m〜50 # m之程度。另外,銲墊PD的總 數例如爲800個之程度。 接著,利用第26圖〜第45圖來說明本實施形態之半 導體裝置的上述銲墊PD的下層狀態。此處,顯示具有第 3層配線構造的半導體裝置之例。在最上方的第3配線層 形成上述銲墊PD。第26圖〜第31圖係顯示銲墊PD13〜 PD 1 8 ( PD )的正下方之第2配線層的配線M2的重要部 位平面圖之一例,第32圖〜第37圖係顯示與上述第26 -16- 1311346 (13) 圖〜第31圖相同之銲墊ρ〇13〜PD18(PD)之下層的第1 配線層的配線Ml的重要部位平面圖之一例,第38圖〜 第43圖係顯示與上述第26圖〜第31圖相同之銲墊PD13 〜PD18(PD)之下層的基板主面的重要部位平面圖之一 例。另外,第44圖係顯示第27圖、第33圖以及第39圖 的ΥΙΟ— Y10線的剖面圖,第45圖係顯示第29圖、第35 圖以及第4 1圖的Y 1 1 — Y 1 1線的剖面圖。銲墊P D 1 3、 PD14例如爲閘極輸出訊號用銲墊PD。銲墊PD13係顯示 鋸齒狀配置之銲墊中的外側(更接近半導體晶片1 C的外 圍側)之銲墊’銲墊.PD14係顯示鋸齒狀配置之銲墊中的 內側(更接近半導體晶片1C的中心側)之銲墊。銲墊 PD15例如爲源極輸出訊號用銲墊PD,顯示鋸齒狀配置的 銲墊中的內側銲墊。銲墊PD16例如爲上述角落虛擬銲 墊。銲墊PD17、PD18例如爲類比輸入訊號用銲墊pd。 另外,此處雖然爲了說明而挑選出一部份的銲墊P D 1 3〜 P D 1 8,但是實際上係對於全部銲墊P D,可適用本實施形 態之構造。另外’爲了使圖面容易觀看’在第1層配線 Μ1、第2層配線M2以及分離部2賦予剖面線。 首先,利用第26圖〜第31來說明歸墊PD13〜PD18 之正下方的第2層配線Μ2。在銲墊PD13〜PD18之正下 方的第2層配線M2中,例如形狀、尺寸以及配線圖案的 位置關係等係如第26圖和第27圖的第2層配線Μ2或第 3 0圖和第3 1圖的第2層配線M2般,形成爲相同或者近 似。另外,銲墊PD正下方的第2層配線M2彼此的形 -17- 1311346 (14) 狀、尺寸或者配線圖案的位置關係即使不同,也有形成縫 隙SL或者虛擬配線之區域以使多數銲墊PD13〜PD18區 域內的第2層配線M2的佔有率(配線佔有率)成爲相 等。另外,在銲墊PD區域內的第2層配線M2中,也實 際上存在有:半導體晶片之積體電路構造所必要的第2層 配線M2,和其他在積體電路構造本身雖不需要,但是由 於爲了使上述之銲墊區域內的佔有率成爲相等之觀點而配 置的虛設用第2層配線M2 (配線整體爲虛設,而成爲浮 置狀態之情形外,也有以積體電路用配線的一部份所形成 的情形)之情形。 接著,由第32圖〜第37圖來說明銲墊PD13〜PD18 的下層之第1層配線Ml。銲墊PD13〜PD18的下層之第 1層配線Μ 1例如形狀、尺寸以及配線圖案的位置關係 等,也如第32圖和第33圖的第1層配線Ml或第36圖 和第3 7圖的第1層配線Μ1般,形成爲相同或者近似。 另外,形狀、尺寸或者配線圖案的位置關係即使不同,也 有形成縫隙S L或者虛擬配線之區域以使多數銲墊P D 1 3〜 PD1 8區域內的第1層配線Ml的佔有率(配線佔有率) 成爲相等。另外,在銲墊P D區域內的第1層配線Ml 中,也實際上存在有:半導體晶片之積體電路構造所必要 的第1層配線Ml,和其他在積體電路構造本身雖不需 要,但是由於爲了使上述之銲墊區域內的佔有率成爲相等 之觀點而配置的虛設用第1層配線Ml (配線整體爲虛 設,而成爲浮置狀態之情形外’也有以積體電路用配線的 -18 - (15) 1311346 一部份所形成的情形)之情形。 如此,在本實施形態中,在銲墊P D下的全部配線層 中,藉由使其每一配線層(此處,第1、第2配線層)之 銲墊PD區域內的配線佔有率成爲均勻,可以使半導體晶 片1C的主面內之多數銲墊PD的上面高度幾乎成爲均 勻。因此,可使接合於該各銲墊PD的凸塊之上邊高度幾 乎均勻。另外,可以提升各銲墊PD的上面平坦度,所以 能夠使接合於此的凸塊的上邊的平坦性提升。因此,藉由 凸塊可以無不當地將半導體晶片1 C的多數銲墊PD和構 裝半導體晶片1C的構裝體之多數配線良好地予以接合。 接著,由第38圖〜第43圖來說明銲墊PD 13〜PD18 的下層之基板1 S的主面狀態。在本實施形態中,在半導 體晶片1C的全部銲墊PD的下層設置主動區域La、Lb。 主動區域係爲了在基板IS的主面形成元件區域而以分離 部2所規定的區域。因此,雖然一般在虛擬銲墊下不需要 設置主動區域,但是在本實施形態中,爲了使半導體晶片 1C的主面內的多數銲墊PD的上面高度,即多數凸塊的上 邊高度成爲一致,在虛擬銲墊(銲墊PD16等)之下也設 置主動區域Lb。如此,藉由在含虛設用銲墊PD的全部銲 墊之下層設置主動區域,可以使全部銲墊pD的基底絕緣 膜上面的平坦性以及高度一致。即可使多數銲墊PD的基 底狀態更爲一致,可使多數銲墊PD的上面高度以及平坦 性更爲均勻之故,所以可使接合於該銲墊PD的凸塊之上 邊高度以及平坦性更爲均勻。 -19- 1311346 (16) 接著,依據第44圖以及第45圖來說明半導體裝置之 剖面構造。基板1 S例如係由p型矽(S i )單結晶形成, 在其主面的裝置形成面形成有分離部2,用以規定上述主 動區域La以及虛擬主動區域Lb。分離部2例如係由藉由 LOCOS ( Local Oxidization of Silicon:區域氧化砂)法所 形成的氧化矽(Si〇2等)形成。但是,也可以溝型 (SGI : Shallow Groove Isolation 或者 STI : Shallow Trench Isolation)之分離部2來形成分離部2。 在由第44圖所示的銲墊PD14下層的基板1S之分離 部2所包圍的主動區域La例如形成pn接合二極體D。此 pn接合二極體D例如矽靜電破壞防止用之保護二極體, 藉由基板1 S的p井PWL和其上部的η型半導體區域8的 pn接合而形成。在基板1S的主面上例如形成由氧化矽膜 形成的絕緣膜IS1。在其上形成第1層配線Ml。第1層 配線 Μ1例如具有由下層依序堆積鈦(Ti )、氮化鈦 (TiN )、鋁(或者鋁合金)以及氮化鈦(TiN )之構 造。此鋁或者鋁合金等之膜爲主配線材料,形成爲最厚。 另外,該主配線材料的下層的鈦以及氮化鈦爲具有:抑制 鋁往基板1 S側移動,反之,基板1 S的矽往配線側移動之 阻障層機能、提升絕緣膜IS 1和第1層配線Μ1之密接性 的機能,另外,抑制或者防止由於電子遷移或者壓力遷移 所致的配線斷線不良的機能之機能膜。另外,主配線材料 的上層之氮化鈦在上述機能之外,也是具有在曝光處理時 可抑制或者防止光輪狀暈之反射防止膜的機能之機能膜。 -20 - 1311346 (17) 第1層配線Μ1爲透過形成在絕緣膜I s 1之平面圓形狀的 多數接觸孔CNT而與η型半導體區域8和pn接合二極體 D1連接。第1層配線Μ1例如係由氧化矽膜所形成的絕 緣膜IS2所覆蓋。在本實施形態中,上述多數的銲墊區域 內的絕緣膜IS2上面的高度成爲一致。另外,上述多數的 銲墊區域內的絕緣膜I S 2的上面可以獲得高的平坦性。在 此絕緣膜IS2上形成第2層配線M2。第2層配線M2的 材料構造與上述第1層配線Ml相同。第2層配線M2爲 透過形成在絕緣膜IS2之平面圓形狀的多數通孔TH1而 與第1層配線Μ1導電連接。第2層配線M2例如由以氧 化砂膜形成的絕緣膜IS 3所覆蓋。在本實施形態中,上述 多數的銲墊區域內的絕緣膜IS3上面的高度成爲一致。另 外,上述多數的銲墊區域內的絕緣膜IS3的上面可以獲得 高的平坦性。在該絕緣膜IS3上形成第3層配線M3。第 3層配線M3矽透過形成在絕緣膜IS3之平面圓形狀的多 數通孔ΤΗ2而與第2層配線M2導電連接。另外,第3層 配線M3雖然藉由表面保護用絕緣膜IS4而被覆蓋其大 半,但是第3層配線M3的一部份係由形成在絕緣膜IS4 的一部份的平面長方形狀的開口部9露出。由此開口部9 露出的第3層配線M3部份係成爲銲墊PD14 ( PD)。在 本實施形態中,多數的銲墊區域內的絕緣膜1S 2 ' IS 3的 上面高度係形成爲一致,所以銲墊PD的上面高度也成爲 一致。表面保護用絕緣膜I S 4例如係由:氧化矽膜的單體 膜、具有在氧化矽膜上堆積氮化矽膜之構造的機能膜或者 -21 - 1311346 (18) 具有在氧化矽膜上由下層依序堆積氮化矽膜以及聚亞醯胺 膜之構造的積層膜所形成。銲墊PD14(PD)係通過開口部 9而介由基底金屬膜10而與凸塊11接合。基底金屬膜1〇 係在提升凸塊1 1和銲墊PD或絕緣膜IS4的接著性之機能 外,也具有抑制或者防止凸塊1 1的金屬元素往第3層配 線Μ 3側移動或反之第3層配線Μ 3的金屬元素往凸塊1 1 側移動之阻障層機能的膜,例如,由鈦(Ti )或者鈦化鎢 (TiW)等高融點金屬膜的單體膜或者具有在鈦膜上由下 層依序堆積鎳(Ni)膜以及金(Au)之構造的積層膜所 形成。基底金屬膜10的平面尺寸比銲墊PD14(PD)的開口 部9稍微大些,與凸塊1 1幾乎相同,例如,爲40 /z mX70 # m之程度。凸塊1 1例如由金(A u )等形成,例如藉由 電鍍法形成。凸塊1 1的材料例如也可以使用鉛(Pb )-錫(Sn)銲料。 另一方面,在第45圖所示虛設用PD16下層的基板 1S雖如上述般,形成主動區域Lb,但是在該主動區域Lb 並無特別形成元件。當然,與其他婷墊P D相同,形成二 極體或其他元件,設置P井或η井等亦可。此虛設用銲墊 PD16下層的第2層配線M2和第1層配線Ml係通過多數 的通孔TH1而導電連接。銲墊PD16爲虛設用,所以雖然 不需要使其下層的第2層配線M2和第1層配線Ml導電 連接,但是在第1層配線M1中’爲了使和其他銲墊PD 的下層構造相同,所以也在銲墊PD16的下層設置多數的 通孔ΤΗ 1。藉此,可以使虛設用銲墊PD 1 6的上面高度更 -22- 1311346 (19) 接近其他銲墊PD的上面高度。即可以使接合於虛設用銲 墊PD16的凸塊11的上邊高度和接合於其他銲墊PD的凸 塊11之上邊高度更爲接近。 接著,說明此半導體裝置之製造工程的一例。在構成 平面略圓形狀的晶圓之基板1 s的主面例如藉由L 0 C 0 S法 形成分離部2,形成主動區域La、Lb後’在由分離部2 所包圍的主動區域La形成元件。在虛設用銲墊PD16下 的主動區域L b並不形成元件。接著,在基板1 S的主面上 藉由 CVD ( Chemical Vapor Deposition:化學氣相沈積 法)法等堆積絕緣膜IS1後,在絕緣膜IS1之特定地方藉 由微影法技術以及乾蝕刻技術形成平面圓形狀的接觸孔 CNT。之後,在該絕緣膜IS1上例如藉由濺鍍法等由下層 依序堆積氮化鈦、鈦膜、鋁膜以及氮化鈦膜後,藉由微影 法技術以及乾.蝕刻技術將此積層金屬膜予以圖案化,以形 成第1層配線Ml。接著,同樣地在絕緣膜IS 1上堆積絕 緣膜IS2,在絕緣膜IS2形成通孔TH1後,在該絕緣膜 IS2上與第1層配線Ml相同以形成第2層配線M2。接 著,同樣地在絕緣膜IS2上堆積絕緣膜IS3,在絕緣膜 IS3形成通孔TH2後,在該絕緣膜IS3上與第1層配線 Μ1相同而形成第3層配線M3。如上述般,爲了使配線的 佔有率一致,也有在這些各層的配線層設置縫隙SL (未 圖示出)。例如,在形成第1層配線Μ1後,藉由微影法 技術以及乾蝕刻技術予以圖案化以形成第1層配線Μ 1, 也可以藉由堆積絕緣膜IS2之工程,在溝內部塡埋絕緣膜 -23- 1311346 (20) IS2以形成縫隙SL。在其他配線層、第2層 第3層配線Μ 3形成縫隙S L之情形下’也 法而形成。之後’在絕緣膜1S3上堆積表面 IS4後,在絕緣膜IS4形成第3層配線M3 的開口部9,以形成銲墊PD。接著,在絕緣 藉由濺鍍法等形成鈦或者鈦化鎢等之高融點 膜,或者由具有在鈦膜上由下層依序堆積鎳 構造的積層膜所形成的導體膜後,在其上形 域露出,而其以外被覆蓋之光阻圖案。接著 等形成由金等形成之凸塊11後,去除光阻 由蝕刻去除基底導體膜,形成基底金屬膜 以製造在銲墊PD上具有凸塊11的半導體 半導體裝置之製造工程中,藉由以回蝕法或 磨(CMP : Chemical Mechanical Polishing 膜I S 1〜I S 3的上面變得平坦,可以使半導售 面內之多數銲墊PD的上面高度,即凸塊1 更爲均勻,另外,可以使各銲墊PD上面的 在採用上述回鈾法時,例如,在堆積絕緣膜 其上面,在其上堆積絕緣膜IS 2後,回蝕其 絕緣膜IS 1〜IS3藉由不等向性的乾蝕刻法 爲理想。另外,在採用上述C Μ P法蝕,雖 緣膜I S 1〜I S 3而個別施行,但是只對於形员 底絕緣膜IS 3的上面施以C Μ Ρ,也可以獲得 即在各絕緣膜I S 1〜I S 3形成後,進行回蝕: 配線Μ 2以及 可以同樣的方 保護用絕緣膜 的一部份露出 膜IS4上例如 金屬膜的單體 膜以及金膜之 成凸塊形成區 ,藉由電鍍法 圖案,另外藉 1 〇。如此,得 裝置。在此種 者化學機械硏 )法以使絕緣 !晶片1 C的主 1的上邊高度 平坦性提升。 IS1後,回蝕 上面,在每一 而施以回蝕較 可以就每一絕 ^銲墊PD之基 足夠的效果。 或者CMP,或 -24- 1311346 (21) 者只對於絕緣膜I s 3的上面進行c Μ P,可以提高凸塊1 1 的上邊高度的均勻性。 接著,第4 6圖係顯示第2 5圖所示本實施形態的半導 體裝置之各銲墊PD下的各每一層配線層的配線佔有率。 另外,第47圖係以棒狀曲線表示第46圖的第1層配線的 佔有率。另外,第48圖係以棒狀曲線表示第46圖的第2 層配線的佔有率。使各每一配線層之銲墊PD下的配線之 面積佔有率成爲相等。相對於改善前的半導體晶片1 C的 主面內的凸塊11之上邊高度偏差(4σ )爲批次內平均例 如1 . 5 # m之程度,在本實施形態中,半導體晶片.1 C的 主面內之凸塊11的上邊高度偏差(4σ )爲批次內平均例 如0.8/zm之程度,可以達到4σ <1.0/zm。另外,半導 體晶片1C之主面內的銲墊PD的高低差(最高者和最低 者之差)例如爲〇·3 m之程度。另外,半導體晶片1C 之主面內的凸塊1 1的高低差例如爲3.0 /z m之程度。此時 的銲墊PD下的配線之面積佔有率的偏差例如爲3%之程 度。如依據本發明者之檢討,銲墊PD下的配線之面積佔 有率的偏差在1 〇%以內,最好爲5%以內的情形爲佳。另 外,銲墊PD下的配線的面積佔有率以佔有5 0% (銲墊PD 的區域之一半)以上爲佳。另外,在施以上述CMP處理 時,半導體晶片1C之主面內的凸塊11的上邊高度偏差 (4 σ )在批次內平均例如爲0.78 //m之程度,凸塊11的 高度差例如爲2.3 v m之程度。另外,4 σ係顯示統計處理 半導體晶片1 C之主面內的數個地方(例如,6 0處)的凸 -25- 1311346 (22) 塊高度而算出的凸塊高度偏差之値。另外,此時的凸塊高 度係指由特定的基準距離至凸塊1 1的上邊的距離。此 處,雖將特定的基準距離設爲表面保護用絕緣膜IS4的上 面,但是也可將基板1 S的主面設爲基準位置。 接著,說明組裝本實施形態之半導體裝置的LCD之 一例。第49圖係LCD15的重要部位平面圖,第50圖係 第49圖的重要部位剖面圖,第51圖係第50圖的重要部 位放大剖面圖,第5 2圖係第51圖的重要部位放大剖面 圖。LCD15係具有液晶面板16、LCD驅動用半導體晶片 1 C以及背光。液晶面板1 6係具有:平面.四方形狀的2片 玻璃基板16a、16b,和玻璃基板16a、16b之外圍間的密 封部1 6c,和封入2片玻璃基板1 6a、16b之間的液晶材 料1 6d,和黏貼在液晶面板1 6的表背面的偏光板。LCD 1 5 有使用薄膜電晶體(TFT: Thin Film Transistor)的主動 型,和單純矩陣型(STN: Super — Twisted— Nematic:超 扭轉向列)之被動型。在主動型之情形,則在玻璃基板 (構裝體)16a形成在畫面顯示文字或圖畫等用的最小單 位之畫素的排列,和驅動該畫素用的閘極線以及源極線等 之配線1 7。在此情形下,多數的各各畫素係具有TFT和 電容器。另外,在主動型之情形,在玻璃基板1 6b係形成 彩色濾光片。而且,在此情形下,玻璃基板1 6a、1 6b的 材料例如使用無鹼玻璃。另一方面,在被動型之情形,在 玻璃基板1 6 a、1 6 b係形成在相互正交方向延伸的配線 1 7。另外,在偏光板之外,也配置相位差板。在此情形, -26- 1311346 (23) 玻璃基板1 6a、1 6b的材料例如使用碳酸鈉石灰或者低鹼 玻璃。不管主動型、被動型,配線1 7都例如使用由銦和 錫之氧化物形成的透明導電膜(ITO : Indium Tin Oxide film (銦錫氧化物))。另外,在任一種情形下,半導體 晶片1C都是在將該凸塊11的形成面朝向玻璃基板16a的 主面(配線1 7的形成面)之狀態下,例如介由不等向性 薄膜(ACF : Anisotoropic Conductive Film) 18 而連接在 玻璃基板 1 6 a上(C 0 G : C h i ρ Ο n G1 a s s :玻璃連接式晶 片)。異方性導電膜1 8例如係在由如環氧樹脂等之熱硬 化性樹脂所形成的絕緣性接著劑1.8a中分散或者定向鎳微 粒子或者焊錫球等導電粒子18b之電氣連接材料。半導體 晶片1 C之凸塊1 1和玻璃基板1 6a之配線1 7係藉由在其 間以壓潰狀態存在之導電粒子1 8b而導電連接。也可以使 用不等向向導電糊(ACP : Anisotoropic Conductive Paste)以代替此ACF。另外,在玻璃基板16a外圍的配 線1 7係介由撓性基板19而與印刷基板20導電連接。撓 性基板1 9例如具有由聚亞醯胺樹脂等形成的基板本體 19a ’和接合在其表面而以銅(Cu)爲主體的配線19b。 撓性基板1 9的配線1 9b的一端係與上述半導體晶片1 C以 及以與上述相同要領,介由異方性導電膜1 8而與玻璃基 板16a上的配線1 7導電連接。另一方面,配線〗9b的另 一端係介由焊錫2 1等與印刷基板20的配線導電連接。在 印刷基板2 0搭載有控制半導體晶片1 c的L C D驅動器電 路的動作之控制電路用半導體晶片或者其他的電子零件 -27- 1311346 (24) 等。 在將半導體晶片1 C構裝於玻璃基板1 6 a上,係例如 以如下方法爲之。首先,在玻璃基板1 6a上貼合異方性導 電膜18後,使半導體晶片1C的凸塊11朝向玻璃基板 1 6a側,將該凸塊1 1對位於配線1 7。接著,將半導體晶 片1C的凸塊11以特定壓力介由異方性導電膜18而按壓 於配線1 7,藉由數十秒保持加熱之狀態,以壓接狀態而 整體連接多數的凸塊1 1和多數的配線1 7。以此加熱、加 壓工程,接著劑融解、流動,而塡充於半導體晶片1C和 玻璃基板1 6a的間隙中,.進行半導體晶片1 C的密封。另 外,異方性導電膜1 8中的導電粒子1 8b被捕捉於凸塊1 1 和配線1 7之間,藉由所捕捉的導電粒子而使凸塊11和配 線 17導電連接。也可以採用 NCP ( Non Conductive Paste :非導電糊)之連接方式來代替此種使用 ACF (或 者ACP )之連接方式。NCP連接係藉由ACP連接之沒有 導電粒子的連接構造的絕緣糊(絕緣性接著劑)的連接方 式。在NCP連接時,半導體晶片1C的構裝方法本身雖與 使用上述ACF或ACP之情形相同,但是在NCP中,並不 是如ACP之以導電粒子爲媒體的連接,係直接壓接凸塊 1 1和配線1 7,在該壓接狀態下,藉由絕緣性接著劑予以 固定。ACF、ACP以及NCP與藉由融解凸塊11而接合之 方式相比,其構裝時的加壓力或加熱溫度比較低,所以在 獲得凸塊11的高度偏差或者表面平坦性、凸塊1 1和配線 1 7接合的穩定性上爲重要的因素。因此,可以使半導體 -28- 1311346 (25) 晶片1C之主面內的凸塊11的高度一致’另外’在各凸塊 1 1中,使用可以獲得高表面平坦性的上述本實施形態’ 在良好連接半導體晶片1C之主面內的凸塊11和多數的配 線17上爲有效。特別是在NCP中’在凸塊1 1和配線17 之間不存在導電粒子’所以凸塊1 1的高度偏差或表面平 坦性在獲得凸塊1 1和配線1 7的接合穩定性上大有作用’ 因此使用上述本實施形態在良好連接多數的凸塊11和多 數的配線1 7上更爲有效。因此’如依據本實施形態’可 以降低將半導體晶片1 c進行c 0 G構裝於L C D 1 5時的組 裝不良率。 (實施形態2 ) 在本實施形態中,例如’說明適用於 TCP ( Tape Carrier Package :帶狀載座封裝)時。第53圖係TCP之 重要部位斜視圖,第54圖係第53圖的TCP的內引線側 的重要部位放大剖面圖。 TCP係具有:基底捲帶(構裝體)25,和形成在其表 面的多數引線26,和介由凸塊1 1連接在該引線26的內 引線26a前端之半導體晶片1 C,和密封半導體晶片1 C以 及內引線26a等之密封部27,和覆蓋基底捲帶25的表面 的引線26之一部份的焊錫電阻2 8。基底捲帶2 5係例如 由聚亞醯胺樹脂等形成。引線26例如由銅(Cu )和錫 (Sn)之合金形成,在其表面施以銲料(Pb 一 Sn)或者金 (Au )的電鍍處理。在引線26中,以密封部27覆蓋的 -29 - 1311346 (26) 部份之內引線26a和由密封部27露出的外引線26b爲形 成爲一體。密封部27係例如由環氧系樹脂形成。 在將半導體晶片1 C構裝於基底捲帶2 5上,例如以如 下方法爲之。首先,將半導體晶片1C使其主面(多數的 凸塊1 1之形成面)朝上而載置於銲線台上以後’使半導 體晶片iC之主面內的凸塊11和基底捲帶25之內引線 26a對位。接著,藉由加熱成特定溫度的銲線工具將多數 的內引線26a按壓於多數的凸塊11’整批壓接接合多數 的內引線26a和多數的凸塊11。如在內引線26a的表面 施以焊錫.電鍍,則內引線2 6 a和凸塊1 1係藉由金一錫共 晶合金而接合,另外’如在內引線2 6 a的表面施以金電 鍍,則內引線2 6 a和凸塊1 1係藉由金一金接合而予以接 合。 接著,第55圖係將第53圖的TCP構裝於LCD15之 狀態的重要部位剖面圖。TCP之一長邊側的引線26 (外 引線26b )係介由異方性導電膜1 8而與LCD15之配線I7 如同上部般導電連接。另一方面,TCP的另外一長邊側的 引線26 (外引線26b )藉由焊錫21而與印刷基板20的配 線29導電連接。也可以使用異方性導電膜18以代替焊錫 2卜 在本實施形態中,半導體晶片1 C的主面內之多數的 凸塊1 1的高度也均勻,另外,凸塊1 1的表面的平坦性 高,所以可以使半導體晶片1 C的多數的凸塊1 1和TCP 的多數的內引線26a良好連接。因此,如依據本實施形 -30- 1311346 (27) 態,能夠降低將半導體晶片i c構裝於帶狀載座時的組裝 不良率。 (實施形態3 ) 在本實施形態中,例如說明適用於 COF ( Chip On Film :薄膜連接式晶片)時。 第56圖係以COF將本實施形態的半導體裝置構裝於 LCD 1 5之狀態的重要部位剖面圖。撓性基板(構裝體)1 9 的多數配線1 9b係介由異方性導電膜1 8而與LCD 1 5的配 線1 7如上述般導電連接。另外,在撓性基板19的配線 19b介由凸塊11而與半導體晶片1C導電連接。另外,其 他的電子零件30介由焊錫凸塊31而與配線19b導電連 接。1在電子零件3 0形成控制半導體晶片1 C的動作之控 制電路等。將半導體晶片1 C構裝於撓性基板1 9的方法係 與上述實施形態1相同。 在本實施形態中,半導體晶片1C的主面內之多數的 凸塊11的高度也均勻’另外,各凸塊11的表面平坦性 高,所以可以使半導體晶片1 C的多數的凸塊1 1和撓性基 板1 9的多數的配線1 9b良好連接。因此,如依據本實施 开夕,可以降低將半導體晶片1 C構裝於撓性基板1 9時的 組裝不良率。 (實施形態4) 在本實施形態中,係說明例如適用於BGA ( Ball -31 - 1311346 (28)
Grid Array :球柵陣列封裝)時。第π圖係顯示例如Fan 一 Out 开夕式之 T — TF( Tape — type Thin Fine — Pitch:帶 狀形式薄精細間距)· BGA ( CSP : Chip Size Package : 晶片尺寸封裝)的剖面圖。基底捲帶25上的引線26係介 由凸塊1 1而與半導體晶片1 c導電連接。在此情形下,代 替上述L· C D驅動器電路而在半導體晶片1 c例如係形成微 處理器等之邏輯電路或者單元單位1C或者閘陣列等之 ASIC ( Application Specific 1C :特殊應用積體電路)等 多接腳的電路。銲墊PD的全部或者至少一部份係與上述 貫施形想1等相问,配置在主動區域。另外,引線26與 半導體晶片〗C的外圍側的焊錫球32導電連接。此焊錫球 32係通過基底捲帶25上的焊錫電阻28的開口部而相連 接。爲了確保焊錫球3 2的平坦性,藉由接著劑3 4而在基 底捲帶25的背面側黏貼補強材料(補強框材)33。補強 材料3 3例如係以銅爲主體之材料,爲了使對於構裝基板 的構裝後,對焊錫球3 2造成的應力變小,選擇與構裝基 板的熱膨脹係數差小的材料。變成一種基於半導體晶片 1 C和構裝基板的熱膨脹係數差所致的應力,由於基底捲 帶25而得以緩和之構造。因此,不需要構裝後的塡膠。 在本實施形態中,半導體晶片1 C的主面內的多數的 凸塊1 1之高度變得均勻,另外,各凸塊1 1的表面平坦性 高,所以可以使半導體晶片1 C的多數的凸塊1 1和基底捲 帶25上的引線26良好連接。因此,如依據本實施形態, 可以降低半導體裝置之組裝不良。 -32- 1311346 (29) (實施形態5 ) 在本實施形態中,說明例如適用於B G A ( Array :球柵陣列封裝)時之其他的例子。第5 8 Fan — In形式之t — tf. BGA(CSP)之平面圖, 係第5 8圖的X1 一 X丨線的剖面圖,第6 〇圖係丨 圖以及第59圖的重要部位放大剖面圖。另外,% I S係表示絕緣膜。 在本實施形態中,在半導體晶片1 C的 D R A M ( D y n a m i c R a n d 〇 m A c c e s s M e m 〇 r y :隨機 體)等之記憶體電路以代替上述L C D驅動器電 PD係在半導體晶片1C的中央沿著第58圖的上 列配置(所謂之中心銲墊方式),係配置在構 之周邊電路等的元件或者配線等所配置的主動區 由接著劑36而在半導體晶片1C的主面上(除了 區域外)接著有彈性體(具有彈性的樹脂)3 5。 該彈性體35上接著基底捲帶25。焊錫球32係 在基底捲帶25的通孔而與引線26導電連接。 32變成只配置在半導體晶片1C的主面下之構造 般,藉由在半導體晶片1C的主面和基底捲帶25 在彈性體3 5,在將便宜的玻璃環氧樹脂基板用 板時,也可以抑制焊錫球3 2的焊接根部的熱 外,在使引線2 6撓曲爲略S字狀的狀態下與鍀 接。藉此,可使集中在引線26和銲墊PD的接
Ball Grid 圖係例如 第59圖 顯示第58 _ 60圖之 主面形成 存取記憶 路。銲墊 下方向排 成 DRAM 域內。藉 銲墊形成 另外,在 :通過形成 此焊錫球 :。如上述 之間使存 爲構裝基 應力。另 〖墊PD連 &合部的應 -33- 1311346 (30) 力緩和。在引線26的前端的表面例如施以金(Au )電 鍍。而且,該引線26的前端和銲墊PD不介由凸塊而使 其直接接合。引線26以及銲墊PD等係以密封部27予以 密封。在此情形下,也不需要構裝後的塡膠。 在本實施形態中,半導體晶片1 C的主面內的多數的 銲墊PD之高度也變得均勻,另外,各銲墊PD的表面平 坦性高,所以可使半導體晶片1 C的多數的銲墊PD和基 底捲帶25的多數的引線26良好連接。因此,如依據本實 施形態,可以降低半導體裝置之組裝不良率。 以上’雖依據實施形態而具體說明由本發明者所完成 的發明’但是本發明並不限定於上述實施形態,在不脫離 其要旨之範圍內,不用說可有種種變更之可能性。 例如在上述實施形態中,雖設半導體裝置的銲墊下的 全部每一配線層,其銲墊區域內的配線佔有率都相等,但 是也可以爲一部份的配線層的銲墊區域內的配線佔有率成 爲相等。 另外’在上述實施形態中,雖以3層配線構造的半導 體裝置爲例’但是並不限定於此,也可以適用於具有2層 配線構造或者3層以上的配線層之半導體裝置。 另外’在上述實施形態中,雖就在構裝於構裝體前的 半導體晶片的電極銲墊接合凸塊之形式而做說明,但是並 不限定於此’例如也可以適用於不在構裝於構裝體前的半 導體晶片的電極銲墊接合凸塊,而在構裝體的配線側(例 如’基底捲帶的引線前端)接合凸塊,在將半導體晶片構 -34- 1311346 (31) 裝於構裝體時,介由凸塊而將半導體晶片的電極銲墊和構 裝體的配線連接之形式。在此情形下,與上述實施形態相 同,半導體晶片側的多數電極銲墊的高度也一致,所以可 以無不適當地使半導體晶片的多數電極銲墊和構裝體的配 線良好連接。 在以上說明中,雖就將由本發明者所完成的發明適用 於成爲其背景的利用領域之LCD驅動器電路、微處理器 或者DRAM時而做說明,但是並不限定於此,例如也可 以適用在具有 SRAM (Static Random Access Memory:靜 態隨機存取記憶體)或者快閃記憶體(EEPROM : Electric Erasable Programmable Read Only Memory:電氣可抹除 可程式唯讀記憶體)等之記憶體電路的半導體裝置或者將 記憶體電路和邏輯電路設置在同一基板的混載型半導體裝 置。 以上,如簡單說明由這些實施形態所揭示發明中的代 表性者所可以獲得的效果,則如下述: 介由使多數的電極銲墊下的各層的配線層之配線佔有 率一致,能夠使半導體晶片的主面內之多數的電極銲墊之 上面高度幾乎均勻。另外’藉由使電極銲墊下的各層的配 線層之形狀、尺寸或者配線間隔成爲相同’能夠提高電極 銲墊之上面高度的均勻性。 另外,藉由在含虛設用電極銲墊的全部之電極銲墊的 下層配置主動區域,可以使全部的電極銲墊的基底絕緣膜 上面的平坦性以及高度一致。 -35- 1311346 (32) 即藉由使配置在半導體晶片的主面的元件或者配線等 所配置的區域內之多數的電極銲墊的基底構造成爲均勻, 可以使半導體晶片的主面內的多數電極銲墊的高度幾乎均 勻。 另外’可以降低半導體晶片的電極銲墊和構裝半導體 晶片的構裝體之配線之間的接合不良,所以能夠降低構裝 半導體晶片ic時的組裝不良率。 [發明之效果] 如簡單說明由本案所揭示發明中的代表性者所可以獲 得的效果,則如下述: 即可以使半導體晶片的主面內之多數電極銲墊的高度 一致。 【圖式簡單說明】 第〗圖係本發明之一實施形態的半導體裝置之電極銲 墊的下層之配線例的重要部位平面圖。 第2圖係本發明之一實施形態的半導體裝置之電極銲 墊的下層之與第1圖相同層的配線例的重要部位平面圖。 第3圖係本發明之一實施形態的半導體裝置之電極銲 墊的下層之與第1圖以及第2圖相同層的配線例的重要部 位平面圖。 第4圖係第1圖的配線的Y1 一 Y1線的剖面圖。 第5圖係第2圖的配線的Y 2 — Y 2線的剖面圖。 -36- 1311346 P3) 第6圖係第3圖的配線的γ 3 — Y 3線的剖面圖。 第7圖係本發明之一實施形態的半導體裝置之電極銲 墊的下層之與第1圖、第2圖以及第3圖相同層的配線例 的重要部位平面圖。 第8圖係第7圖的配線的Υ4— Υ4線的剖面圖。 第9圖係本發明之一實施形態的半導體裝置之電極銲 墊的下層之配線例的重要部位平面圖。 第10圖係發明之一實施形態的半導體裝置之電極銲 墊的下層之與第9圖相同層的配線例的重要部位平面圖。 第1 1圖係發明之一實施形態的半導體裝置之電極銲 墊的下層之與第9圖以及第1 〇圖相同層的配線例的重要 部位平面圖。 第1 2圖係第9圖的配線的Υ5 — Υ5線的剖面圖。 第1 3圖係第1 0圖的配線的Υ6 — Υ6線的剖面圖。 第1 4圖係第1 1圖的配線的Υ7 _ Υ7線的剖面圖。 第15圖係本發明之一實施形態的半導體裝置之電極 銲墊的下層之配線例的重要部位平面圖。 第16圖係本發明之一實施形態的半導體裝置之電極 銲墊的下層之配線例的重要部位平面圖。 第17圖係本發明之一實施形態的半導體裝置之電極 銲墊的下層之配線例的重要部位平面圖。 第1 8圖係本發明之一實施形態的半導體裝置之電極 銲墊的下層之與第1 7圖相同層的配線例的重要部位平面 圖。 -37- 1311346 (34) 第19圖係本發明之一實施形態的半導體裝置之電極 銲墊的下層之與第1 7圖以及第1 8圖相同層的配線例的重 要部位平面圖。 第2 0圖係就銲墊區域內的下層配線的佔有率,比較 本發明者所檢討的技術(改善前)和本發明之一實施形態 (改善後)所示的說明圖。 第21圖係本發明之一實施形態的半導體裝置之電極 銲墊的下層之半導體基板的一例的重要部位平面圖。 第22圖係本發明之一實施形態的半導體裝置之與第 20圖的電極銲墊爲不同的電極銲墊之下層的半導體基板 的一例的重要部位平面圖。 第23圖係第21圖的半導體基板的Y8 — Y8線的剖面 圖。 第24圖係第22圖的半導體基板的Y9 — Y9線的剖面 圖。 第25圖係構成本發明之一實施形態的半導體裝置的 半導體晶片之一例的整體平面圖。 第26圖係本發明之一實施形態的半導體裝置的電極 銲墊的正下方之第2層配線例的重要部位平面圖。 第27圖係本發明之一實施形態的半導體裝置而與第 26圖不同的電極銲墊之正下方的第2層配線例的重要部 位平面圖。 第28圖係本發明之一實施形態的半導體裝置而與第 26圖以及第27圖不同的電極銲墊之正下方的第2層配線 -38- 1311346 (35) 例的重要部位平面圖。 第29圖係本發明之一實施形態的半導體裝置而與第 26圖〜第28圖不同的電極銲墊之正下方的第2層配線例 的重要部位平面圖。 第3 0圖係本發明之一實施形態的半導體裝置而與第 26圖〜第29圖不同的電極銲墊之正下方的第2層配線例 的重要部位平面圖。 第31圖係本發明之一實施形態的半導體裝置而與第 26圖〜第30圖不同的電極銲墊之正下方的第2層配線例 的重要部位平面圖。 第32圖係本發明之一實施形態的半導體裝置而與第 26圖相同電極銲墊的下層之第1層配線例的重要部位平 面圖。 第3 3圖係本發明之一實施形態的半導體裝置而與第 27圖相同電極銲墊的下層之第1層配線例的重要部位平 面圖。 第34圖係本發明之一實施形態的半導體裝置而與第 2 8圖相同電極銲墊的下層之第1層配線例的重要部位平 面圖。 第35圖係本發明之一實施形態的半導體裝置而與第 2 9圖相同電極銲墊的下層之第1層配線例的重要部位平 面圖。 第36圖係本發明之一實施形態的半導體裝置而與第 3 0圖相同電極銲墊的下層之第1層配線例的重要部位平 -39- 1311346 (36) 面圖。 第37圖係本發明之一實施形態的半導體裝置而與第 31圖相同電極銲墊的下層之第1層配線例的重要部位平 面圖。 第3 8圖係本發明之一實施形態的半導體裝置而與第 26圖相同電極銲墊的下層之半導體基板的主面例的重要 部位平面圖。 第39圖係本發明之一實施形態的半導體裝置而與第 27圖相同電極銲墊的下層之半導體基板的主面例的重要 部位平面圖。 第40圖係本發明之一實施形態的半導體裝置而與第 28圖相同電極銲墊的下層之半導體基板的主面例的重要 部位平面圖。 第41圖係本發明之一實施形態的半導體裝置而與第 29圖相同電極銲墊的下層之半導體基板的主面例的重要 部位平面圖。 第42圖係本發明之一實施形態的半導體裝置而與第 30圖相同電極銲墊的下層之半導體基板的主面例的重要 部位平面圖。 第4 3圖係本發明之一實施形態的半導體裝置而與第 3 1圖相同電極銲墊的下層之半導體基板的主面例的重要 部位平面圖。 第44圖係第27圖、第33圖以及第39圖的Y10 — Y 1 0線的剖面圖。 -40- 1311346 (37) 第45圖係第29圖、第35圖以及第41圖的Y11 一 Y 1 1線的剖面圖。 第46圖係第25圖所示的半導體裝置之各電極銲墊下 的各每一配線層的配線佔有率的說明圖。 第47圖係顯示第46圖的第1層配線的佔有率之棒狀 曲線圖。 第4 8圖係顯示第4 ό圖的第2層配線的佔有率之棒狀 曲線圖。 第4 9圖係液晶顯示裝置的重要部位平面圖。 第5 0圖係第4 9圖的重要部位剖面圖。 第5 1圖係第5 0圖的重要部位放大剖面圖。 第5 2圖係第5 1圖的重要部位放大剖面圖。 第5 3圖係本發明之其他實施形態的τ C Ρ的重要部位 斜視圖。 第54圖係第53圖的TCP的內引線側的重要部位放 大剖面圖。 第55圖係將第53圖的TCP構裝於液晶顯示裝置之 狀態的重要部位剖面圖。 第5 6圖係以COF將本發明之其他實施形態的半導體 # β _裝於液晶顯示裝置之狀態的重要部位剖面圖。 胃5 7圖係本發明之另外的其他實施形態之ρ an 〇ut /式的T — TF. BGA(CSP)的剖面圖。 弟58圖戲本發明之其他實施形態的Fan— In形式的 T s "p ρ u · bga ( CSP )的平面圖。 -41 - 1311346 (38) 第5 9圖係第5 8圖的X 1 — X 1線的剖面圖。 第60圖係第58圖以及第59圖的重要部位放大剖面 圖。 圖號說明 1 S :半導體基板 2 :分離部 3 :聞極驅動電路 4 :源極驅動電路 5 :液晶驅動電路
6 :靜態RAM 7 :周邊電路 8 : η型半導體區域 9 :開口部 10 :基底金屬膜 1 1 :凸塊 1 5 :液晶顯示裝置 1 6 a、1 6 b :玻璃基板 1 6 c :密封材料 16d :液晶材料 1 7 :配線 1 8 :異方性導電膜 1 8 a :絕緣性接著劑 18b :導電粒子 -42- 1311346 (39) 1 9 :撓性基板 1 9 a :基板本體 1 9 b :配線 2 0 :印刷基板 2 1 :焊錫 25 :基底捲帶 26 :弓丨線 26a :內引線 2 6b :外引線 2 7 :密封部 2 8 :焊錫電阻 2 9 :配線 3 〇 :電子零件 3 1 :焊錫凸塊 3 2 :焊錫球 3 3 :補強材料 3 4 :接著劑 3 5 :彈性體 3 6 :接著劑 PD、PD1〜PD18:電極銲墊 MXa 〜MXk、MXm、MXn、MXp 〜MXs:配線 IS、 ISa、 ISb、 IS1〜IS4:絕緣膜 Μ1 :第1層配線 M2 :第2層配線 -43 - 1311346 (40) Μ 3 :第3層配線 D: ρη接合二極體 PWL : ρ 井
Claims (1)
1311346 拾、申請專利範圍 第92 1 20708號專利申請案 中文申請專利範圍修正本 民國97年12月15日修正 1. 一種半導體裝置,其特徵爲具有: 配置於半導體晶片的主面之主動區域內的多數電極銲 墊;及配置在上述半導體晶片主面上之多數配線層’ 在上述多數配線層中,於上述多數的電極銲墊下方的 至少1個配線層中,使配置在上述多數的電極銲墊之平面 區域內的各區域的配線之佔有率成爲均勻, 在上述多數的電極銲墊的平面區域內,配置由上述半 導體晶片的元件以及配線所切離而呈浮置狀態之虛擬配 線。 2. —種半導體裝置,其特徵爲具有: 配置於半導體晶片的主面之主動區域內的多數的電極 銲墊;及配置在上述半導體晶片的主面上之多數的配線 層, 在上述多數的配線層中,於上述多數的電極銲墊下方 的每一配線層中,使配置在上述多數的電極銲墊之平面區 域內的各區域的配線之佔有率成爲均勻, 在上述多數配線層中,於上述多數的電極銲墊下方的 至少1個配線層中,使配置在上述多數的電極銲墊之平面 區域內的各區域的配線之佔有率成爲均勻, 配置在上述多數的電極銲墊之平面區域內的各區域的 1311346 配線之佔有率之偏差在1 ο %以內。 3.如申請專利範圍第1項記載之半導體裝置,其 中,配置在上述多數的電極銲墊之平面區域內的各區域的 配線之佔有率爲5 0 %以上。 4 .如申請專利範圍第1項記載之半導體裝置,其 中,配置在上述多數的電極銲墊之平面區域內的各區域的 配線之佔有率之偏差在5 %以內。 5. —種半導體裝置,其特徵爲具有: 配置於半導體晶片的主面之主動區域內的多數的電極 銲墊;及配置在上述半導體晶片的主面上之多數的配線 層, 在上述多數的配線層中,於上述多數的電極銲墊下方 的至少1個配線層中,配置在上述多數的電極銲墊之平面 區域內的各區域的配線之佔有率的偏差在1 〇 %以內。 6. —種半導體裝置,其特徵爲具有: 配置於半導體晶片的主面之主動區域內的多數的電極 銲墊;及配置在上述半導體晶片的主面上之多數的配線 層, 在上述多數的配線層中,於上述多數的電極銲墊下方 的至少1個配線層中,配置在上述多數的電極銲墊之平面 區域內的各區域的配線之佔有率在5 0 %以上, 上述多數的虛擬電極銲墊中的至少1個,其面積比上 述多數的電極銲墊中的積體電路用的電極銲墊大。 7. —種半導體裝置,其特徵爲具有: -2- 1311346 配置於半導體晶片的主面之主動區域內的多數的電極 銲墊;及配置在上述半導體晶片的主面上之多數的配線 層, 上述多數的電極銲墊係包含:形成在上述半導體晶片 的主面之積體電路用電極銲墊,以及虛擬電極銲墊,在上 述積體電路用電極銲墊以及虛擬電極銲墊的下層之半導體 晶片的主面設置主動區域。 8 .如申請專利範圍第7項記載之半導體裝置,其 中,上述虛擬電極銲墊的下層之上述主動區域係虛擬主動 區域。 9 .如申請專利範圍第1項記載之半導體裝置,其 中,在上述多數的電極銲墊之各個將凸塊電極予以接合。 10. 如申請專利範圍第1項記載之半導體裝置,其 中,在配置於上述多數的電極銲墊的平面區域內之配線的 一部份形成配線去除部份。 11. 如申請專利範圍第1項記載之半導體裝置,其 中’在上述半導體晶片的主面形成液晶顯示裝置驅動用電 路。 1 2 .如申請專利範圍第1項記載之半導體裝置,其 中’在上述主動區域內的半導體晶片形成半導體元件。 13. —種半導體裝置之製造方法,其特徵爲具有: (a )在半導體基板的主面形成分離部以及主動區域 的工程;及(b)在上述半導體基板的主面上形成多數的 配線層的工程;及(c )在上述多數的配線層中,形成覆 -3- 1311346 蓋最上層的配線之絕緣膜後,藉由在該絕緣膜 區域內形成使上述最上層的配線的一部份露出 以形成多數的電極銲墊的工程, 具有:在上述多數的配線層中,於上述多 墊下方之至少1個配線層中,形成使上述多數 的平面區域內之配線的佔有率變爲均勻之配線 配置在上述多數的電極銲墊之平面區域內 配線的佔有率的偏差在5 %以內。 14. 一種半導體裝置之製造方法,其特徵 (a)在半導體基板的主面形成分離部以 的工程;及(b)在上述半導體基板的主面上 配線層的工程;及(c )在上述多數的配線層 蓋最上層的配線之絕緣膜後,藉由在該絕緣膜 區域內形成使上述最上層的配線的一部份露出 以形成多數的電極銲墊的工程, 具有:在上述多數的配線層中,於上述多 墊下方的每一配線層,形成使上述多數的電極 區域內之配線的佔有率變得均勻之配線的工程 在上述多數配線層中,於上述多數電極銲 少1個配線層中,使上述多數電極銲墊的平面 線的佔有率變爲均勻, 配置在上述多數的電極銲墊之平面區域內 配線的佔有率在5 0 %以上, 配置在上述多數的電極銲墊之平面區域內 中,於主動 的開口部, 數的電極銲 的電極銲墊 的工程; 的各區域之 爲具有: 及主動區域 形成多數的 中,形成覆 中,於主動 的開口部, 數的電極銲 銲墊的平面 墊下方之至 區域內之配 的各區域之 的各區域之 -4 - 1311346 配線的佔有率的偏差在1 0%以內。 15. —種半導體裝置之製造方法,其特徵爲具有: (a)在半導體基板的主面形成分離部以及主動區域 的工程;及(b)在上述半導體基板的主面上形成多數的 配線層的工程;及(c )在上述多數的配線層中,形成覆 蓋最上層的配線之絕緣膜後,藉由在該絕緣膜中,於主動 區域內形成使上述最上層的配線的一部份露出的開口部, 以形成多數的電極銲墊的工程, 上述多數的配線層係形成爲,在上述多數的電極銲墊 之下方的至少1個配線層中,上述多數的電極銲墊之平面 區域內的配線之佔有率的偏差在1 0 %以內。 16. —種半導體裝置之製造方法,其特徵爲具有: (a)在半導體基板的主面形成分離部以及主動區域 的工程;及(b)在上述半導體基板的主面上形成多數的 配線層的工程;及(c)在上述多數的配線層中,形成覆 蓋最上層的配線之絕緣膜後,藉由在該絕緣膜中,於主動 區域內形成使上述最上層的配線的一部份露出的開口部, 以形成多數的電極銲墊的工程, 上述多數的配線層係形成爲,在上述多數的電極銲墊 之下方的至少1個配線層中,上述多數的電極銲墊之平面 區域內的配線之佔有率在5 0 %以上。 17. —種半導體裝置之製造方法,其特徵爲具有: (a )在半導體基板的主面形成分離部以及主動區域 的工程;及(b)在上述半導體基板的主面上形成多數的 -5- 1311346 配線層的工程;及(C )在上述多 蓋最上層的配線之絕緣膜後,藉由 區域內形成使上述最上層的配線的 以形成多數的電極銲墊的工程, 上述多數的電極銲墊係包含: 的主面之積體電路用電極銲墊,以 述積體電路用電極銲墊以及虛擬電 基板的主面設置上述主動區域。 1 8 .如申請專利範圍第1 7項 造方法,其中,上述虛擬電極銲墊 虛擬主動區域。 1 9 .如申請專利範圍第1 3項 造方法,其中,在上述(c)工程 合在上述多數的電極銲墊的工程。 2 0 .如申請專利範圍第1 9項 造方法,其中,具有整批壓接接合 凸塊電極和玻璃基板的配線之工程 2 1 .如申請專利範圍第1 9項 造方法,其中,具有介由上述凸塊 數的電極銲墊和設置於捲帶之引線 2 2 .如申請專利範圍第1 3項 製造方法,其中,在上述多數的電 成虛擬配線。 2 3 .如申請專利範圍第1 3項 數的配線層中,形成覆 在該絕緣膜中,於主動 一部份露出的開口部, 形成在上述半導體基板 及虛擬電極銲墊,在上 極銲墊的下層之半導體 記載之半導體裝置之製 下層的上述主動區域係 記載之半導體裝置之製 後,具有將凸塊電極接 記載之半導體裝置之製 上述多數的電極銲墊的 〇 記載之半導體裝置之製 電極而整批接合上述多 的工程。 所記載之半導體裝置之 極銲墊的平面區域內形 所記載之半導體裝置之 -6- 1311346 製造方法’其中’在配置於上述多數的電極銲墊的平面區 域內之配線的一部份形成配線去除部份。 24. —種半導體裝置之製造方法,其特徵爲具有: (a)在半導體基板的主面形成分離部以及主動區域 的工程;及(b)在上述半導體基板的主面上形成多數的 配線層的工程;及(c)在上述多數的配線層中,形成覆 蓋最上層的配線之絕緣膜後,藉由在該絕緣膜中,於主動 區域內形成使上述最上層的配線的一部份露出的開口部, 以形成多數的電極銲墊的工程, 上述多數的電極銲墊係包含:形成在上述半導體基板 的主面之積體電路用電極銲墊,以及虛擬電極銲墊,在上 述積體電路用電極銲墊以及虛擬電極銲墊的下層之半導體 基板的主面設置主動區域。 25 .如申請專利範圍第24項記載之半導體裝置之製 造方法,其中,上述虛擬電極銲墊下層的上述主動區域係 虛擬上述主動區域。 26 .如申請專利範圍第1 3項之半導體裝置之製造方 法,其中, 在上述多數配線層之中,使至少上述多數電極焊墊被 配置的配線層之底部,藉由化學機械硏磨法施予硏磨。 27 ·如申請專利範圍第1 3項之半導體裝置之製造方 法,其中, 在上述半導體基板主面形成液晶顯示裝置驅動用電 路。 1311346 28. 如申請專利範圍第13項之半導體裝置之製造方 法,其中, 在上述主動區域形成半導體元件。 29. —種半導體裝置之製造方法,其特徵爲具有: (a) 準備:具有配置在半導體基板的主面之主動區 域內的多數的電極焊墊;及配置在上述半導體基板的主面 上之多數配線層;及位在上述多數的電極銲墊之各個的凸 塊電極, 上述多數的配線層爲,在上述多數電極焊墊更下方之 至少1個配線層中,使配置於上述多數的電極銲墊之平面 區域內的各區域之配線的佔有率成爲均勻而構成的半導體 晶片之工程;及 (b) 壓接接合上述多數的電極銲墊的凸塊電極和玻 璃基板的配線之工程。 3〇 .如申請專利範圍第29項記載之半導體裝置之製 造方法,其中,於上述半導體基板的上述多數的電極銲墊 的形成面,和與其相面對之上述玻璃基板的配線形成面之 間存在異方性導電膜之狀態下,整批壓接接合上述多數的 電極銲墊的凸塊電極和玻璃基板的配線。 3 1 ·如申請專利範圍第2 9項記載之半導體裝置之製 造方法,其中,上述玻璃基板係搭載有液晶面板的玻璃基 板。 1311346 柒、(一)、本案指定代表圖為:第20圖 (二)、本代表圖之元件代表符號簡單說明: PD1〜PDn:電極銲墊 Μ1 :第1層配線 M2 :第2層配線 Μ 3 :第3層配線 捌、本案若有化學式時,請揭示最能顯示發明特徵的化學 式:
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- 2003-08-21 KR KR1020030057772A patent/KR101072718B1/ko active IP Right Grant
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CN104241230B (zh) * | 2013-06-07 | 2018-11-09 | 辛纳普蒂克斯日本合同会社 | 半导体器件、显示装置模块及其制造方法 |
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US20160284652A1 (en) | 2016-09-29 |
KR20040019902A (ko) | 2004-03-06 |
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US7759804B2 (en) | 2010-07-20 |
JP4445189B2 (ja) | 2010-04-07 |
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US20060289998A1 (en) | 2006-12-28 |
TW200403776A (en) | 2004-03-01 |
US20140159245A1 (en) | 2014-06-12 |
US7102223B1 (en) | 2006-09-05 |
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