CN104241230A - 半导体器件、显示装置模块及其制造方法 - Google Patents

半导体器件、显示装置模块及其制造方法 Download PDF

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Publication number
CN104241230A
CN104241230A CN201410250149.5A CN201410250149A CN104241230A CN 104241230 A CN104241230 A CN 104241230A CN 201410250149 A CN201410250149 A CN 201410250149A CN 104241230 A CN104241230 A CN 104241230A
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China
Prior art keywords
projection
power line
semiconductor chip
long
pair
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CN201410250149.5A
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CN104241230B (zh
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中村寿雄
中込祐一
铃木进也
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Synaptics Inc
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Renesas SP Drivers Inc
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Abstract

本发明提供半导体器件、显示装置模块及其制造方法。半导体器件包括：具有主面的半导体芯片(10)，该主面具有相互平行的一对长边(10a，10b)和与该一对长边正交的一对短边(10c，10d)；第一凸块(11)，被布置在半导体芯片中的沿着一对长边中的一个(10a)定位的第一凸块安置区域(13)中；第二凸块(12)，被布置在半导体芯片(10)中的沿着一对长边中的另一个(10b)定位的第二凸块安置区域(14)中；第一电力线(22)，被布置在第一凸块安置区域(13)和第二凸块安置区域(14)之间的区域中，且在平行于一对长边(10a，10b)的方向上延伸；以及第三凸块(24)，其被集成在半导体芯片(10)上。第三凸块(24)中的每一个提供第一电力线(22)的短路。

Description

半导体器件、显示装置模块及其制造方法
技术领域
本发明涉及半导体器件、显示装置模块及其制造方法，特别地，涉及一种具有适合于倒装芯片安装的凸块的半导体器件。
背景技术
诸如玻璃上芯片(COG)安装的倒装芯片安装，是一种被用于电子电器的尺寸缩小的广泛使用的安装技术。倒装芯片安装是其中凸块被形成在半导体芯片上并且利用在被集成在半导体芯片中的电路和被形成在电路板上的互连之间的凸块实现电气连接的技术。例如，在下面的专利文献中公开该倒装芯片安装。
日本专利申请公布No.2007-103848A公开了其中与凸块电极的尺寸相比焊盘的尺寸被缩小从而缩小半导体芯片的尺寸的技术。
日本专利申请公布No.2011-29396A公开了其中凸块电极具有连接两个信号互连的功能的半导体器件。
国际公布No.WO2010/146884A公开了一种半导体器件，其中一组虚拟凸块被提供在沿着一个长边布置的输入凸块阵列和沿着另一长边布置的输出凸块阵列之间。在此，虚拟凸块是不具有提供电气连接功能的凸块。在该专利文献中，公开了一种技术，用于通过利用虚拟凸块阻挡ACF(各向异性导电膜)树脂朝着短边的流动获得ACF树脂朝着芯片的角部的充分流动，从而抑制由ACF树脂的不充分流动产生的连接故障。
发明内容
作为发明人对具有凸块的半导体器件的研究的结果，发明人已经发现凸块能够被用于减少电力线(在本申请中，意指递送电源电压的互连或者保持在电路接地电平的互连)的有效电阻。因此，本发明的一个目的是为了提供用于减少电力线的有效电阻的技术。
在本发明的方面中，半导体器件包括：半导体芯片，该半导体芯片具有主面，该主面具有相互平行的一对长边和与一对长边正交的一对短边；第一凸块，该第一凸块被布置在半导体芯片中的沿着一对长边中的一个长边定位的第一凸块安置区域中；第二凸块，该第二凸块被布置在半导体芯片中的沿着一对长边中的另一个长边定位的第二凸块安置区域中；第一电力线，该第一电力线被设置在第一凸块安置区域和第二凸块安置区域之间的区域中，该第一电力线在平行于一对长边的方向上延伸；以及第三凸块，该第三凸块被集成在半导体芯片上。第三凸块中的每一个提供第一电力线的短路。
这样构造的半导体器件适合于到显示面板的玻璃衬底上的倒装芯片安装(或者COG安装)。
附图说明
结合附图，从下面的描述中本发明的以上和其它优点和特征将会更加显而易见，其中：
图1是图示在本发明的一个实施例中的半导体器件的示例性结构的平面视图；
图2是示出在本实施例中的VDD电力线、GND电力线以及凸块的示例性布置的平面视图；
图3是图示在图2中指示的A-A截面上的本实施例中的半导体器件的示例性结构的截面视图；
图4是图示在图2中指示的B-B截面上的本实施例中的半导体器件的示例性结构的截面视图；
图5是图示本实施例中的显示装置模块的示例性结构的平面视图；
图6是部分地图示在本实施例中的显示装置模块的结构的截面视图；
图7是图示在本实施例中的显示装置的制造方法的图；
图8是图示对于当没有凸块被提供在半导体芯片的中央部分时的情况在COG安装工艺中通过将压力施加到半导体芯片的后面引起的半导体芯片的变形的示意图；
图9是图示在COG安装工艺中通过将压力施加到半导体芯片的后面引起的本实施例中的半导体芯片的变形的示意图；
图10是图示本实施例中的半导体器件的修改的平面视图；以及
图11是图示本实施例中的半导体器件的另一修改的平面视图。
具体实施方式
现在在此将会参考说明性实施例描述本发明。本领域的技术人员会认识到使用本发明的教导能够完成可替选的实施例并且本发明不限于为了解释性目的而图示的实施例。
图1是图示根据本发明的一个实施例的半导体器件的示例性结构的平面视图。本实施例的半导体器件，被配置为驱动LCD(液晶显示器)面板的驱动器IC(集成电路)，包括半导体芯片10。半导体芯片10具有矩形或者大体上矩形的主面，该主面具有一对长边10a、10b和短边10c和10d。长边10a和10b相互平行，并且短边10c和10d相互平行。长边10a和10b与短边10c和10d正交。在下面的描述中，XY直角坐标系可以被使用，其中X轴被定义为平行于长边10a和10b并且Y轴被定义为平行于短边10c和10d。应注意的是，虽然在图1中半导体芯片10的主面被图示为矩形，但是半导体芯片10的主面大体上可以是矩形的，其角部成斜角。
半导体芯片10在主面上包括多个凸块11和12。凸块11被布置在沿着长边10a定位的输入侧凸块安置区域13中并且被用作从外部装置(例如，中央处理单元(CPU))接收信号的输入端子。在本实施例中，凸块11包括：电源凸块11a，该电源凸块11a外部地接收外部电源电压VDDIN；和接地凸块11b，该接地凸块11b被用作接地端子(保持在电路接地电平GND的端子)。另一方面，凸块12被布置在沿着长边10b定位的输出侧凸块安置区域14中并且被用作将信号外部地输出到LCD面板(未示出)的输出端子。例如，凸块11和12均可以包括膜堆，该膜堆包括被形成在其上的凸块下金属化(UBM)层和导电层。UBM层可以是由通常使用的材料形成；例如，包括被形成在其上的钛钨(Ti-W)膜和金(Au)膜的膜堆可以被用作UBM层。导电层可以是由低电阻率材料形成；例如，通过金的电镀形成的金膜可以被用作导电层。凸块11和12具有相同的高度并且同时由相同的形成步骤形成。
因为LCD面板通常包括多根源极线和栅极线，所以作为驱动LCD面板的驱动器IC操作的半导体芯片10包括大量的输出端子，即，大量的凸块12。因此应注意的是，在本实施例中长边10a和10b的长度远远大于短边10c和10d的长度。
各种其它的电路被集成在半导体芯片10的输入侧凸块安置区域13和输出侧凸块安置区域14之间的区域中。在本实施例中，液晶驱动电路15、逻辑电路16、源极驱动电路17、栅极驱动电路18以及外围电路19被集成在半导体芯片10中。液晶驱动电路15生成被用于驱动LCD面板的各种模拟信号。逻辑电路16执行对于驱动LCD面板所要求的各种逻辑操作。源极驱动电路17驱动LCD面板的源极线(经常被称为数据线或者信号线)，并且栅极驱动电路18驱动LCD面板的栅极线(经常被称为地址线或者扫描线)。当其中驱动栅极线的面板中栅极(GIP)电路被集成在LCD面板中的配置被使用时，栅极驱动电路18可以将控制信号供应给GIP电路。外围电路19生成对于操作液晶驱动电路15、逻辑电路16、源极驱动电路17以及栅极驱动电路18所必需的各种电压和信号。在本实施例中，外围电路19包括电源电路20，该电源电路20根据被供应到电源凸块11a的外部电源电压VDDIN生成电源电压VDD。
电力线组21被设置在半导体芯片10的中央部分(即，在输入侧凸块安置区域13和输出侧凸块安置区域14之间的区域中)。电力线组21包括多个VDD电力线22和多个GND电力线23。VDD电力线22被馈送有来自于电源电路20的电源电压VDD。GND电力线23被电气地连接到被接地的凸块11b并且保持在电路接地电平GND。
在本发明中，所有的VDD电力线22和GND电力线23被设置为在平行于长边10a和10b的方向(即，X轴方向)中延伸。因为本实施例中的半导体芯片10被构造使得长边10a和10b远远比短边10c和10d长，所以对于将电源电压VDD和电路接地电平供应到被集成在半导体芯片10中的相应的电路，其中VDD电力线22和GND电力线23在平行于长边10a和10b的方向上延伸的布置是有效的。
详细地讲，VDD电力线22被用于将通过电源电路20生成的电源电压VDD供应到液晶驱动电路15、逻辑电路16、源极驱动电路17、栅极驱动电路18以及外围电路19。在图1中图示的结构中，两个VDD电力线22被集成在半导体芯片10中。类似地，GND电力线23被用于将电路接地电平供应到液晶驱动电路15、逻辑电路16、源极驱动电路17、栅极驱动电路18以及外围电路19。在图1中示出的结构中，两个GND电力线23被集成在半导体芯片10中。在本实施例中，VDD电力线22和GND电力线23被交替地布置在Y轴方向上。
另外，多个凸块24和25被设置在半导体芯片10的中央部分。凸块24和25被安置在输入侧凸块安置区域13和输出侧凸块安置区域14之间的区域中。凸块24和25具有与被安置在输入侧凸块安置区域13中的凸块11和被安置在输出侧凸块安置区域14中的凸块12的高度相同的高度。同时在相同的形成步骤形成凸块24和25。
图2是图示VDD电力线22、GND电力线23以及凸块24和25的布置的平面视图。如在图2中所图示，通过凸块24，VDD电力线22被相互短路。换言之，凸块24均被用作用于短路VDD电力线22的分路。图3是图示在图2中指示的A-A截面上的本实施例的半导体芯片10的结构，特别是凸块24的结构的截面视图。
如在图3中所图示，VDD电力线22和GND电力线23都被形成在中间层电介质膜31上。中间层电介质膜31可以是由例如氧化硅形成。在本实施例中，VDD电力线22和GND电力线23位于最上面的互连层中。
VDD电力线22和GND电力线23被覆盖有表面保护层(或者钝化层)32。表面保护层32可以是由例如氮化硅形成。穿过表面保护层32形成达到相应的VDD电力线22的上面的通孔32a。
各个凸块24被定位在VDD电力线22和GND电力线23上方的上位处。在此，术语“在…上方的上位处(或者在…上方的该上位)”意指被定位为相对于某物与半导体芯片10的半导体衬底(或者硅衬底)分离开。详细地讲，在本实施例中，凸块24被形成表面保护层32上。各个凸块24包括UBM(凸块下金属化)层33，其被形成在表面保护层32的上面上；和在UBM层33的上面上的导电层34，该导电层34由诸如金(Au)的低电阻率的材料形成。UBM层33可以是由通常使用的材料形成。例如，UBM层33可以包括膜堆，该膜堆包括被形成在其上的钛钨(Ti-W)膜和金(Au)膜。可以通过金的电镀形成导电层34。
各个凸块24被连接到通孔32a中的VDD电力线22。详细地讲，各个凸块24的UBM层33被形成为覆盖通孔32a的侧面和底面，并且导电层34被形成为插入通孔32a。这样构造的凸块24均提供VDD电力线22的短路。
再次参考图2，通过凸块25相互短路GND电力线23。换言之，凸块25均被用作用于短路GND电力线23的分路。图4是图示在图2中指示的B-B截面上的本实施例中的半导体芯片10的结构，特别是凸块25的结构的截面图。
如在图4中所图示，凸块25被形成在表面保护层32上。在本实施例中，各个凸块25包括被形成在表面保护层32的上面上的UBM层35和在UBM层35的上面上的由诸如金(Au)的低电阻率材料形成的导电层36。UBM层35可以是由通常已知的材料形成。例如，UBM层35可以包括膜堆，该膜堆包括被形成在其上的钛钨(Ti-W)膜和金(Au)膜。可以通过金的电镀形成导电层36。
穿过表面保护层32形成到达相应的GND电力线23的上面的通孔32b，并且凸块25均被连接到通孔32b中的GND电力线23。详细地讲，各个凸块25的UBM层35被形成为覆盖通孔32b的侧面和底面，并且导电层36被形成为插入通孔32b。通过这样构造的凸块25短路GND电力线23。
在本实施例中，在VDD电力线22之间提供电力连接的凸块24均被设置为与GND电力线23上方的上位处的GND电力线23相交。类似地，在GND电力线23之间提供电力连接的凸块25均被设置为与VDD电力线22上方的上位处的VDD电力线22相交。在本实施例中这样的结构与其中VDD电力线22和GND电力线23被交替布置的布局有关。其中VDD电力线22和GND电力线23被交替布置的布局有效地增加在VDD电力线22和GND电力线23之间的电容，并且从而稳定VDD电力线22上的电源电压VDD。为了在其中VDD电力线22和GND电力线23被交替布置的布局中在VDD电力线22之间提供电气连接，凸块24均被设置为与GND电力线23上方的上位处的GND电力线23相交。类似地，为了在其中VDD电力线22和GND电力线23被交替布置的布局中在GND电力线23之间提供电气连接，凸块25均被设置为与VDD电力线22上方的上位处的VDD电力线22相交。
本发明中的半导体芯片10的结构的优点之一是，由于凸块24和25的使用减少了电力线组21的有效电阻。更加具体地，在本实施例中的半导体芯片10中，通过利用凸块24短路VDD电力线22，减少VDD电力线22的总电阻。这有效地提高了半导体芯片10的噪声容限。不同于被集成在半导体芯片10内部的金属互连(即，被集成在表面保护层32下方的金属互连)，凸块24能够是由低电阻材料(诸如金)形成，并且凸块24的厚度能够被容易地增加。这意味着凸块24的电阻能够被减少。因此，与当通过使用被集成在半导体芯片10内部的金属互连短路VDD电力线22时的情况相比较，通过使用凸块24通过短路VDD电力线22能够进一步减少VDD电力线22的总电阻。
在此应注意的是，在其中凸块24被用作在VDD电力线22之间提供短路的分路的结构中，重要的是，在多个位置处短路VDD电力线22，即，多个凸块24被用于提供VDD电力线22的短路。如果在单个位置处VDD电力线22被短路，则由于跨过VDD电力线22的电压降，可能引起取决于位置的电源电压VDD的不平坦。
类似地，凸块25的使用有效地减少GND电力线23的总电阻，提高噪声容限。在此应注意的是，在其中凸块25被用作在GND电力线23之间提供短路的分路的结构中，重要的是，在多个位置处GND电力线23被短路，即，多个凸块25被用于提供GND电力线23的短路，与凸块24的情况一样。
本实施例中的上述半导体芯片10适合于通过使用COG安装被安装在显示面板模块上。如稍后详细地描述的，被设置在半导体芯片10的中央部分的凸块24和25有效地抑制COG安装工艺中的半导体芯片10的变形，特别在当半导体芯片10的厚度被减少并且短边10c和10d的长度被增加时的情况下。在下面，给出其中通过COG安装和COG安装的工艺半导体芯片10被安装在LCD面板上的显示装置模块的详细描述。
图5是图示本实施例中的显示装置模块40的示例性结构的平面视图。如在图5中所图示，显示装置模块40包括LCD面板41和FPC(柔性印制电路板)42。半导体芯片10，用作驱动LCD面板41的驱动器IC，通过COG安装被安装在LCD面板41上。通过半导体芯片10驱动LCD面板41以在LCD面板41的显示部41a上显示期望的图像。
图6是部分地图示显示装置模块40的结构的截面图。如在6中所图示，LCD面板41包括玻璃衬底43和44。玻璃衬底43和44由间隔物45来保持，并且以跨过在该两者之间所夹的小间隙的方式来彼此相对置。互连46(示出一个)和互连47(示出一个)被形成在玻璃衬底43的表面上。互连46被电气地连接到半导体芯片10的凸块11(用作输出端子)，并且互连47被电气地连接到凸块12(用作输入端子)。
通过使用各向异性导电材料的COG安装，半导体芯片10被安装在玻璃衬底43上。各向异性导电材料主要由导电颗粒和其中导电颗粒被分散的粘合剂(结合剂)组成。当在膜被加热的情况下压力在膜厚度方向上被施加到各向异性导电材料的膜时，膜被安置在其中膜在膜厚度方向上导电并且在平面内方向上绝缘的状态。在此，术语“主要”意指可能添加有次要材料。在本实施例中，ACF(各向异性导电膜)51被用作各向异性导电材料，并且利用ACF51，半导体芯片10被结合到玻璃衬底43。在此，半导体芯片10的凸块11经由被包括在ACF51中的导电颗粒被电气地连接到互连46。类似地，凸块12经由被包括在ACF51中的导电颗粒被电气地连接到互连47。
利用ACF52，FPC42被结合到玻璃衬底43。经由被包括在ACF52中的导电颗粒，被形成在FPC42的表面上的互连48(示出一个)被电气地连接到互连47。经由ACF52、互连47以及ACF51，互连48被电气地连接到半导体芯片10的凸块12。这意指能够将信号从互连48馈送到半导体芯片10的凸块12。
图7图示在本实施例中的显示装置模块40的示例性制造方法，更加具体地，为了将半导体芯片10安装在LCD面板41的玻璃衬底43上执行的一系列步骤。
用于将半导体芯片10安装在LCD面板41的工艺以将ACF51粘贴在玻璃衬底43上开始(步骤1)。ACF51被粘贴在半导体芯片10被结合到玻璃衬底43的位置处。
随后在其中半导体芯片10被定位在玻璃衬底43的预期位置的状态下将半导体芯片10临时结合到ACF51(步骤2)。在此步骤中，以相对小的压力靠着ACF51按压半导体芯片10；在半导体芯片10的凸块11和玻璃衬底43上的互连46之间以及在凸块12和互连47之间没有建立电气连接。
随后进行最终结合(步骤3)。详细地讲，在玻璃衬底43被加热的情况下，以相对大的压力靠着玻璃衬底43按压半导体芯片10，并且从而利用ACF51半导体芯片10被结合到玻璃衬底43。结果，经由被包括在ACF51中的导电颗粒，半导体芯片10的凸块11被电气地连接到互连46，并且凸块12以相同的方式被电气地连接到互连47。
应注意的是，当在沿着短边10c和10d的方向上半导体芯片10具有极其缩小的厚度和增加的长度时，在最终结合(在步骤3)中半导体芯片10的变形可能成为问题。在半导体芯片10主要由硅衬底形成的情况下，例如，当半导体芯片10的厚度等于或者小于200μm并且短边10c和10d的长度等于或者大于1mm时，半导体芯片10的变形可能成为问题。然而，在本实施例中，凸块24和25，被设置在半导体芯片10的中央部分处，有效地抑制最终结合中的半导体芯片10的变形。
让我们考虑该情况，例如，半导体芯片仅包括沿着半导体芯片的长边10a和10b设置的凸块11和12并且在中央部分处没有设置凸块，如在图8中所图示；通过图8中的数字100表示这样构造的半导体芯片。当在最终结合中大的压力被施加到半导体芯片100的背面(在其上没有设置凸块11和12的面)时，半导体芯片100的中央部分被按压并且这可能引起半导体芯片10的变形。
在本实施例的半导体器件中，相反地，即使当在最终结合中压力被施加到半导体芯片10的背面时，因为由于被设置在中央部分的凸块24和25导致压力被散布，所以在半导体芯片10的中央部分的变形被有效地抑制，如在图9中所图示。更加具体地，当压力被施加到半导体芯片10的背面时，凸块24和25靠着LCD面板41的玻璃衬底43被按压，用作支撑半导体芯片10的中央部分的柱。结果，凸块24和25散布被施加到背面的压力，抑制在中央部分的半导体芯片10的变形。
如这样描述的，在本实施例中的半导体芯片中，多个凸块24和25被安置在半导体芯片10的中央部分处(更加具体地，在输入侧凸块安置区域13和输出侧凸块安置区域14之间的区域中)。通过多个凸块24短路电力线组21的VDD电力线24，并且通过多个凸块25短路GND电力线23。这样的结构有效地减少VDD电力线22和GND电力线23的总电阻，提高了噪声容限。
而且，本实施例中的半导体器件的结构，其中凸块24和25被设置在半导体芯片10的中央部分，有效地抑制COG安装的工艺中半导体芯片的变形。
虽然在上面具体地描述了本发明的优选实施例，但是本发明不应被解释为受到上述实施例的限制；对于本领域的技术人员来说显然的是，通过各种修改可以实现本发明。
例如，在本实施例电力线组21和凸块24和25的布置可以被不同地修改。图10和图11是图示根据本发明的半导体器件的修改的平面视图。如在图10中所图示，例如，多个电力线组21被设置，并且为各个电力线组21设置多个凸块24和多个凸块25。图10图示其中通过数字21A和21B表示的两个电力线被设置的结构。电力线组21A和21B被布置在Y轴方向(平行于半导体芯片10的短边10c和10d的方向)中，并且电力线组21A和21B中的每一个包括多个VDD电力线22和多个GND电力线23。在电力线组21A和21B中的每一个中，通过多个凸块24短路VDD电力线22，并且通过多个凸块25短路GND电力线23。
如在图11中所图示，相对于跨过电力线组21B的凸块24和25的位置，可以在X轴方向(平行于半导体芯片10的长边10a和10b的方向)上移动跨过电力线组21A的凸块24和25的位置。凸块24和25的这种布置优选用于散布被施加到半导体芯片10的背面的压力，并且从而进一步抑制半导体芯片10的变形。
虽然在上述实施例中各个凸块24被设置为短路两个VDD电力线22，电力线组21(或者电力线组21A和21B中的每一个)可以包括三个或者多个VDD电力线22，各个凸块24被设置为短路三个或者多个VDD电力线22。类似地，电力线组21(或者电力线组21A和21B中的每一个)可以包括三个或者多个GND电力线23，各个凸块25被设置为短路三个或者多个GND电力线23。
虽然在上述实施例中各个凸块24被图示为被直接地连接到VDD电力线22，但是各个凸块24可以经由另一互连层(可以包括焊盘)被电气地连接到VDD电力线22。类似地，各个凸块25可以经由另一互连层(可以包括焊盘)被电气地连接到GND电力线23。
而且，虽然在上面描述了驱动LCD面板的驱动器IC的实施例，但是本发明可以被应用于驱动除了LCD面板的显示面板的驱动器IC(例如，有机发光显示(OLED)面板)。此外，根据本发明的半导体器件可以被实现为除了驱动显示面板的驱动器IC之外的各种装置。

Claims (11)

1.一种半导体器件，包括：
半导体芯片，所述半导体芯片具有主面，所述主面具有相互平行的一对长边和与所述一对长边正交的一对短边；
多个第一凸块，所述多个第一凸块被布置在所述半导体芯片中的沿着所述一对长边中的一个长边定位的第一凸块安置区域中；
多个第二凸块，所述多个第二凸块被布置在所述半导体芯片中的沿着所述一对长边中的另一个长边定位的第二凸块安置区域中；
多个第一电力线，所述多个第一电力线被设置在所述第一凸块安置区域和所述第二凸块安置区域之间的区域中，所述多个第一电力线在平行于所述一对长边的方向上延伸；以及
多个第三凸块，所述多个第三凸块被集成在所述半导体芯片上，
其中，所述多个第三凸块中的每一个凸块提供所述多个第一电力线的短路。
2.根据权利要求1所述的半导体器件，进一步包括：
多个第二电力线，所述多个第二电力线被设置在所述第一凸块安置区域和所述第二凸块安置区域之间的区域中，所述多个第二电力线在平行于所述一对长边的方向上延伸；和
多个第四凸块，所述多个第四凸块被集成在所述半导体芯片上，
其中，所述多个第一电力线被馈送电源电压，
其中，所述多个第二电力线具有电路接地电平，并且
其中，所述多个第四凸块中的每一个凸块提供所述多个第二电力线的短路。
3.根据权利要求2所述的半导体器件，其中，在平行于所述一对短边的方向上，交替地布置所述多个第一电力线和所述多个第二电力线。
4.根据权利要求3所述的半导体器件，
其中，所述多个第三凸块中的每一个凸块被定位在所述第二电力线上方的上位处，并且
其中，所述多个第四凸块中的每一个凸块被定位在所述第一电力线的上方的上位处。
5.根据权利要求2至4中的任意一项所述的半导体器件，其中，
所述第一、第二、第三以及第四凸块具有相同的高度。
6.一种显示装置模块，包括：
显示面板；和
半导体器件，所述半导体器件被结合在所述显示面板的玻璃衬底上，
其中，所述半导体器件包括：
半导体芯片，所述半导体芯片具有主面，所述主面具有相互平行的一对长边和与所述一对长边正交的一对短边；
多个第一凸块，所述多个第一凸块被布置在所述半导体芯片中的沿着所述一对长边中的一个长边定位的第一凸块安置区域中；
多个第二凸块，所述多个第二凸块被布置在所述半导体芯片中的沿着所述一对长边中的另一个长边定位的第二凸块安置区域中；
多个第一电力线，所述多个第一电力线被设置在所述第一凸块安置区域和所述第二凸块安置区域之间的区域中，以在平行于所述一对长边的方向上延伸；以及
多个第三凸块，所述多个第三凸块被集成在所述半导体芯片上，
其中，所述半导体芯片被结合到所述玻璃衬底，使得所述多个第一凸块、所述多个第二凸块以及所述多个第三凸块与所述玻璃衬底相对置，
其中，所述多个第一凸块被连接到形成在所述玻璃衬底上的第一互连，
其中，所述多个第二凸块被连接到形成在所述玻璃衬底上的第二互连，并且
其中，所述多个第三凸块中的每一个凸块提供所述多个第一电力线的短路。
7.根据权利要求6所述的显示装置模块，其中，
通过使用主要由导电颗粒和其中所述导电颗粒被分散的粘合剂所组成的各向异性导电材料，来使所述半导体芯片结合到所述玻璃衬底。
8.根据权利要求7所述的显示装置模块，
其中，所述半导体芯片的厚度等于或者小于200μm，并且
其中，所述一对短边的长度等于或者大于1mm。
9.一种制造显示装置模块的方法，包括：
将半导体器件结合到显示面板的玻璃衬底，
其中，所述半导体器件包括：
半导体芯片，所述半导体芯片具有主面，所述主面具有相互平行的一对长边和与所述一对长边正交的一对短边；
多个第一凸块，所述多个第一凸块被布置在所述半导体芯片中的沿着所述一对长边中的一个长边定位的第一凸块安置区域中；
多个第二凸块，所述多个第二凸块被布置在所述半导体芯片中的沿着所述一对长边中的另一个长边定位的第二凸块安置区域中；
多个第一电力线，所述多个第一电力线被设置在所述第一凸块安置区域和所述第二凸块安置区域之间的区域中，以在平行于所述一对长边的方向上延伸；以及
多个第三凸块，所述多个第三凸块被集成在所述半导体芯片上，
其中，所述多个第三凸块中的每一个凸块提供所述多个第一电力线的短路，
其中，所述半导体芯片被结合到所述玻璃衬底，使得所述多个第一凸块、所述多个第二凸块以及所述多个第三凸块与所述玻璃衬底相对置，并且
其中，在所述结合中，所述多个第一凸块被连接到形成在所述玻璃衬底上的第一互连，并且所述多个第二凸块被连接到形成在所述玻璃衬底上的第二互连。
10.根据权利要求9所述的方法，其中，
在所述结合中，通过使用主要由导电颗粒和其中所述导电颗粒被分散的粘合剂所组成的各向异性导电材料，来使所述半导体芯片结合到所述玻璃衬底。
11.根据权利要求10所述的方法，
其中，所述半导体芯片的厚度等于或者小于200μm，并且
其中，所述一对短边的长度等于或者大于1mm。
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