JP5539346B2 - 半導体チップおよびその実装構造 - Google Patents
半導体チップおよびその実装構造 Download PDFInfo
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- JP5539346B2 JP5539346B2 JP2011519618A JP2011519618A JP5539346B2 JP 5539346 B2 JP5539346 B2 JP 5539346B2 JP 2011519618 A JP2011519618 A JP 2011519618A JP 2011519618 A JP2011519618 A JP 2011519618A JP 5539346 B2 JP5539346 B2 JP 5539346B2
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- protruding electrode
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Description
前記底面において、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の領域に、前記底面の長辺に対して垂直方向に延びる辺を長辺とする長方形状の複数の突起電極からなる第3の突起電極群を備え、
前記第3の突起電極群に含まれる複数の突起電極は、
外部との電気的な接続がなされない電極であり、
前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする。
本発明の第1の局面に係る半導体チップが前記駆動回路として異方性導電膜を用いて前記第1の基板に実装されていることを特徴とする。
前記底面において、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の領域に、前記底面の長辺に対して垂直方向に延びる辺を長辺とする長方形状の複数の突起電極からなる第3の突起電極群を備え、
前記第3の突起電極群に含まれる複数の突起電極は、外部との電気的な接続がなされない電極であり、
前記第3の突起電極群は、前記第1の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列と前記第2の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列とを含み、
各突起電極列に含まれる複数の突起電極は、前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする。
本発明の第3の局面に係る半導体チップが前記駆動回路として異方性導電膜を用いて前記第1の基板に実装されていることを特徴とする。
前記半導体チップは、前記底面の一方の長辺に沿って配置され前記配線基板上の電気配線からの入力信号を受け取るための複数の突起電極からなる第1の突起電極群と、前記底面の他方の長辺に沿って配置され出力信号を前記配線基板上の電気配線に出力するための複数の突起電極からなる第2の突起電極群と、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の領域に配置され前記底面の長辺に対して垂直方向に延びる辺を長辺とする長方形状の複数の突起電極からなる第3の突起電極群とを備え、
前記第3の突起電極群には、少なくとも前記底面の一方の短辺近傍および他方の短辺近傍に形成された突起電極が含まれ、
前記第3の突起電極群に含まれる複数の突起電極は、前記配線基板上の電気配線との電気的な接続がなされない電極であり、
前記底面の一方の短辺近傍および他方の短辺近傍に形成された突起電極の各々の長辺は、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の距離の5分の3以上の長さであることを特徴とする。
前記第3の突起電極群には、前記底面の一方の短辺近傍に形成された突起電極と前記底面の他方の短辺近傍に形成された突起電極との間の領域に一列に配置された複数の突起電極が含まれていることを特徴とする。
前記第3の突起電極群に含まれる複数の突起電極は、前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする。
前記第3の突起電極群は、前記底面の一方の短辺近傍に形成された突起電極と前記底面の他方の短辺近傍に形成された突起電極との間の領域に、前記第1の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列と前記第2の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列とを含み、
各突起電極列に含まれる複数の突起電極は、前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする。
前記配線基板は、液晶モジュールに含まれる液晶パネルを構成する2枚の基板のうちの一方の基板であって、
前記半導体チップは、前記液晶パネルを駆動するための駆動回路であることを特徴とする。
また、半導体チップの底面において、中央部から短辺側に近づくに従い導電性樹脂の流れが効果的に阻害される。一方、半導体チップの底面において、短辺側から中央部に近づくに従い第3の突起電極の占有面積が小さくなる。以上より、半導体チップの設計自由度をある程度確保しつつ、導電性樹脂の流量不足に起因する接続不良の発生が抑制される。
また、第3の突起電極群に含まれる複数の突起電極は、電気的接続の機能を有していない。このため、それら第3の突起電極群に含まれる複数の突起電極を介して電気信号のやりとりはなされないので、配線パターン等を考慮することなく、導電性樹脂の流れを阻害するための複数の突起電極を半導体チップの底面に配置させることができる。これにより、チップサイズを大きくすることなく、半導体チップにおける端子間の狭ピッチ化が可能となる。
本発明の第7の局面によれば、半導体チップの底面において、中央部から短辺側に近づくに従い導電性樹脂の流れが効果的に阻害される。一方、半導体チップの底面において、短辺側から中央部に近づくに従い第3の突起電極の占有面積が小さくなる。以上より、半導体チップの設計自由度をある程度確保しつつ、導電性樹脂の流量不足に起因する接続不良の発生が抑制される。
<1.1 液晶モジュールの構成>
図2は、本発明の第1の実施形態に係るLSIチップ(半導体チップ)を備えた液晶モジュールの平面図である。この液晶モジュールは、液晶パネルとLSIチップ10とFPC(Flexible Printed Circuit)40とによって構成されている。液晶パネルは、画素電極(表示電極)を含みTFTアレイが形成されたTFTアレイ基板20と、カラー表示用のカラーフィルタが形成されるとともに液晶層を介して画素電極との間に電圧を印加するための対向電極が形成されたカラーフィルタ基板30とによって構成されている。TFTアレイ基板20およびカラーフィルタ基板30はともにガラス基板である。また、図2に示すように、カラーフィルタ基板30よりもTFTアレイ基板20の方が平面視で大きくなっている。TFTアレイ基板20とカラーフィルタ基板30とが平面視で重なる領域に表示部が設けられている。TFTアレイ基板20上の領域のうちカラーフィルタ基板30とは対向していない領域は一般に「額縁」と呼ばれている。本実施形態においては、額縁となる領域(以下、「額縁エリア」という。)21には、液晶パネル駆動用のLSIチップ10が実装されるとともに、当該LSIチップ10の動作を制御するためのコントローラ等を含むFPC40が接続され、これにより、液晶モジュールが実現されている。このように、本実施形態においては、ガラス基板上にLSIチップ10が搭載された構成すなわちCOG(Chip On Glass)方式が採用されている。なお、図2では、説明の便宜上、カラーフィルタ基板30を平面視でやや左上方向にずらして図示している。
図1は、本実施形態におけるLSIチップ10の底面図である。図1に示すように、このLSIチップ10の底面には、一方の長辺に沿って一列に配置された複数個の入力バンプ11からなる入力バンプ群110と、他方の長辺に沿って千鳥状に配置された複数個の出力バンプ12からなる出力バンプ群120と、入力バンプ群110が設けられている領域と出力バンプ群120が設けられている領域との間の領域に一列に配置された複数個のダミーバンプ13からなるダミーバンプ群130とが設けられている。なお、ダミーバンプ13とは、電気的接続の機能を持たないバンプのことである。入力バンプ群110は、このLSIチップ10を搭載するTFTアレイ基板20上に形成された電極パッドとACFによって接続される。そして、その入力バンプ群110に接続される電極パッドには、このLSIチップ10を動作させるための電気信号が与えられる。出力バンプ群120も、このLSIチップ10を搭載するTFTアレイ基板20上に形成された電極パッドとACFによって接続される。そして、その出力バンプ群120に接続される電極パッドには走査信号線や映像信号線が接続され、当該電極パッドを介してこのLSIチップ10から走査信号線および映像信号線に駆動用の信号が与えられる。
図15に示した従来の構成によると、LSIチップ70の底面の一方の長辺に沿って一列に配置された入力バンプ群710と他方の長辺に沿って千鳥状に配置された出力バンプ群720との間の領域には、ACF樹脂の流れを阻害するようなバンプ等は設けられていなかった。このため、図4(A)に示すように、中央部から短辺側へのACF樹脂の流量と比較すると、中央部から長辺側へのACF樹脂の流量は著しく小さくなっていた。その結果、LSIチップ70のコーナー部近傍において、ACF樹脂の流量不足が顕著となり(図22参照)、反応不足や樹脂不足に起因して信頼性が十分な接続状態が得られず、接続不良が生じていた。これに対して、本実施形態に係る構成によると、入力バンプ群110と出力バンプ群120との間の領域には、図1に示すように、ACF樹脂の大きな流れに対して垂直方向に長辺を有する複数のダミーバンプ13からなるダミーバンプ群130が設けられている。このため、図4(B)に示すように、中央部から短辺側へのACF樹脂の流れがダミーバンプ13によって阻害され、従来の構成と比較して多量のACF樹脂が中央部から長辺側へと流れる。これにより、図5で符号15の矢印で示すように、LSIチップ10のコーナー部近傍においてもACF樹脂の充分な流れが確保され、ACF樹脂の流量不足に起因する接続不良の発生が抑制される。
図7は、本発明の第2の実施形態におけるLSIチップ10の底面図である。本実施形態においては、図7に示すように、LSIチップ10の底面の一方の短辺近傍および他方の短辺近傍にのみダミーバンプ13が設けられている。すなわち、上記第1の実施形態におけるダミーバンプ群130に含まれる複数のダミーバンプ13(図1参照)のうち最も外側に配置されている2個のダミーバンプ13のみがLSIチップ10の底面に形成されている。それ以外の構成については、上記第1の実施形態と同様であるので、説明を省略する。
図8は、本発明の第3の実施形態におけるLSIチップ10の底面図である。LSIチップ10の底面におけるバンプの形成に関しては様々な制限が課され得る。例えば、バンプの長辺の長さが所定の長さ以下に制限されることもある。このような場合、入力バンプ群110とダミーバンプ群130との間の距離あるいは出力バンプ群120とダミーバンプ群130との間の距離が大きくなり、中央部から短辺側へのACF樹脂の大きな流れが阻害されないことが考えられる。そこで、本実施形態においては、図8に示すように、ダミーバンプ群130は、相対的にLSIチップ10底面の一方の長辺側にずれて配置されたダミーバンプ13と相対的にLSIチップ10底面の他方の長辺側にずれて配置されたダミーバンプ13とが交互に配置されるように形成されている。それ以外の構成については、上記第1の実施形態と同様であるので、説明を省略する。
図13は、本発明の第4の実施形態におけるLSIチップ10の底面図である。図22に示したように、端子間が狭ピッチ化されたLSIチップ70においても、底面の長辺の中心付近では接続不良が生じない程度にACF樹脂の流量が確保されることが多い(符号76の矢印参照)。従って、中央部に近いほど、中央部から短辺側へのACF樹脂の流れを阻害する必要性が低いことが考えられる。そこで、本実施形態においては、図13に示すように、ダミーバンプ群130に含まれる複数のダミーバンプ13は、LSIチップ10底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されている。それ以外の構成については、上記第1の実施形態と同様であるので、説明を省略する。
上記各実施形態においては、LSIチップ10が液晶パネルのTFTアレイ基板20に実装される例を挙げて説明しているが、本発明はこれに限定されない。ACFを用いて半導体チップが配線基板に実装されるものであれば、ACF樹脂の流量不足に起因する接続不良の発生を抑制するために本発明を適用することができる。
10…LSIチップ
11…入力バンプ
12…出力バンプ
13…ダミーバンプ
20…TFTアレイ基板
21…額縁エリア
30…カラーフィルタ基板
40…FPC
110…入力バンプ群
120…出力バンプ群
130…ダミーバンプ群
Claims (9)
- 長方形状の底面を有し、前記底面の一方の長辺に沿って配置され外部からの入力信号を受け取るための複数の突起電極からなる第1の突起電極群と、前記底面の他方の長辺に沿って配置され出力信号を外部に出力するための複数の突起電極からなる第2の突起電極群とを含む半導体チップであって、
前記底面において、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の領域に、前記底面の長辺に対して垂直方向に延びる辺を長辺とする長方形状の複数の突起電極からなる第3の突起電極群を備え、
前記第3の突起電極群に含まれる複数の突起電極は、
外部との電気的な接続がなされない電極であり、
前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする、半導体チップ。 - 互いに対向する第1および第2の基板からなる液晶パネルを含み、前記液晶パネルを駆動するための駆動回路が前記第1の基板に設けられる液晶モジュールであって、
請求項1に記載の半導体チップが前記駆動回路として異方性導電膜を用いて前記第1の基板に実装されていることを特徴とする、液晶モジュール。 - 長方形状の底面を有し、前記底面の一方の長辺に沿って配置され外部からの入力信号を受け取るための複数の突起電極からなる第1の突起電極群と、前記底面の他方の長辺に沿って配置され出力信号を外部に出力するための複数の突起電極からなる第2の突起電極群とを含む半導体チップであって、
前記底面において、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の領域に、前記底面の長辺に対して垂直方向に延びる辺を長辺とする長方形状の複数の突起電極からなる第3の突起電極群を備え、
前記第3の突起電極群に含まれる複数の突起電極は、外部との電気的な接続がなされない電極であり、
前記第3の突起電極群は、前記第1の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列と前記第2の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列とを含み、
各突起電極列に含まれる複数の突起電極は、前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする、半導体チップ。 - 互いに対向する第1および第2の基板からなる液晶パネルを含み、前記液晶パネルを駆動するための駆動回路が前記第1の基板に設けられる液晶モジュールであって、
請求項3に記載の半導体チップが前記駆動回路として異方性導電膜を用いて前記第1の基板に実装されていることを特徴とする、液晶モジュール。 - 電気配線が形成された配線基板に長方形状の底面を有する半導体チップが異方性導電膜を用いて実装された実装構造であって、
前記半導体チップは、前記底面の一方の長辺に沿って配置され前記配線基板上の電気配線からの入力信号を受け取るための複数の突起電極からなる第1の突起電極群と、前記底面の他方の長辺に沿って配置され出力信号を前記配線基板上の電気配線に出力するための複数の突起電極からなる第2の突起電極群と、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の領域に配置され前記底面の長辺に対して垂直方向に延びる辺を長辺とする長方形状の複数の突起電極からなる第3の突起電極群とを備え、
前記第3の突起電極群には、少なくとも前記底面の一方の短辺近傍および他方の短辺近傍に形成された突起電極が含まれ、
前記第3の突起電極群に含まれる複数の突起電極は、前記配線基板上の電気配線との電気的な接続がなされない電極であり、
前記底面の一方の短辺近傍および他方の短辺近傍に形成された突起電極の各々の長辺は、前記第1の突起電極群が形成されている領域と前記第2の突起電極群が形成されている領域との間の距離の5分の3以上の長さであることを特徴とする、実装構造。 - 前記第3の突起電極群には、前記底面の一方の短辺近傍に形成された突起電極と前記底面の他方の短辺近傍に形成された突起電極との間の領域に一列に配置された複数の突起電極が含まれていることを特徴とする、請求項5に記載の実装構造。
- 前記第3の突起電極群に含まれる複数の突起電極は、前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする、請求項6に記載の実装構造。
- 前記第3の突起電極群は、前記底面の一方の短辺近傍に形成された突起電極と前記底面の他方の短辺近傍に形成された突起電極との間の領域に、前記第1の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列と前記第2の突起電極群が形成されている領域に沿って一列に配置された複数の突起電極からなる突起電極列とを含み、
各突起電極列に含まれる複数の突起電極は、前記底面の中央部から短辺側に近づくに従い長辺が長くなるように形成されていることを特徴とする、請求項5に記載の実装構造。 - 前記配線基板は、液晶モジュールに含まれる液晶パネルを構成する2枚の基板のうちの一方の基板であって、
前記半導体チップは、前記液晶パネルを駆動するための駆動回路であることを特徴とする、請求項5から8までのいずれか1項に記載の実装構造。
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- 2010-02-02 US US13/377,780 patent/US20120080789A1/en not_active Abandoned
- 2010-02-02 RU RU2012101104/28A patent/RU2487435C1/ru not_active IP Right Cessation
- 2010-02-02 BR BRPI1012742A patent/BRPI1012742A2/pt not_active IP Right Cessation
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US11335668B2 (en) | 2019-10-30 | 2022-05-17 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
US11769755B2 (en) | 2019-10-30 | 2023-09-26 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
JPWO2010146884A1 (ja) | 2012-12-06 |
US20120080789A1 (en) | 2012-04-05 |
CN102460668A (zh) | 2012-05-16 |
RU2487435C1 (ru) | 2013-07-10 |
EP2432006A1 (en) | 2012-03-21 |
CN102460668B (zh) | 2014-11-19 |
WO2010146884A1 (ja) | 2010-12-23 |
BRPI1012742A2 (pt) | 2019-09-24 |
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