CN102460668B - 半导体芯片的安装结构 - Google Patents

半导体芯片的安装结构 Download PDF

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Publication number
CN102460668B
CN102460668B CN201080025871.9A CN201080025871A CN102460668B CN 102460668 B CN102460668 B CN 102460668B CN 201080025871 A CN201080025871 A CN 201080025871A CN 102460668 B CN102460668 B CN 102460668B
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China
Prior art keywords
projected electrode
projected
electrode group
group
row
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CN102460668A (zh
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盐田素二
中滨裕喜
松井隆司
堀口武志
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Sharp Corp
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Sharp Corp
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Abstract

实现能够抑制与安装目标的基板发生连接不良且端子间被窄间距化的半导体芯片。LSI芯片(10)包括：输入凸块组(110)，其包括沿底面的一个长边配置成一列的多个输入凸块(11)；和输出凸块组(120)，其包括沿底面的另一个长边配置成交错状的多个输出凸块(12)，在该LSI芯片中，在设置有输入凸块组(110)的区域和设置有输出凸块组(120)的区域之间的区域设置有伪凸块组(130)，该伪凸块组包括以在与底面的长边垂直的方向上延伸的边为长边的长方形状的多个伪凸块(不具有电连接功能的凸块)(13)。

Description

半导体芯片的安装结构
技术领域
本发明涉及半导体芯片及其安装结构，更详细地说，涉及用导电性的粘接剂安装到基板的半导体芯片的结构和将这种半导体芯片向基板安装而得的安装结构。 
背景技术
近年来，对电子设备的小型化和薄型化的要求变高。与此相伴，关于IC(Integrated Circuit：集成电路)芯片和LSI(Large Scale Integration：大规模集成电路)芯片(以下将两者合并简称为“芯片”)安装到配线基板的方法，有各种提案。例如，作为以极小的区域实现芯片向配线基板的安装的方法，已知有被称为“倒装法(flip chip)安装”的安装方法。所谓倒装法安装，是在被称为“裸芯片(bare chit)”的未封装(package)的芯片的表面形成被称为“凸块(bump)”的突起电极，使电路面朝下与配线基板直接电连接的安装方法。 
在倒装法安装时，配线基板与芯片的粘接一般使用各向异性导电材料。各向异性导电材料，是在压接部的厚度方向上具有导电性，在压接部的面方向上具有绝缘性的连接材料。各向异性导电材料主要由作为导电性粒子和粘接剂发挥功能的树脂(以下称为“粘接树脂”)构成(导电性粒子分散在粘接树脂中)。在粘接时，通过对粘接部分加热加压，将粘接树脂摊开。此时，通过导电性粒子被夹(捕捉)在相对的电极间，相对的电极间电导通。另外，导电性粒子向粘接树脂充填的充填量，根据电极的连接面积和电极间间隔(space)设计。 
作为各向异性导电材料，典型地已知有被称为ACP(Anisotropic Conductive Paste：各向异性导电胶)的胶状的粘接剂和被称为ACF(Anisotropic Conductive Film：各向异性导电膜)的膜状的粘接剂。ACP和ACF是在由环氧树脂等热硬化性树脂形成的粘接剂中使镍粒子和镀金塑料粒子等导电性粒子分散而成的粘接剂。如果将ACP和ACF 作比较，则相比ACF，ACP的导电性粒子的流动性高。因此，ACP具有粘接时导电性粒子难以被捕捉到电极间的缺点。与之相对地，ACF具有粘接时导电性粒子容易被捕捉到电极间而能够可靠地确保电导通的优点。近年来，伴随着电子设备的小型化和薄型化，芯片的端子间的间距(pitch)的狭小化和电极焊盘(pat)的微细化在不断进步。因此，出于容易捕捉导电性粒子的观点，多采用ACF作为粘接剂。 
图15是作为液晶显示装置的驱动电路使用的现有的LSI芯片70的底面图。在该LSI芯片70的底面设置有：包括沿一个长边配置成一列的多个输入凸块(输入端子)71的输入凸块组710；和包括沿另一个长边配置成交错状的多个输出凸块(输出端子)72的输出凸块组720。输入凸块组710和输出凸块组720，通过在装载该LSI芯片70的配线基板上形成的电极焊盘和ACF而连接。对与输入凸块组710连接的电极焊盘，提供用于使该LSI芯片70动作的电信号。在与输出凸块组720连接的电极焊盘连接有扫描信号线和视频信号线，经由该电极焊盘从该LSI芯片70将驱动用信号提供给扫描信号线和视频信号线。 
接着，对用ACF进行的芯片(例如，图15所示的LSI芯片70)向配线基板的安装进行说明。首先，如图16(A)所示，准备：形成有用于与芯片50电连接的电极焊盘(Electrode pad)53的配线基板51；和形成有凸块52的芯片50，以覆盖电极焊盘53的方式将ACF54粘贴到配线基板51。之后，如图16(B)所示，通过压接工具55进行芯片50向配线基板51的热压接。热压接在设置于芯片50的底面的凸块52和配线基板51上的电极焊盘53位置匹配(对位)的状态下进行。通过该热压接，构成ACF54的树脂(以下称为“ACF树脂”)熔融，如图16(C)所示，ACF树脂从芯片50的中央部向外侧流出。此时，由于ACF树脂充填在凸块52间，所以通过包含于ACF树脂中的导电性粒子能够确保芯片50底面的凸块52与配线基板51上的电极焊盘53的电导通状态。 
另外，与本申请发明相关地，已知有如下的现有技术。在日本的特开2004-252466号公报中，公开了具有图17和图18所示结构的底面的IC芯片80、85的发明。在图17中，对输入凸块组、与视频信号线连接的输出凸块组和与扫描信号线连接的输出凸块组分别标注符号 81、82和83。在图18中，对输入凸块组、与视频信号线连接的输出凸块组和与扫描信号线连接的输出凸块组分别标注符号86、87和88。根据这些IC芯片80、85，输出凸块不是交错配置，因此输出凸块间的ACF树脂的流动性提高。另外，在日本的特开2006-106132号公报中，公开了如图19所示在芯片的短边侧具有测试用端子组91的结构和如图20所示在比输入端子组93更靠中央侧的位置具有测试用端子组94的结构。另外，图20是图21中用符号95表示的区域的局部放大图。而且，在日本的特开2007-173738号公报中，公开了通过采用具有伪(dummy)配线导体部的结构，来阻止密封树脂内产生的气泡进入到配线导体的技术。 
现有技术文献 
专利文献 
专利文献1：日本特开2004-252466号公报 
专利文献2：日本特开2006-106132号公报 
专利文献3：日本特开2007-173738号公报 
发明内容
发明要解决的课题 
然而，由于上述端子间的窄间距化，在芯片底面的四角(以下称为“角落部”)，会发生芯片的输出凸块和配线基板上的电极焊盘之间的电连接不良(以下称为“连接不良”)。对此在下面进行说明。图22是用于对图15所示的LSI芯片70的端子间被窄间距化时的LSI芯片70的底面的ACF树脂的流动进行说明的图。在图22中，用箭头的方向表示ACF树脂的流动，用箭头的宽度表示ACF树脂的流动的大小(流量)。就从中央部向短边侧的流动而言，在输入凸块71与输出凸块72之间的区域没有设置凸块，因此如符号75的箭头所示成为非常大的流量。就从中央部向长边侧的流动中的向输出凸块72侧的流动而言，如符号76～78的箭头所示，从长边的中心起，流量随着接近角落部而变小。其理由是因为，由于输出凸块72以窄间距交错排列，ACF树脂变得难以流过输出凸块72间。另外，由于ACF树脂向更容易流动的方向的流量变大，所以从中央部向长边侧的流量变小与如上所述 从中央部向短边侧的流量变大相当的量。如上所述，在LSI芯片70的特别是角落部附近，如符号78的箭头所示，成为非常小的流量。其结果是，在角落部附近发生上述的连接不良。另外，输入凸块71没有达到输出凸块72那种程度的窄间距化，因此从中央部向长边侧的流动中的向输入凸块71侧的流动，在角落部附近也如符号79的箭头所示，能够确保不发生连接不良程度的流量。 
于是，本发明的目的在于，实现能够抑制与安装目标的基板发生连接不良的情况，且端子间被窄间距化的半导体芯片。 
用于解决课题的手段 
本发明的第一方面，是一种半导体芯片，其特征在于：该半导体芯片具有长方形形状的底面，包括：第一突起电极组，其包括沿上述底面的一个长边配置且用于接收来自外部的输入信号的多个突起电极；和第二突起电极组，其包括沿上述底面的另一个长边配置且用于将输出信号输出到外部的多个突起电极， 
在上述底面，在形成有上述第一突起电极组的区域和形成有上述第二突起电极组的区域之间的区域具有第三突起电极组，该第三突起电极组包括以在与上述底面的长边垂直的方向上延伸的边为长边的长方形状的多个突起电极， 
包含于上述第三突起电极组中的多个突起电极，是不与外部电连接的电极。 
本发明的第二方面，在本发明的第一方面的基础上， 
包含于上述第三突起电极组中的多个突起电极，仅包括在上述底面的一个短边附近和另一个短边附近形成的突起电极。 
本发明的第三方面，在本发明的第一方面的基础上， 
包含于上述第三突起电极组中的多个突起电极的长边的长度，为形成有上述第一突起电极组的区域和形成有上述第二突起电极组的区域之间的距离的二分之一以上。 
本发明的第四方面，在本发明的第一方面的基础上， 
上述第三突起电极组包括多个突起电极列，该多个突起电极列至少包含：包括沿形成有上述第一突起电极组的区域配置成一列的多个突起电极的突起电极列；和包括沿形成有上述第二突起电极组的区域 配置成一列的多个突起电极的突起电极列。 
本发明的第五方面，在本发明的第一方面的基础上， 
包含于上述第三突起电极组中的多个突起电极形成为：相对地偏向上述底面的一个长边侧配置的突起电极和相对地偏向上述底面的另一个长边侧配置的突起电极交替配置。 
本发明的第六方面，在本发明的第一方面的基础上， 
包含于上述第三突起电极组中的多个突起电极形成为：从上述底面的中央部起，长边随着接近短边侧而变长。 
本发明的第七方面，在本发明的第一方面的基础上， 
上述第三突起电极组包含：包括沿形成有上述第一突起电极组的区域配置成一列的多个突起电极的突起电极列；和包括沿形成有上述第二突起电极组的区域配置成一列的多个突起电极的突起电极列， 
包含于各突起电极列中的多个突起电极形成为：从上述底面的中央部起，长边随着接近短边侧而变长。 
本发明的第八方面，在本发明的第一方面的基础上， 
上述第二突起电极组包括多个突起电极列，该多个突起电极列至少包含：包括沿上述底面的一个长边配置成一列的多个突起电极的突起电极列；和包括沿形成有上述第三突起电极组的区域配置成一列的多个突起电极的突起电极列。 
本发明的第九方面，是一种液晶模块，其特征在于：该液晶模块包含包括相互相对的第一基板和第二基板的液晶面板，在上述第一基板上设置有用于驱动上述液晶面板的驱动电路， 
本发明的第一方面至第八方面中任一方面所述的半导体芯片作为上述驱动电路被用各向异性导电膜安装于上述第一基板。 
本发明的第十方面，是一种安装结构，其特征在于：其为将具有长方形状的底面的半导体芯片用各向异性导电膜安装到形成有电配线的配线基板而得的安装结构， 
上述半导体芯片包括：第一突起电极组，其包括沿上述底面的一个长边配置且用于接收来自上述配线基板上的电配线的输入信号的多个突起电极；第二突起电极组，其包括沿上述底面的另一个长边配置且用于将输出信号输出到上述配线基板上的电配线的多个突起电极； 和第三突起电极组，其包括配置在形成有上述第一突起电极组的区域和形成有上述第二突起电极组的区域之间的区域，以在与上述底面的长边垂直的方向上延伸的边为长边的长方形状的多个突起电极， 
包含于上述第三突起电极组中的多个突起电极，是不与上述配线基板上的电配线电连接的电极。 
本发明的第十一方面，在本发明的第十方面的基础上， 
包含于上述第三突起电极组中的多个突起电极，仅包括在上述底面的一个短边附近和另一个短边附近形成的突起电极。 
本发明的第十二方面，在本发明的第十方面的基础上， 
包含于上述第三突起电极组中的多个突起电极的长边的长度，为形成有上述第一突起电极组的区域和形成有上述第二突起电极组的区域之间的距离的二分之一以上。 
本发明的第十三方面，在本发明的第十方面的基础上， 
上述第三突起电极组包括多个突起电极列，该多个突起电极列至少包含：包括沿形成有上述第一突起电极组的区域配置成一列的多个突起电极的突起电极列；和包括沿形成有上述第二突起电极组的区域配置成一列的多个突起电极的突起电极列。 
本发明的第十四方面，在本发明的第十方面的基础上， 
包含于上述第三突起电极组中的多个突起电极形成为：相对地偏向上述底面的一个长边侧配置的突起电极和相对地偏向上述底面的另一个长边侧配置的突起电极交替配置。 
本发明的第十五方面，在本发明的第十方面的基础上， 
包含于上述第三突起电极组中的多个突起电极形成为：从上述底面的中央部起，长边随着接近短边侧而变长。 
本发明的第十六方面，在本发明的第十方面的基础上， 
上述第三突起电极组包含：包括沿形成有上述第一突起电极组的区域配置成一列的多个突起电极的突起电极列；和包括沿形成有上述第二突起电极组的区域配置成一列的多个突起电极的突起电极列， 
包含于各突起电极列中的多个突起电极形成为：从上述底面的中央部起，长边随着接近短边侧而变长。 
本发明的第十七方面，在本发明的第十方面的基础上， 
上述第二突起电极组包括多个突起电极列，该多个突起电极列至少包含：包括沿上述底面的一个长边配置成一列的多个突起电极的突起电极列；和包括沿形成有上述第三突起电极组的区域配置成一列的多个突起电极的突起电极列。 
本发明的第十八方面，在本发明的第十方面至第十七方面的任一方面的基础上， 
上述配线基板是构成包含于液晶模块中的液晶面板的两块基板中的一个基板， 
上述半导体芯片是用于驱动上述液晶面板的驱动电路。 
发明效果 
根据本发明的第一方面，在半导体芯片的底面，在用于接收输入信号的第一突起电极组和用于将输出信号输出的第二突起电极组之间的区域设置有第三突起电极组，该第三突起电极组包括以在与该半导体芯片的底面的长边垂直的方向上延伸的边为长边的多个突起电极。因此，在用各向异性导电膜将半导体芯片安装到配线基板时，构成各向异性导电膜的树脂(导电性树脂)的流动被第三突起电极组阻碍。由此，与现有技术相比，大量的导电性树脂从半导体芯片的中央部向长边侧流动。其结果是，在半导体芯片的角落部附近也能够确保导电性树脂的充分的流动，能够抑制发生由导电性树脂的流量不足引起的连接不良。 
另外，包含于第三突起电极组中的多个突起电极，不具有电连接的功能。因此，不会经由这些包含于第三突起电极组中的多个突起电极进行电信号的收发，所以能够不考虑配线图案地，将用于阻碍导电性树脂的流动的多个突起电极配置于半导体芯片的底面。由此，能够不增大芯片尺寸地，实现半导体芯片的端子间的窄间距化。 
根据本发明的第二方面，仅在半导体芯片的底面的两短边附近设置用于阻碍导电性树脂的流动的突起电极。因此，能够不降低半导体芯片的设计自由度地，使比现有技术多的量的导电性树脂流向半导体芯片的角落部附近。由此，能够有效地抑制芯片尺寸的变大，并且抑制在最容易发生导电性树脂的流量不足的角落部附近发生连接不良。 
根据本发明的第三方面，在半导体芯片的底面，导电性树脂从中 央部向短边侧的流动的大半由第三突起电极组阻碍。因此，能够更加可靠地抑制发生由半导体芯片的角落部附近的导电性树脂的流量不足引起的连接不良。 
根据本发明的第四方面，在突起电极的长度存在限制的半导体芯片中，能够比较有效地阻碍导电性树脂从该半导体芯片的底面的中央部向短边侧的流动。因此，在半导体芯片的角落部附近也能够确保导电性树脂的充分的流动。由此，在突起电极的长度存在限制的半导体芯片中，能够抑制发生由导电性树脂的流量不足引起的连接不良。 
根据本发明的第五方面，与本发明的第四方面同样地，在突起电极的长度存在限制的半导体芯片中，能够抑制发生由导电性树脂的流量不足引起的连接不良。 
根据本发明的第六方面，在半导体芯片的底面，从中央部起，导电性树脂的流动随着接近短边侧而能够被有效地阻碍。另一方面，在半导体芯片的底面，从短边侧起，第三突起电极的占有面积随着接近中央部而变小。如上所述，能够一定程度地确保半导体芯片的设计自由度，并且能够抑制发生由导电性树脂的流量不足引起的连接不良。 
根据本发明的第七方面，与本发明的第六方面同样，能够一定程度地确保半导体芯片的设计自由度，并且能够抑制发生由导电性树脂的流量不足引起的连接不良。 
根据本发明的第八方面，在用于将输出信号输出到外部的第二突起电极组包括多个突起电极列的半导体芯片中，能够得到与本发明的第一方面同样的效果。 
根据本发明的第九方面，能够实现将发挥与本发明的第一方面至第八方面中的任一方面同样的效果的半导体芯片安装到液晶面板的基板的液晶模块。 
附图说明
图1是本发明的第一实施方式的LSI芯片的底面图。 
图2是具有上述第一实施方式的LSI芯片的液晶模块的俯视图。 
图3是图1的A-A线截面图。 
图4的A和B是在上述第一实施方式中，用于对效果进行说明的 图。 
图5是在上述第一实施方式中，用于对ACF树脂的流动进行说明的图。 
图6的A和B是在上述第一实施方式中，用于对效果进行说明的图。 
图7是本发明的第二实施方式的LSI芯片的底面图。 
图8是本发明的第三实施方式的LSI芯片的底面图。 
图9是上述第三实施方式的变形例的LSI芯片的底面图。 
图10是上述第三实施方式的变形例的LSI芯片的底面图。 
图11是上述第三实施方式的变形例的LSI芯片的底面图。 
图12是上述第三实施方式的变形例的LSI芯片的底面图。 
图13是本发明的第四实施方式的LSI芯片的底面图。 
图14是上述第四实施方式的变形例的LSI芯片的底面图。 
图15是作为液晶显示装置的驱动电路使用的现有的LSI芯片的底面图。 
图16的A-C是用于对用ACF进行的芯片向配线基板的安装进行说明的图。 
图17是现有的IC芯片的底面图。 
图18是现有的IC芯片的底面图。 
图19是现有的芯片的底面图。 
图20是现有的芯片的底面图的局部放大图。 
图21是现有的芯片的底面图。 
图22是在现有例子中，用于对ACF树脂的流动进行说明的图。 
具体实施方式
以下，参照附图对本发明的实施方式进行说明。 
<1.第一实施方式> 
<1.1液晶模块的结构> 
图2是具有本发明的第一实施方式的LSI芯片(半导体芯片)的液晶模块的俯视图。该液晶模块包括液晶面板、LSI芯片10和FPC(Flexible Printed Circuit：柔性印刷电路)40。液晶面板包括：包含像 素电极(显示电极)且形成有TFT阵列的TFT阵列基板20；和形成有彩色显示用的彩色滤光片并且隔着液晶层形成有用于在与像素电极之间施加电压的对置电极的彩色滤光片基板30。TFT阵列基板20和彩色滤光片基板30都是玻璃基板。另外，如图2所示，相比彩色滤光片基板30，TFT阵列基板20在俯视时大。在TFT阵列基板20和彩色滤光片基板30在俯视时重叠的区域，设置有显示部。TFT阵列基板20上的区域中不与彩色滤光片基板30相对的区域，一般被称为“边框”。在本实施方式中，在成为边框的区域(以下称为“边框区域”)21，安装有液晶面板驱动用的LSI芯片10，并且连接有包括用于对该LSI芯片10的动作进行控制的控制器等的FPC40，由此实现液晶模块。像这样，在本实施方式中，采用在玻璃基板上装载有LSI芯片10的结构，即COG(Chip On Glass：玻璃基芯片)方式。另外，在图2中，为了便于说明，将彩色滤光片基板30在俯视时稍微偏向左上方地图示。 
<1.2LSI芯片的底面的结构> 
图1是本实施方式的LSI芯片10的底面图。如图1所示，在该LSI芯片10的底面，设置有包括沿一个长边配置成一列的多个输入凸块11的输入凸块组110；包括沿另一个长边配置成交错状的多个输出凸块12的输出凸块组120；和包括在设置有输入凸块组110的区域和设置有输出凸块组120的区域之间的区域配置成一列的多个伪凸块(dummy bump)13的伪凸块组130。另外，所谓伪凸块13，是指不具有电连接功能的凸块。输入凸块组110通过在装载该LSI芯片10的TFT阵列基板20上形成的电极焊盘和ACF连接。而且，对与该输入凸块组110连接的电极焊盘，提供用于使LSI芯片10动作的电信号。输出凸块组120也通过在装载该LSI芯片10的TFT阵列基板20上形成的电极焊盘和ACF连接。而且，在与该输出凸块组120连接的电极焊盘连接有扫描信号线、视频信号线，经由该电极焊盘将驱动用的信号从该LSI芯片10提供给扫描信号线和视频信号线。 
另外，在本实施方式中，由输入凸块组110实现第一突起电极组，由输出凸块组120实现第二突起电极组，由伪凸块组130实现第三突起电极组。 
图3是图1的A-A线截面图(图2的B-B线截面图)。如图3所 示，在设置于LSI芯片10的底面的一端(FPC侧)附近的输入凸块11和设置于LSI芯片10的底面的另一端(显示部侧)附近的输出凸块12之间，设置有伪凸块13。TFT阵列基板20和LSI芯片10，通过ACF9相互粘接。在此，如果着眼于该LSI芯片10的底面的短边方向(符号19的箭头所示方向)的各凸块的长度，则典型地，伪凸块13的长度比输入凸块11的长度或输出凸块12的长度长。另外，使伪凸块13的长边的长度La为尽可能接近输入凸块11-输出凸块12间的长度Lb的长度，以使得如后所述ACF树脂的流动受到阻碍。例如，优选上述La为上述Lb的二分之一以上。另外，更优选上述La为上述Lb的五分之三以上。另外，在图3中，省略了TFT阵列基板20上的电极焊盘。 
<1.3效果> 
根据图15所示的现有的结构，在LSI芯片70的底面的沿一个长边配置成一列的输入凸块组710和沿另一个长边配置成交错状的输出凸块720之间的区域，没有设置阻碍ACF树脂的流动的凸块等。因此，如图4(A)所示，如果与从中央部向短边侧的ACF树脂的流量作比较，则从中央部向长边侧的ACF树脂的流动显著地小。其结果是，在LSI芯片70的角落部附近，ACF树脂的流量不足显著(参照图22)，由于反应不足、树脂不足而无法得到可靠性充分的连接状态，发生连接不良。与之相对地，根据本实施方式的结构，在输入凸块组110和输出凸块组120之间的区域，如图1所示，设置有包括在与ACF树脂的大的流动垂直的方向具有长边的多个伪凸块13的伪凸块组130。因此，如图4(B)所示，从中央部向短边侧的ACF树脂的流动被伪凸块组13阻碍，与现有的结构相比大量的ACF树脂从中央部向长边侧流动。由此，如图5中符号15的箭头所示，在LSI芯片10的角落部附近也能够确保ACF树脂的充分的流动，由ACF树脂的流量不足引起的连接不良的发生受到抑制。 
另外，在图17所示的现有的结构中，符号84所示的凸块能够相当于本实施方式的伪凸块13。在图18所示的现有的结构中，符号89所示的凸块能够相当于本实施方式的伪凸块13。但是，现有的结构的伪凸块84、89如图6(A)所示在与ACF树脂的大的流动相同的方向具有长边，而本实施方式的伪凸块13如图6(B)所示在与ACF树脂 的大的流动垂直的方向具有长边。因此，在本实施方式中，能够有效地将ACF树脂的流动方向变为朝向(LSI芯片的底面的)长边侧，在LSI芯片10的角落部附近也能够可靠地确保充分的量的ACF树脂的流动。 
如上所述，关于端子(凸块)间被窄间距化的LSI芯片10向TFT阵列基板20的安装，由以往在LSI芯片10的角落部附近产生的ACF树脂的流量不足引起的连接不良(LSI芯片10底面的输出凸块12和TFT阵列基板20上的电极焊盘之间的电连接不良)的发生受到抑制。其结果是，能够提供可靠性高的液晶模块。 
另外，在本实施方式中，作为用于阻碍ACF树脂的流动的构成要素，采用不具有电连接功能的伪凸块13。由于不能经由伪凸块13进行电信号的收发，所以能够不考虑配线图案地将多个伪凸块13配置于LSI芯片10的底面。因此，能够不降低LSI设计时的布局效率地，不使芯片尺寸变大地实现端子间的窄间距化。由此，能够实现装载有端子间被窄间距化的LSI芯片10的液晶模块。 
而且，根据本实施方式，不对连接工序中的调节操作(进行尝试从而得出最佳条件的操作)和连接工序的管理操作不带来大的负担地，能够对液晶模块采用端子间被窄间距化的LSI芯片10。 
<2.第二实施方式> 
图7是本发明的第二实施方式的LSI芯片10的底面图。在本实施方式中，如图7所示，仅在LSI芯片10的底面的一个短边附近和另一个短边附近设置有伪凸块13。即，包含于上述第一实施方式的凸块组130中的多个凸块13(参照图1)中仅配置在最外侧的两个凸块13形成于LSI芯片10的底面。除此以外的结构，与上述第一实施方式同样，所以省略说明。 
在输入凸块组110和输出凸块组120之间的区域设置越多的抑制ACF树脂从中央部向短边侧的流动的伪凸块13，LSI芯片10和TFT阵列基板20的连接的可靠性越高。但是，在LSI芯片10的底面设置的伪凸块13越多，LSI芯片10的设计自由度越低。因此，如图7所示通过采用仅在LSI芯片10的底面的两短边附近设置伪凸块13的结构，能够不降低LSI芯片10的设计自由度地，在LSI芯片10的角落部附 近也确保充分的量的ACF树脂。由此，能够有效地抑制芯片尺寸的扩大，并且能够抑制在最容易发生ACF树脂的流量不足的角落部附近发生连接不良。 
<3.第三实施方式> 
图8是本发明的第三实施方式的LSI芯片10的底面图。对于LSI芯片10的底面的凸块的形成，能够进行各种限制。例如，有时也将凸块的长边的长度限制在规定的长度以下。在这样的情况下，输入凸块组110与伪凸块组130之间的距离或输出凸块组120与伪凸块组130之间的距离变大，可以认为ACF树脂从中央部向短边侧的大的流动不被阻碍。因此，在本实施方式中，如图8所示，伪凸块组130形成为：相对地偏向LSI芯片10底面的一个长边侧配置的伪凸块13和相对地偏向LSI芯片10底面的另一个长边侧配置的伪凸块13交替配置。除此以外的结构，由于与上述第一实施方式同样，所以省略说明。 
根据本实施方式，在凸块的长边的长度被限制在规定的长度以下的LSI芯片10中，能够比较有效地阻碍从中央部向ACF树脂的流动。由此，在LSI芯片10的角落部附近也能够确保ACF树脂的充分的流动，能够抑制发生由ACF树脂的流量不足引起的连接不良。 
另外，在凸块的长边的长度被限制在规定的长度以下的情况下，例如图9、图10所示，也可以通过多列配置的多个伪凸块13构成伪凸块组130。详细而言，在图9所示的结构中，伪凸块组130包括：包括沿输入凸块组110配置成一列的多个伪凸块13的伪凸块列131；和包括沿输出凸块组120配置成一列的多个伪凸块13的伪凸块列132。在图10所示结构中，伪凸块组130包括：包括沿输入凸块组110配置成一列的多个伪凸块13的伪凸块列131；包括沿输出凸块组120配置成一列的多个伪凸块13的伪凸块列132；和包括在这两个伪凸块列131、132间配置成一列的多个伪凸块13的伪凸块列133。另外，也可以采用将图8所示的结构和图9或图10所示的结构组合而成的结构，即图11、图12所示的结构。 
<4.第四实施方式> 
图13是本发明的第四实施方式的LSI芯片10的底面图。如图22所示，在端子间被窄间距化的LSI芯片70中，在底面的长边的中心附近也大多能够确保不产生连接不良程度的ACF树脂的流量(参照符号76的箭头)。因此可以认为，越靠近中央部，越没有必要阻碍ACF树脂从中央部向短边侧的流动。因此，在本实施方式中，如图13所示，包含于伪凸块组130的多个伪凸块13形成为：从LSI芯片10底面的中央部起，长边随着接近短边侧而变长。除此以外的结构，由于与上述第一实施方式同样，所以省略说明。
在上述第二实施方式中，在最容易发生ACF树脂流量不足的角落部附近的连接不良的发生受到抑制，而在本实施方式中，能够一定程度地确保LSI芯片10的设计自由度，并且能够不仅抑制发生角落部附近的连接不良而且抑制发生角落部附近以外的连接不良。 
另外，出于同样的观点，如图14所示，伪凸块组130采用包括两列伪凸块列的结构，包含于各伪凸块列中的多个伪凸块13也可以形成为：从LSI芯片10底面的中央部起，长边随着接近短边侧而变长。 
<5.其他> 
在上述各实施方式中，举出将LSI芯片10安装到液晶面板的TFT阵列基板20的例子进行了说明，但本发明并不限定于此。只要是用ACF将半导体芯片安装到配线基板即可，为了抑制发生由ACF树脂的流量不足引起的连接不良能够应用本发明。 
另外，在上述各实施方式中，输入凸块组110包括一列凸块列(包括沿LSI芯片10底面的一个长边配置成一列的多个输入凸块11的凸块列)，输出凸块组120包括两列凸块列(包括沿LSI芯片10底面的另一个长边配置成一列的多个输出凸块12的凸块列，和包括沿形成有伪凸块组130的区域配置成一列的多个输出凸块12的凸块列)，但本发明并不限定于此。只要输入凸块组110和输出凸块组120分别沿LSI芯片10的一个长边和另一个长边配置，就能够适用本发明。 
附图符号说明 
9……ACF 
10……LSI芯片 
11……输入凸块 
12……输出凸块 
13……伪凸块 
20……TFT阵列基板 
21……边框区域 
30……彩色滤光片基板 
40……FPC 
110……输入凸块组 
120……输出凸块组 
130……伪凸块组 

Claims (5)

1.一种安装结构，其特征在于：
其为将具有长方形状的底面的半导体芯片用各向异性导电膜安装到形成有电配线的配线基板而得的安装结构，
所述半导体芯片包括：第一突起电极组，其包括沿所述底面的一个长边配置且用于接收来自所述配线基板上的电配线的输入信号的多个突起电极；第二突起电极组，其包括沿所述底面的另一个长边配置且用于将输出信号输出到所述配线基板上的电配线的多个突起电极；和第三突起电极组，其包括配置在形成有所述第一突起电极组的区域和形成有所述第二突起电极组的区域之间的区域，以在与所述底面的长边垂直的方向上延伸的边为长边的长方形状的多个突起电极，
所述第三突起电极组至少包括在所述底面的一个短边附近和另一个短边附近形成的突起电极，
包含于所述第三突起电极组中的多个突起电极，是不与所述配线基板上的电配线电连接的电极，
在所述底面的一个短边附近和另一个短边附近形成的突起电极各自的长边的长度，为形成有所述第一突起电极组的区域与形成有所述第二突起电极组的区域之间的距离的五分之三以上。
2.如权利要求1所述的安装结构，其特征在于：
所述第三突起电极组包括在形成于所述底面的一个短边附近的突起电极与形成于所述底面的另一个短边附近的突起电极之间的区域配置成一列的多个突起电极。
3.如权利要求2所述的安装结构，其特征在于：
包含于所述第三突起电极组中的多个突起电极形成为：从所述底面的中央部起，长边随着接近短边侧而变长。
4.如权利要求1所述的安装结构，其特征在于：
所述第三突起电极组在形成于所述底面的一个短边附近的突起电极与形成于所述底面的另一个短边附近的突起电极之间的区域包含：包括沿形成有所述第一突起电极组的区域配置成一列的多个突起电极的突起电极列；和包括沿形成有所述第二突起电极组的区域配置成一列的多个突起电极的突起电极列，
包含于各突起电极列中的多个突起电极形成为：从所述底面的中央部起，长边随着接近短边侧而变长。
5.如权利要求1至4中任一项所述的安装结构，其特征在于：
所述配线基板是构成包含于液晶模块中的液晶面板的两块基板中的一个基板，
所述半导体芯片是用于驱动所述液晶面板的驱动电路。
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