TWI302740B - A method of preparing a vertical channel of a field effect transistor, a field effect transistor using the method and a method of preparing an inverter made of a field effect transistor with a vertical channel, an inverter using the method - Google Patents
A method of preparing a vertical channel of a field effect transistor, a field effect transistor using the method and a method of preparing an inverter made of a field effect transistor with a vertical channel, an inverter using the method Download PDFInfo
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- TWI302740B TWI302740B TW093115950A TW93115950A TWI302740B TW I302740 B TWI302740 B TW I302740B TW 093115950 A TW093115950 A TW 093115950A TW 93115950 A TW93115950 A TW 93115950A TW I302740 B TWI302740 B TW I302740B
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- 238000000034 method Methods 0.000 title claims description 96
- 230000005669 field effect Effects 0.000 title claims description 60
- 239000013078 crystal Substances 0.000 claims description 166
- 239000000758 substrate Substances 0.000 claims description 50
- 229910052732 germanium Inorganic materials 0.000 claims description 42
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 41
- 230000000694 effects Effects 0.000 claims description 35
- 239000004575 stone Substances 0.000 claims description 35
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 claims description 33
- 229910052799 carbon Inorganic materials 0.000 claims description 31
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 29
- 230000008439 repair process Effects 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 241000238631 Hexapoda Species 0.000 claims description 19
- 230000000295 complement effect Effects 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 17
- 230000006835 compression Effects 0.000 claims description 16
- 238000007906 compression Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 238000012937 correction Methods 0.000 claims description 8
- 235000008331 Pinus X rigitaeda Nutrition 0.000 claims description 7
- 235000011613 Pinus brutia Nutrition 0.000 claims description 7
- 241000018646 Pinus brutia Species 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 241000282320 Panthera leo Species 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 241000239226 Scorpiones Species 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 241000282326 Felis catus Species 0.000 claims 4
- 230000004913 activation Effects 0.000 claims 3
- 239000004020 conductor Substances 0.000 claims 3
- 238000010884 ion-beam technique Methods 0.000 claims 3
- 239000002689 soil Substances 0.000 claims 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 206010012735 Diarrhoea Diseases 0.000 claims 2
- 229910001347 Stellite Inorganic materials 0.000 claims 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims 2
- AHICWQREWHDHHF-UHFFFAOYSA-N chromium;cobalt;iron;manganese;methane;molybdenum;nickel;silicon;tungsten Chemical compound C.[Si].[Cr].[Mn].[Fe].[Co].[Ni].[Mo].[W] AHICWQREWHDHHF-UHFFFAOYSA-N 0.000 claims 2
- 229910052746 lanthanum Inorganic materials 0.000 claims 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 2
- 238000005224 laser annealing Methods 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 claims 2
- 239000011148 porous material Substances 0.000 claims 2
- 238000002360 preparation method Methods 0.000 claims 2
- 239000000126 substance Substances 0.000 claims 2
- 241000251468 Actinopterygii Species 0.000 claims 1
- 241001124076 Aphididae Species 0.000 claims 1
- 235000017166 Bambusa arundinacea Nutrition 0.000 claims 1
- 235000017491 Bambusa tulda Nutrition 0.000 claims 1
- 241001330002 Bambuseae Species 0.000 claims 1
- 150000000703 Cerium Chemical class 0.000 claims 1
- 241000258937 Hemiptera Species 0.000 claims 1
- 235000014676 Phragmites communis Nutrition 0.000 claims 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 claims 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical group [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- 241000352457 Shivajiella indica Species 0.000 claims 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical class OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 239000011425 bamboo Substances 0.000 claims 1
- 239000003610 charcoal Substances 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 230000008602 contraction Effects 0.000 claims 1
- 235000021438 curry Nutrition 0.000 claims 1
- 238000005520 cutting process Methods 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 229910052735 hafnium Inorganic materials 0.000 claims 1
- 229910052744 lithium Inorganic materials 0.000 claims 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 150000003891 oxalate salts Chemical class 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 claims 1
- 150000003839 salts Chemical class 0.000 claims 1
- 229910021647 smectite Inorganic materials 0.000 claims 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims 1
- 238000010792 warming Methods 0.000 claims 1
- 229910052727 yttrium Inorganic materials 0.000 claims 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical group [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 255
- 108091006146 Channels Proteins 0.000 description 62
- 229910001922 gold oxide Inorganic materials 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 15
- 239000012212 insulator Substances 0.000 description 11
- 229910003811 SiGeC Inorganic materials 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000005610 quantum mechanics Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 210000002784 stomach Anatomy 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 244000144730 Amygdalus persica Species 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- 102000002322 Egg Proteins Human genes 0.000 description 1
- 108010000912 Egg Proteins Proteins 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 244000131316 Panax pseudoginseng Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 235000006040 Prunus persica var persica Nutrition 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 235000013345 egg yolk Nutrition 0.000 description 1
- 210000002969 egg yolk Anatomy 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- 230000002496 gastric effect Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 210000004072 lung Anatomy 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- ZLIBICFPKPWGIZ-UHFFFAOYSA-N pyrimethanil Chemical compound CC1=CC(C)=NC(NC=2C=CC=CC=2)=N1 ZLIBICFPKPWGIZ-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical class O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
-
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
-
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
1302740 九、發明說明: 貧修(奶正替換頁丨 ’ 15 9 50*u——一, ,,—•…—) 97年5月28日修正-替換頁 【相關申請之交互參照】 本申凊更父互參照附呈之Q· 〇Uyang及jack 〇· Chu(本案 發明人)的美國專利申請號10/463038 (代理人案號 YOR920030140US1),標題為「超可縮放高速異質接面垂直 N-通道金屬絕緣體半導體電晶體及其方法(ultra ScalaWe ffigh Speed Heterojunction Vertical N-Channel MISFETs and Methods Thereof)」。其針對垂直n型通道金屬絕緣體半導體場效電晶 體’於此納入作為參考,並讓渡與本案受讓人。 本申請更交互參照附呈之Q. Ouyang及Jack 0· Chu(本案 發明人)的美國專利申請號10/462933 (代理人案號 YOR920030141US1),標題為「二維帶隙工程實現之高速橫向 異質接面金屬絕緣體半導體場效電晶體及其方法(High Speed
Lateral Heterojunction MISFETs Realized by 2-dimensional
Bandgap Engineering and Methods thereof)」。其針對樺向異質接 面金屬絕緣體半導體場效電晶體,於此納入作為參考,並讓渡 與本案受讓人。 夕' 又 【發明所屬之技術領域】 本發明係關於半導體電晶體,且更特別地,關於金屬絕緣 體半導體場效電晶體(MISFET)。此金屬絕緣體半導體場效電 晶體由一導電通道及一異質接面組成。此導電通道於電流方向 沒有異質能障(hetero-barrier),此異質接面位於電晶體的源級 極與體極(body)(主體bulk)間。 1302740 【先前技術】 日修(雖替換頁 ϋ*---— 97年5月28日修正-替換頁 、矽金氧半場效電晶體的改變尺寸已成半導體業的主要挑 戰。當元件尺寸縮小到奈米等級,要減少某些不希望的物理效 應時,傳統技術開始不管用。例如,防擊穿(anti_punchthr〇ugh, APT)或環型佈植(haloimplantati〇n)慣用於減少短通道效應 (short-channel effects,SCE)。然而由於溫度加強擴散很^ 達到陡峭的摻雜分佈。並且這些高度摻雜的通道或環型佈植 (pocket implant)區域使接面電容及帶至帶穿隧(band_t〇_band tunneling)增加。於s· Thompson等人的「金氧半尺寸變化: 21 世紀的電晶體挑戰(MOS scaling·· transistor challenges for the 21st century)」Intel Technology Journal,Q3, 1998 中,已顯示對 給疋技術而吕’通道工程(channel engineering)只能減少電 路閘極延遲大約10%。且其無法在閘極氧化物與源/汲極接面 深度尺寸變化提供的世代之後,提供通道長度尺寸變化的世 代0 藉由帶隙工程,於元件設計中一個重要的自由度可被提 供。藉分子束蟲晶(molecular beam epitaxy,MBE)成長高品 質拉伸應變(tensile strained)矽/矽鍺(siGe)與壓縮應變 (compressively strained)石夕鍺/石夕異質結構、不同類型的化學 氣相沉積(chemical vapor deposition,CVD)、及/或離子佈植, 容許將帶隙工程概念納入成熟的矽科技。 帶隙工程已被用來實現不同類型的異質接面場效電晶體 (HFET)。最廣泛被研究的是調摻場效電晶體(modulation doped field effect transistor ’ MODFETs ),其中量子井被用來將 1302740 I 5. 28 i午丨S親. L案號.:·概棚gQ—— 97年5月28日修正-替^胃 載子限制在輕摻雜半導體中(見κ· Ismail的「矽/石夕鍺高速場 效電晶體(Si/SiGe High-Speed Field-Effect Transistors)」,IEDM,
Tech· Dig·,ρ· 509-512, 1995)。由於雜質散射減少、埋式通道 (buriedchannel)中的表面粗糙散射減少、與所使用異質材料 系統有關的應變導致移動率(m〇biHty)增加(如果有),都可 達成較高載子移動率。衍生自相同概念,不同形式的異質結構 互補金氧半元件也被提出與研究(見M· A· Araistong等人的 「矽/矽鍺異質接面互補金氧半電晶體之設計(Design of Si/SiGe Heterojunction Complementary Metal-Oxide
Semiconductor Transistors) j^IEDM Tech. Dig., p. 761-764, 1995; S. Imai等人的「矽-石夕鍺半導體元件及其製造方法(別&仏
Semiconductor Device and Method of Fabricating the Same)」,美 國專利號5,847,419及Μ· Kubo等人的「以矽-鍺-碳化合物半 導體層形成HCMOS元件的方法(Meth〇(i of F_ing hCM〇S Devices with Silicon-Germanium- carbon compound Semiconductor Layer)」’美國專利號 6,19〇 975,触 2〇, 2〇〇1 )。 攻些70件的伽錄高载子移鮮,而致高鶴電流與高速。 然而,這些平面元件中仍有兩個主要問題:元件尺寸變化及短 通道效應之控制。 一平面場效電晶體元件中,通道長度受限於微影技術。假如 ^件,直形式製作,其中通道長度只決定於蟲晶技術,此問 題y解决❿源//及極中的石朋和石舞的擴散,可藉於源/汲極中引 入薄=GeC層輯超可驗之垂直電㈣來減少。此如γ· 等人的具SlGeC源極-波極的25奈米p通道垂直金氧
❼文見曰曰體(25-nm P-Channel vertical MOSFETs with SiGeC 8 1302740 „ 案號:93115950 97年5月28日修ιέ-替換頁 source-drains)」,IEEE,Electron Device Letters,vol. 20, no· 6, 1999,及H· Rucker等人的「碳摻雜的矽與矽鍺中的摻雜質擴 散·物理模型與貫驗驗證(Dopant diffusion in C-doped Si and SiGe: physical model and experimental verification)」,IEDM, Technical Digest, p 345-8, 1999 所示。 關於短通道效應,絕緣層上矽(silicolM)n-insulator,SOI) 被用來控制短通道效應’而非極陡λ肖的退通道分佈(retr〇graded channel profiles)與極淺的源/汲極接面。然而單只絕緣層上矽 無法完全去除短通道效應,此外,絕緣層上石夕固有的問題是浮 體效應(floating body effect)。另一個減少短通道效應的方法 是在源/體極接面有一個内建能障,尤其是能障高度無關於所 加偏壓的能IV。由異質接面提供的帶偏移(band 〇ffset)在此 情況非常適合。於S· Hareland等人的「減少深次微米金氧半 場效電晶體中的擊穿電流與擴大金氧半場效電晶體尺寸變化 的新結構性方法(New structural approach for redueiug punchthrough current in deep subsemiconductor MOSFETs and extending MOSFET scaling) j 5 IEEE Electronics Letters, vol. 29? no· 21,pp· 1894-1896, October 1993,以及X· D· Chen 等人的「源 />及極與通道間具有異質接面的垂直p型金氧半場效電晶體 (Vertical P-MOSFETS with heterojunction between source/drain and channel)」,Device Research Conference,Denver,June 2000,異質接面金氧半場效電晶體(HJM〇SFET)被提出與研 究。 ^ 一 p通道/η通道、互補垂直金屬絕緣體半導體場效電晶體 Ι3Ό2740
军^另2%修(楚ji替換頁I 案號:·931159ϋθ~~~~—一」 97年5月28曰修正·替換頁 元件’與此種元件於動怨隨機存取記憶體(dynamic random accessmemory’DRAM)中的特定應用,被描述於美國專利號 5,920,088、6,207,977、5,963,800 與 5,914,504。異質接面被用 於垂直元件的源極/通道接面。即使非常短的通道都可做到, 且短通道效應可減少,這樣的元件結構仍有大缺點。在關閉狀 態(即閘極偏壓為0,汲極偏壓為高),異質能障對減少汲極 引致能障降低(drain-induced barrier lowering,DIBL )、主體擊 穿(bulkpunchthrough)有用,因此對減少關閉狀態漏電流有 用。然而在開狀悲(即閘極與〉及極偏壓為高)時,此内建異質 能障對驅動電流有害。這是因為源極/通道接面的異質能障嚴 重阻擔載子從源極入通道的熱發射(thermal emission)。載子 注入的唯一方法是橫越能障的量子力學穿隧,而這成為通道中 傳輸的瓶頸。因為強烈的表面粗链度散射(surface scattering),這些文獻所提到在通道中橫越能障後,所謂的衝 擊傳輸(ballistictransport)並不會發生。因此這樣的元件中的 驅動電流嚴重減少。此外,此種元件一部分的源極(靠近通道 的)未摻雜’驅動電流會因源極的高串聯電阻進一步減少。 Q· Ouyang荨人於「新穎p金氧半場效電晶體中的二維帶隙工 程(Two-Dimensional Bandgap Engineering in Novel pMOSFETs)」,SISPAD,Seattle September 2000 中,以及乂〇
Chen等人於「於源/汲極與通道間具異質接面的垂直p金氧半 場效電晶體(Vertical P-MOSEFTS with heterojunction between source/drain and channel) Device Research Conference, Denver, June2(K)0中,有詳細研究。 最近一橫向、高移動率、埋式p型通道異質接面電晶體 1302740 才1修(釣正替換1:: ί__§〇*"*———,一, —i 97^5月28日修正-替換頁 (HMHJT)於美國專利號6,319,799B1中被Q. Ouyang等人提 出。詳細的模擬研究已由Q· 〇uyang等人執行,於「具較小短 通道效應與較佳驅動電流的新穎矽/石夕鍺異質接面p型金氧半 場效電晶體(A Novel Si/SiGe heterojimetion pMOSFET with Reduced Short Channel Effects and Enhanced Drive Current)」, IEEE Transactions on Electron Devices,47(10),2000 中。此外, Q· Ouyang等人於「驅動電流加強以及短通道效應與浮體效應 減少之新穎垂直p型金氧半場效電晶體之製作(Fabricati〇n 〇f a Novel Vertical pMOSFET with Enhanced Drive Current and Reduced Short-Channel Effects and Floating Body Effects) j VLSI Symposium,Kyoto, June 2001中,此種元件已用垂直結構 實施。此情形中,矽上壓縮應變矽鍺被用來實作高性能p型金 氧半場效電晶體。然而這種元件通道長度的尺寸變化仍受限於 從源/没極入通道的硼擴散。此外,不管埋式通道中有較高的 移動率,埋式通道的跨導(transconductance)相較一表面通道 可被減少,因為閘極電容減少。本發明處理這些問題,並提供 P型金氧半場效電晶體的新結構。最後,本發明揭露垂直高性 能互補金屬絕緣體半導體場效電晶體。 美國專利號5,285,088描述一「南電子移動率電晶體(j^Qgh Electron Mobility Transistor)」。此元件具有一對半導體層供作 源/没極電極,由一多晶石夕鍺層與一多晶石夕層組成,以在主動 區(active area)上方形成一部份突出(projected)的「懸垂形 (overhanging-shape)」。此情況下,源/;:及極與閘極為自行對準 的(self-aligned)。然而其係一平面結構且仍受短通道效應影 響。 一 11 1302740 I卓ϋ修衛正替換頁丨 97年5月28日修正-替換頁 【發明内容】 本叙明的一目的在提供具有極佳性能與尺寸變化性的元 件結構。藉由使用二維帶隙工程,傳統砍科技的取捨可被避 免’且驅動電流與漏電流可獨立地被最佳化。因此可同時達到 非常高的驅動電流及優越的關閉(tum_〇ff)特性。此外,在這 樣的?件帽短通道效應的抑制,更容許金氧半場效電晶體科 技連續且更積極的尺寸變化。 本發明以不同實施例敘述具有這些優點的垂直p型通道 與垂直互補金屬絕緣體半導體場效電晶體結構。本發明的另一 面向是這些元件練程整合。本發明描述的元件在電晶體的源 極和體極間具有至少-個異質鱗,然而在通道中,沿電流方 向沒,質能障。由於源極接面的異質能障,沒極引致能^降 低被實質上齡了,·,次臨界聽(su碗eshQidswing) 與關閉狀祕電流(〇ff_stateleakage)被減少。同時,既然通 道中沒有異質能障,電料被量子力學_ (qua^m me^hamcal tunneling)限制。因此,有了這些元件可以達到 很高的開/關比(on/off rati0)。這些元件在高速、低漏電及低 功率應用中極佳’如DRAM、膝上型電腦、及無線通訊。· 任何具適當帶偏移的異質材料系統可被用來實現此元1 概念’例如秒為基礎或是m_v材料系統。既然梦科技 熟,石夕為基翻㈣是經濟上最可行與最具則丨力的於) 盤金屬絕緣體半導體場效電晶體,⑪上的壓縮應變石夕錯; SxGeC對電洞而言具適當帶偏移。要實施互補金屬絕緣 12 1302740
ί Ο. ^ ΰ / I I年月日修(慰土替換葡 ^rg3TT5S5〇----------------—… 97年5月28日修正-替換頁 體場效電晶體,有兩種選擇或是兩種類型的矽為基礎的異質結 構可用於η型金屬絕緣體半導體場效電晶體,因為它們對電子 而口具有適當帶偏移。一種是在鬆弛(relaxed)石夕錯緩衝層上 的壓縮應變矽或矽鍺,另一種是矽上的拉伸應變Si^-yGexCy。 母異質結構設計中,通道可為表面通道或埋式量子井通道。 •載子移動率不只和晶體中的應變有關,也和晶向(crystal onentatum)有關。最近一研究顯示,對問極氧化物厚度小於2 ,米且閘極長度小於15〇奈米的元件而言,在一(11〇)基板上沿 著<11〇>方向,電洞移動率顯著增加,而在(励)基板上沿著 <100>方向’電子移解彳猶最高。然而使用傳統平面石夕科技 將11〇〇)平面上的n型金氧半場效電晶體與(11G)平面上的P型 t半場效電晶體整合在-起並不實際。若用垂直元件或鑛式 J效,日日體(FinFET)就相對簡單。因此—高電洞移動率通道 與1電子移動率通道可在同一晶圓 用異質結構帶來的通道悄變+曰有使 U心也π有由π件製程衍生的引致 句口Ρ 應力(induced localized stress )。 著垂2=直P ^通道電晶體的兩個實施例被解釋。接 補碌半的兩個實施例被描述。製作方法也被描述。 【實施方式】 埃和2 Γ=間距分別為3.567埃(-一)、训 ;D广,(b·⑷拉伸應變存在於鬆_犧 或鬆他销或錯基板上的擬形石夕中, 一未者在㈣材料中,成長平面(表面 13 I3t)2740 幕“ >Γ ΐι修®正替換頁 wiibybU'-- 97年5月28曰修正-替換頁 而成長方向(垂直於表面)中有較小晶格間距。另一方面,壓 縮雙軸應變存在於鬆他石夕上的擬形石夕鍺、或鬆他石夕錯上的擬^ 鍺中,其意味著在擬形材料中,成長平面(表面)中有較小晶 格間距,而成長方向(垂直於表面)中有較大晶格間距。添= 小量的碳(小於1%)於鬆弛矽上的壓縮應變矽鍺,可以補償 且減少矽鍺中的應變。應變改變了應變材料的帶結構。因此, 應變:能影響能帶偏移、等效質量、及絲密度。參照圖式, 圖1藉由曲線2與3分別顯示矽上壓縮應變SiGe或SiGe(c) 的傳導帶與價帶。電洞被限制在壓縮應變SiGe(c)中,其具有 高電洞移解,而此材料祕適於p型金氧半場效電晶體二 •圖2藉由曲線4與5分別顯示鬆弛矽緩衝層上拉伸應變 SiHCy的傳導帶與價帶。赌形中,電子被限制在拉伸應變 StyCy中’其具有高電子移鱗,而此材料系統適於^型金氧 半場效電晶體]此外,圖3藉由曲線6與7分麵示雜上拉 伸應變梦的傳導帶與價帶。f子被限制在拉伸應财中,其潛 在地具有高電子移動率,而此材料㈣適於n型金氧半場效電 晶體。此三材料系統巾,通道可為表面通道或埋式量子井通 I圖1至圖3中’縱座標代表能量,而橫座標代表深度。 圖4顯示-垂直元件16〇之上視圖(未照比例)。圖^顯 =該垂直元件之第—實施例之剖面圖,其為—壓縮應變 iGeC垂直p齡氧半場效電晶體,包含—垂錄㈤ 00垂直柱5000包含幾層或區域在側壁上,像是源極層咬 區域164、體極層或區域163、沒極層或區域162、通道層或 區域165、絕緣層或區域166、閘極層或區域167。垂直柱或 14 1302740 I ^ 2 y !年月3修(助正替換頁丨 1^^^3445950-—〜… ! 97年5月28曰修正' w千0月“ ϋ修正-替垧百 口面6000形成垂直元件16〇。當作為源極層164之矽鍺芦或 區域被尚度應變,其臨界厚度(criticalthickness)反而小。声 +應變越大,應魏開始獅的臨界厚度就越薄。於此技蓺 中,臨界厚度被理解為缺陷在一層或區域中產生之處的厚度二 缺陷產生係為了減輕其應變使得此層或區域往其自铁晶 距鬆弛。此晶格間距係由層之成份決定。例如錯的晶格間^ 矽的晶格間距的1.04倍。石夕鍺層中含5〇%的鍺,會預期其曰 格間距為石夕的晶格間距的1〇2倍。此實施例中,一鬆弛石夕: 或區域、多祕層或區域、或多晶魏層或區域形成於; 為源極層164之應變石夕鍺層上,並一起形成有足夠厚度供石夕化 的合成源極。該層410可依期望般厚,而源極層或區域164之 厚度小於或約為臨界厚度。 此元件具有以下結構特性: 1) 汲極層162為P+型單晶矽,其濃度水平大於1χ1〇19 /立方公分(atom/cm3)。 . 2) 體極層163為η型石夕,而摻雜水平被調整以達到期 臨界電壓(threshold voltage ); • 3)汲極層162上方的作為碳摻雜磊晶層或區域21〇之p型
SiGeC層係用以減少從汲極層162入體極層163的刪廣散;該 層21〇具有一 P型濃度水平大於1χΐ〇19原子/立方公分。 4) 源極層164為p+型壓縮應變錯、GeC或如⑷,以及鬆 他石夕或多轉或多晶補41〇,兩者皆具有—?型濃度水^ 於lxlO19原子/立方公分; 5) 通道層165為壓縮應變siGeC或矽,且沿箭頭1〇4所示 的電流方向沒有異質能障; 、 15 1302740 年月π修(更)正替换頁 ^^»145950 -——— 97年5月28日修正-替換頁 6) 源極層164與體極層163間在介面570形成有應變 SiGeC/Si異質接面,且較佳的是,與源極/體極冶金 (metallurgical) p/n 接面對齊; 7) 閘極層或區域167為導電層,重疊體極層163上方從源 極層164到汲極層162的整個通道層165,並有絕緣層166在 它們之間。 8) >及極、源極和閘極電極169、170、171與汲極層162、 合成源極層164加410、及閘極層167分別耦合。 9) 基板或層161可為主體矽(bulk silic〇n)或絕緣層上矽 基板或絕緣層上石夕鍺。 作為閘極介電層或區域之絕緣層166可為一氧化物,氮化 物,石夕之氧氮化物(〇Xynitride 〇f silic〇n),與給㈣、銘⑽、 鍅⑼、鑭(La)、紀⑺、组(Ta)之氧化物及石夕酸鹽(silic 的單獨或組合。 作為傳導層或區域之閘極層167可為—金屬、金屬石夕化 物、摻雜的多晶矽、或摻雜的多晶矽鍺、 該層210.被摻雜為p型,範圍為1χ1〇19 方公分。 針1九 該層或區域410被摻雜為ρ型,範圍為ω〇19至㈣21 原子/立方公分。 π低雊訊應用中,較偏好埋 金氧半場效電晶體如圖6所示。1二通逼ρ型 ^ 丁 夕巾目盍層或區域175於閘極 平飞化刚形成。此情形中,應_鍺量子井之通道層165可= 16 Ι3Ό2740 ^ 5, 28 , W修⑽^正參綠 於_1'_…〜— 97年5月28日修!— 移” ’因為沒有表面粗麵::了:㈣ &域175,圖6與圖5相同。 曰乂 注意以上實施例為不對稱元件,只於源極 即介面570有異質接面。在某 層間, 路,這些耕較佳為對^包應財例如傳輸閘極電 本發明第四實施例,如圖7所示,為一表面通 半場效電晶體90卜其與第一實施例有類似結構,但具有2 =通道以及合成及極:此合成汲極包含一薄壓縮應變如^ __與作為汲極層I62之石夕層或區域。此結構中,作 層164之SiGeC層或區域可能或可以有相同應變量二區 域900可為p型,濃度水平大於1χ1〇19原子/立方公分,碳換 雜區域900可被摻雜為ρ型,範圍為1χ1〇19至以丨沪原子 方公分。因此在源極與汲極接面的異質能障有相同 此元件接近一對稱元件。 b 圖8A和圖8B顯示一(100)矽基板上一垂直11型金氧半場 效電晶體與-垂1: p 551金氧半場效電晶體之台面結構或垂直 柱結構的方向之上視圖。圖8A中11與1)通道皆在(11⑺家族的 平面中。即使(110)平面中的電洞移動率高於(1〇〇)平面的,電 子移動率相較(丨00)平面較差。然而,當η型金氧半場效電晶 體的台面結構或垂直柱結構自晶圓凹口線(wafer n〇tch丨丨加) 方疋轉45度,台面結構或垂直柱結構的四個侧壁上的n型通道 會在(001)、(〇1〇)、(〇〇1)和(010)平面中,如圖8B所示。同時, 在圖8B中,p型金氧半場效電晶體的台面結構或垂直柱結構 17 1302740 37 ^ r .p 卓·為‘1修(更)正替換頁 .M^: ____ ^ . ία^ 97年5月28日修正-替換苜 有一側謂準晶圓凹口線,而台面轉或垂直柱結構的側壁上 的ρ型通道會在_、_)、_)和(oil)平面中。因此,如 圖=所示之垂直互補金氧半的佈局可同時達到高電洞移動率 ”门电子移動率。應〉主思的是,圖8β所示之方向設計可被用 於任何垂直金氧半場效電晶體,例如有或沒有—取代間極 ^>iacementgate)的石夕垂直金氧半場效電晶體,以及本說明 曰中描述的異質接面金氧半場效電晶體。 圖9顯示一垂直互補金氧半反相器262之實施例,包含一 2 η型金氧半場效電㈣74與―p型金氧半場效電晶體 。此台面方向如圖8Β所示,ρ型通道台面或垂直柱結構 5〇00側壁在平面_中,η型通道台面或垂直柱結構3麵侧 i在平面⑽)中。元件隔離由絕緣層區域或毯覆介電層 /blanket dielectric layers) 168、148 和 68 提供。n 型金氧半場 效電晶體74有-拉伸應變SiGeC之源極層64,如果汲極層 62被摻雜磷,n型金氧半場效電晶體%還有一碳換雜之 〜Gedw 魏極中以減少磷槪&型金氧半場效 電晶體有-壓縮應變SlGeC源、極層164,如果沒極層162被推 ’ P型金氧半場效電晶體還有一碳摻雜蟲晶層21 〇於没極 中以減少刪紐。兩個元件皆有⑪表面通道層65、165。作為 =齡電層之絕緣層或區域66、166可為氧化物、氧氮化物、 Ί尚介電係數介電質、或它們的結合。閘極層67、167可為 具能隙中功錄(涵娜_k &η_η)的_金屬,或是 具適當功函數的兩種不同金屬,或是_金氧半場效電晶體用 η型多晶石夕或多晶石夕錯、p型金氧半場效電晶體用p型多晶矽 或多晶_。垂餘結構6_形成p型錄半場效電晶體 18 1302740 5. 28 干月 β修(史un. 案聽·1595D 97年5月28日修正_替換頁 74 〇 一 一 一·》v i; 26。。垂直柱_結構形成鳴半場效= -鮮備—反相騎方法,此反 政互補金氧半電晶體組成,包含下列步驟所不之垂直场 做01上,糁雜作為汲極層62 卞日日土 大於1X1❼恤方公她她域為„型,至- 之晶層輕域W η獅級極層62 層或== 作之:體:層6,域㈣-咖 為ρ型; 作為體極層63之石夕蟲晶層或區域63 作為::==巧晶層或區域於。型 應變从靖或 公分的濃度水平; 、 原子/立方 蟲晶區?,n型作為源極層64之應變轧·Α ω〇;原子/立方公分區域45G為η型,至一大於 62之:ί:ΐΐί如〇〇1 ’包含至少-侧壁自物及極層 鄕區域 轡Si r石曰日日層或區域、弟四層應 l-yCya曰曰層或區域上方,至矽層或區域#兄; 二:=順區域於垂直柱結侧^ 形成-作為間極介電層之絕緣層或區域的於作為通道層 19 1302740 ψ. 5.2 8 , 牛月日修(更)正替換頁 •^謔.9311 咖η — 97年5月28日修正-替換頁一 65之矽層或區域上方; 上方形成-作為酿層67之導電層或區域於絕緣層或區域66 遮罩與綱—鄰近區如暴露單晶基板61; 雜大於1X1019原子/立方公分的濃度水平的一 Ρ 线^極層162之销或_於—第-單晶基板⑹上; 或區域上方’碳摻綠晶層或區域
原子/立方公分的濃度水平; A^lxlO 層或極f 163之矽磊晶層或區域於碳摻雜磊晶 n曰型〆 方,4雜作為體極層⑹之綠晶層或區域為 區域164ίί縮應變 層⑹之壓扩廡1 ·之石夕蟲晶層或區域上方,摻雜作為源極 二域交SWqGewCq蟲晶層或區域為型 於1X10原子/立方公分的濃度水平;至大 石夕層或區域於作為源㈣164之該 或區域上方,摻雜石夕層或區域4 一大於1X10 9原子/立方公分的濃度水平; 至 垂^柱結構,包含第—層作為""及極層162之 3或£域、弟二層碳摻縣晶層或區域加、第 極層163之石夕蟲#爲+厂上# 9 马體 a或區或、弟四作為源極層164之壓縮應變 i-W'q/W 晶層或區域、以及第五矽層或區域410; 直柱:=1為通道層165之應變Si1—sGe顧區域於上述垂 ^ 5000 1] (outer perimeter) _L ^-; 形成—作為開極介電層之絕緣層或區域I66於上述作為 20 1302740 if/, ϋ. j'F Π 瘦 案號:93 Η595θ- 一------------ 97年5月28日修正-替換頁 通道層165之層或區域之外圍上方,以及 區域m層167之_祕域社舰緣層或 上述方法更包含下列步驟·· ^二毯覆介電層68於整個垂直柱結構麵上方; 電極69之導電層或區域穿過上述毯覆介 尾層68接觸n型作為汲極層泣之矽磊晶層; 電声極7G之_或“穿過上述毯覆介 結構_頂上切層或區域桃 電戶68,接極71之導電層或區域穿過上述毯覆介 結構麵相上之糊極㈣之導 形成一毯覆介電層168於整個垂直柱結構_〇上方; 介電=作2汲㈣極169之導電層或區域穿過上述毯覆 電層168 ’接觸ρ型作為汲極層162之矽層或區域; if 17G導錢或區域穿過战毯覆介 二〇曰;68’接觸上述垂錄結構5_頂上之?财層或區域 人形成一作為閘極電極171之導電層或區域穿過上述毯覆 "電層168 ’接觸垂直柱結構漏外圍上之作為閘極層167 之導電層或區域,以及 形成-毯覆介電層M8於單晶基板61上、介於兩個垂直 柱結構4001和6000間,作為元件隔離。 且垂直於 垂直柱結構3001之側壁較佳係於平面(1〇〇)中, 21 f 1302740 基板平面。 5· 2 » h日修(更)正替換頁 ^t.aau5〇5ft 97年5月28日修正-替換頁 垂直柱結構5000之側壁較佳係於平面(11〇)中,且垂直於 基板平面。 产圖10顯不垂直互補金氧半之第二實施例362,除了 η型 金氧半場效電Μ 374外,類似圖9。η型金氧半場效電晶體 374有-拉伸應變料道層65建立在一鬆弛魏體極層幻 上。體極層63相對於作驗極層62之實質基板為鬆弛的。有 拉伸應變々作為通道的伽是較高的電子移 或台面麵方向如圖8B所示,其中P型通道在平面⑴^中構 η型通道在平面⑽)中’以有更高電洞與電子移動率。 丰雷11 _法’此反相11由垂直場效互補金氧 半電日日體組成,包含下列步驟·· 一时形成-作為汲極層62之鬆弛知Ge々晶層或區域於一第 3晶基板61上’摻雜作為汲極層62之_⑭晶層或區 或為η型’至-大於_19原子/立方公分的濃度水平; 形成-碳摻雜矽鍺磊晶層或區域3〇〇於n型作為没極層 域^ilGei層或區耻方’獅此碳摻雜之贿蟲晶層或區 型,至一大於1x1019原子/立方公分的濃度水平; 雜石夕極層63之鬆弛Sil-lG^晶層或區域於碳摻 濉矽鍺磊晶層或區域300上方,換雜作 別咖蟲晶層為㈣;方“隹作為體極層63之鬆弛 之作t源極層64之拉伸應變石夕蟲晶層或區域於p型 作為脰極層63之他Sli-iGei蟲晶層或區域上方,推雜該 22 1302740 !个稷^正替換頁 L 案號一93445 齡―..·— 97年5月28日修正-替換頁一〜 ,至一大於lxl〇19 作為源極層64之拉伸應變綠晶層為η型 原子/立方公分的濃度水平; 極層:^=0==—之該作為源 45〇 Λ η ^ 夕日層上方,摻雜該鬆弛SiuGq之矽層 t,加XlGl9卵対公分的濃度水平; & S Ϊ柱結構細,包含至少—趣自作為汲極層 :厗1ΐΛί層延伸過第二層應變碳摻雜石夕鍺層3⑻、第 —層P型作為體極声63之步si? q· r αλ-之廡心二 氣1你、第四層作為源極層64 之應瓞矽上方,至該矽層450; 成至二上之r夕層或區域於垂直柱結構 方;形成-縣層或區域66_騎· 65之補或區域上 上方形成-作為_層67之導電層或區域於絕緣層或區域66 遮罩與_—鄰近區域以暴露單晶基板161; 料t成具有—大於lxl()19原子/立方公分的濃度水平的一 P 為没極層162石夕層或區域於一第一單晶基板161上; 形成-碳摻雜蟲晶層或區域210於層或區域162上方,播 τ s 2ω為p型’至一大於lxl〇i9原子/立方公分的濃度水平; 开v成作為體極層163之石夕蟲晶層或區域於層21〇上方, 摻雜層163為n型; 形成一作為源極層164之壓縮應變Si—GewC^晶層或 =於層⑹上方’摻雜作為源極層164之% wqGewCq層為 p 土’至-大於Ixio19原子/立方公分的濃度水平; 形成-石夕層或區域410於作為源極層164之Sii wqGewCq 23 (Ι3Ό2740 lO^pQ ______ 層或區域上方,摻雜之石夕 97年5月28日修正-替換頁 /立方公分的濃度水平;為?型,至一大於_19原子 形成一垂直柱結構5000,包含作 層、第二層礙摻雜声 H乍為及極層⑹之第-石夕 第四作為源肺16曰4 一运作為體極層⑹之石夕蟲晶層、 =源極層164mwqGewCq層、以及第树 形成一作為通道層165之應變s ", 直柱結構5000之外圍上方;,r你層或區域於上述垂 ====166於增165之相上方,以及 之外圍ί方閉極層167之導電層或區域於上述絕緣層166 上述方法更包含下列步驟·· 形成—毯覆介電層68於整個垂直柱結構侧上方· 形成一作為汲極電極69之導雷居 ’ 電屑68,V電層或區域穿過上述毯覆介 二==為_62之^⑽層或區域; 電居極7G之_細_上述毯覆介 更層68、’辆上輕餘結構侧頂上切層顿; 形成一作為閘極電極Μ 電層68,接繼錄輯穿過上述毯覆介 或區域67,· 、、。構4001外圍上之作為閘極層之導電層 形成-毯覆介電層168於整_直構 形成-作為汲極電極169之導Huo上方, 介雪层彳从拉細 之泠电層或區域穿過上述毯覆 开^ - = 物藤層162切層或區域,· 電屬觸i原170導電層或區域穿過上述毯覆介 开I -構糊頂上之p财桃 形成-作為間極電極171之導電層或區域穿過上述毯覆 24 13.02740 ! ,97.5.2^ ,) j」丨-H镇..¾正香按頁 iH9311595a— — 97年5月28日修正-替換頁 ,丨笔層168,接觸垂直柱結構5〇〇〇夕卜圍上之作為間極層π? 之導電層,以及 形成-毯較電層U8於單晶基板61 ±、介於兩個垂直 柱結構4001和6000間,作為元件隔離。 垂直柱結構3001之侧壁較佳係於平面(1〇〇)中,且垂直於 基板平面。 垂直柱結構5000之侧壁較佳係於平面(11〇)中,且垂直於 基板平面。 根據較佳實關,本㈣更包錢錢移鱗異質接面p 型金屬絕緣體半導體場效電晶體的製程整合方案: 、磊晶成長數層之一堆疊,供作汲極、體極、和源極,伴隨 或不伴隨原位(in situ)摻雜; 圖案化则以形成-台面5000、或台座(pedestal)、或 枕(pillow)、或柱(c〇iumn)、或鰭(fm); 磊晶成長通道層165、帽蓋(cap)層(若需要)於台面、 台座、枕、柱或鰭之側壁上; ^成長或沉積絕緣層,其可為氧化物'氧氮化物、其他高介 電係數介電質、或它們的結合; 〃 成長或沉積閘極電極層於台面、台座、枕、柱或鰭之側壁 上,閘極電極層可為多晶矽、多晶矽鍺或金屬; 圖案化/飯刻閘極電極,形成最後的垂直柱結構6〇〇〇 ; 曰離子佈植及退火,假如源極、汲極、體極、或多晶矽或多 晶石夕鍺閘極電極沒有原位摻雜; 25 ,1302740 年月6修(更)正替換頁 菜號:咖卿_5,〇--- 97年5月28日修IE-胃^胃 閘極圖案化及蝕刻; 沉積場氧化物; 做接觸開口; 矽化(silicidation)源級極;以及 金屬化及金屬燒結(sintering)。 應之參 應主思的是’圖式中類似元件或成分參照類似且對 考編號。 、、 包含高移動率通道與較佳地與源極及/或汲極接面相符的 異質接面的半導體元件,已被描述與轉。_此技藝者而t ,顯的是,不脫離本發明寬廣範_的修正和變化是可:的。I 這些修正和變化應專屬地被所附申請專利範圍的範疇限制。 【圖式簡單說明】 ·· 考慮本發明詳細說明時,若與圖式一同閱讀,本發明的以 上及其他特徵、目的和優點會變得明顯,其中·· 圖1為在立方(cubic)矽上的壓縮應變矽鍺或SiG _ 能帶圖。 圖2為在立方矽上的拉伸應變sic的能帶圖。 圖3為在鬆弛矽鍺緩衝上的拉伸應變矽的能帶圖。 圖4為一垂直通道金氧半場效電晶體之上視圖。 广圖5為一垂直壓縮應變矽鍺/石夕或SiGeC/Si表面通道p型 ^氧半場效電晶體之剖面示意圖,此電晶體具有含碳之擴散阻 障層’以及由鬆秘層與應變SlGeC層組成的合成(咖㈣如) 源極區域。 26 Ι3Ό2740 W. 5. '卜月曰修( S^sausasa. 替換: 金氧二t:垂直壓縮應變辦或弧 體之剖面示意圖,此電晶體具有含碳之^阻 θ 7 A #層與雜SiGeC層組㈣合成祕區域。 金ι^ί 一垂直壓縮應變销辦或驗⑽表面通道P型 兩者比=電晶體之剖面示意圖,此電晶體在源極與汲極接面 兩者皆具有異質接面。 么圖和圖8Β為-(1〇〇)基板上一垂直互補金氧半反相器 口面結構(mesastmcture)或垂直柱結構的方向之上視圖。 q入,9為根據本發明之一垂直互補金氧半的剖面示意圖,n ^金氧半場效電晶體有拉伸應變SiC源/汲極,而p型金氧半 場效電晶體有壓縮應變SiGeC源/汲極。 圖10為根據本發明之一垂直互補金氧半的剖面示意圖,n 型金氧半場效電晶體有伸拉應變矽源/汲極,而p型金氧半場 效電晶體有壓縮應變SiGeC源/沒極。 【主要元件符號說明】 2〜7 曲線 104箭頭 148 毯覆介電層 160 垂直元件 161,61基板或單晶基板 162,62 汲極層或區域 163, 63 體極層或區域 164, 64 源極層或區域 165, 65 通道層或區域 166, 66 絕緣層或區域 27 1302740 年月日修(®正替換頁 案號:9311505Θ---- 97年5月28日修正-替換頁 167, 67 閘極層或區域 168, 68 毯覆介電層 169, 69 >及極電極 170, 70 源極電極 171,71 閘極電極 175 矽覆蓋層或區域 210碳摻雜磊晶層或區域 260 p型金氧半場效電晶體 262, 362垂直互補金氧半反相器 300 SUjGeiCj或矽鍺磊晶層或區域 3001,4001,5000, 6000 垂直柱結構 374, 74 η型金氧半場效電晶體 410 鬆弛矽層或區域、多晶矽層或區域、或多晶矽鍺層或區 域 450 鬆弛SiHGei之矽層或區域 570 介面 900 SigeC 層 901 表面通道p型金氧半場效電晶體 28
Claims (1)
1302740 If i. 手月日 修便)正替換頁丨 案號·产 97年9月1日修正一替換買 十、申請專利範圍: 1. -種準備-場效電晶體之—垂直通道的方法包含以下步驟: 提供-第-p型單晶_域於—第—基板上,該第—p型單 =石夕區域具有—大於㈣、他方公分(atoms/em3)的濃度水 平, ㈣第二碳摻齡晶區域於該第—p型單晶魏域上方, 摻雜該苐二碳摻縣晶區域為p型,至-大於副19原子/立方公 分的濃度水平; -第三㈣域於該第二碳摻齡㈣域上方,摻雜該第 二双區域為η型; =成-第四壓縮應變Sil,GewC^晶區域於該第三石夕區域上 方,^雜該第四壓縮應變SiiwqGewC ω〇19原子/立方公分的濃度水平; ^至大於 μ Jtf五,晶區域於該第四壓縮應變ng晶區 =::r娜域為-,至一9原子/立 。形成-垂直柱結構’該垂直柱結構包含至少—側壁自 型單晶矽區域、第二碳摻雜μ區域 變Si1:qGe,挪域、以及第五㈣區觀I㈣喊 形成-第六壓縮應變sii sGes區雜該垂直減構之該至少— -區域亡方’自該第二碳摻雜磊晶區域延伸過該第三矽區 或上方、至糾四壓縮應變蠢晶區域。 2·如申請專利範圍第1項所述之方法,更包含: 上方形::閘極介電區域於該第四壓縮應氣萬 29 1302740 年及I· 修(更)正替換頁 宇轉.cmi fiQfin w丄、、若Λ 97年9月1日修正-替換頁 形成一導電區域於該閘極介電區域上方。 3·如申請專利範圍第1項所述之方法,更包含: 形成-毯覆介電層於-整體垂錄結構上方; 形成第-導電介層穿過該毯覆介電層,接觸該第一 ρ型單 晶砍區域; 形成-第一導電介層穿過該毯覆介電層,接觸該垂直柱結構 頂上之該第五矽磊晶區域;以及 开7成第—‘電介層穿過該毯覆介電層,接觸該導電區域。 《如申請專利範圍第i項所述之方法,其中該第一 ρ型單晶石夕區 ^ L第二石夕區域和第五石夕蟲晶區域、第二碳摻雜蠢晶區域、第四 壓縮應變Si^qGewCqi晶區域和第六壓縮應變siisGes區域係藉 -製程形成’該製程選自娜CVD、rtcvd、LpcVD、ApcvD 和MBE所組成之群組。 5·、如^睛專利範圍第2項所述之方法,其中該第一 P型單晶石夕區 域係藉-製程摻雜為p型,該製程選自離子佈麵後退火或原位 摻雜所組成之群組。 6.如申請專利範®第1項所述之方法,其帽第五綠晶區域相 對該第四壓縮應變swqGewc#晶區域之上表面為鬆弛的。 30 1 為單晶矽或多晶矽或多晶矽鍺。 2 π如申料利紐第2項所述之方法,其中該第五綠晶區域可 1302740 m. 9λ «ι ί—·匕· r‘ :.φ 案號:^3115950 97年9月Γ曰修正—替換貨 8·如申請專利範圍第1項所述之方法,其中該垂直柱結構係藉一 製程形成’該製程選自反應式離子餘刻及離子束移除所組成之群 組0 9·如申請專利範圍第1項所述之方法,其中該垂直柱結構之該侧 壁係於晶體平面(100)中,且與該第一基板平面垂直。 10·如申請專利範圍第1項所述之方法,其中於該垂直柱結構之該 侧壁上的該第六壓縮應變Si^Ges區域相對於該第一 ρ型單晶石夕區 域係應變的。 _ 11.如申請專利範圍第2項所述之方法,其中該閘極介電區斯系選 自氧化物、氮化物、石夕之氧氮化物、與铪㈣、銘(A1)、錯⑼、 鑭(La)、紀⑺、组(Ta)之氧化物及石夕酸鹽的單獨或組合所組成之 組0 、 12.如申請專利範圍第2項所述之方法,其中該導電區域係選自金 屬、金屬石夕化物、換雜的多晶石夕和掺雜的多晶石夕錯組成之群組。“ I3·如申請專利範圍第!項所述之方法,其中該第 域被摻雜為p型’範圍為lxl俨至1χ妒原子/立方公分雜麻曰曰〔 ϋ中請細繼1項所述之方法,其巾鄉五綠晶區域被 推雜為ρ型,至範圍為lxl〇19至⑽21原子/立方公分的水平。 •如申請專利範圍第i項所述之方法,其中該第六壓縮應變 31 1302740 修暖)正替換頁i 案號 j~93445950 —----------------- _ 97年9月1曰修正一替換頁 %仇區域於該第一 p型單晶石夕區域 ;:二=換: 禾一衩摻雜磊晶區域、第 動养雜Γ WqGewCq蟲晶區域和第五石夕蟲晶區域旁的區域被自 ==為P型,而退火後’於該第球區域相區域被自動摻雜 •如H概圍第〗項所述之方法,其_六壓縮應變 的自動摻雜以及該些摻雜區域中該些摻雜物的活化 輪,該製程係選自快速退火、爐管退火 所組成之群組。 17·二種準倩_場效電晶體之—垂直通道的方法,包含步驟: 提供-第-P型單晶魏域於—第—基板上,該第—p型單 晶石夕區域具有-大於lxl()19原子/立方公分的濃度水平; 形成-第二碳摻雜蟲晶區域於該第—p型單晶石夕區域上方, ㈣该第二碳摻雜蟲晶區域為p型,至_大於㈣19原子/立方公 分的濃度水平; …形成-第三石綠晶區域於該第二碳摻雜蠢晶區域上方,接雜 该第二石夕蠢晶區域為η型; ” 形成-第四墨縮應變SiiwqGewCq蟲晶區域於該第三石夕遙晶區 域上方,^雜該第四壓縮應變SiiwqGewCq蟲晶區域為?型,至一 大於1x10原子/立方公分的濃度水平,· 形成-第五石夕蟲晶區域於該第四壓縮應變SU qG〜Cq蟲晶區 或上方,&雜該第五石夕蟲晶區域為P型,至-大於lxl〇19原子/立 方公分的濃度水平; 。。形成-垂直結構’該垂直結構包含至少一側壁自該第一 p型 早晶石夕區域^晶區域、第三料晶區域、第四壓縮 32 1302740 應憂Sii_w_qGewCq遙晶區域、以及第五秒蠢晶 案號:如15950 . 97年9月1日修正-替換頁 區域延伸; 形成一第六壓縮應變SileSGes區域於該垂直結構之該至少一側 壁之區域上方,自該弟一碳摻雜蠢晶區域延伸過該第三石夕蟲晶 區域上方、至該第四壓縮應變Sil-w_qGewCq磊晶區域;以I猫阳 形成一第七矽區域於該第六壓縮應變Sii sGes區域上方。 18·如申請專利範圍第17項所述之方法,更包含: 形成一閘極介電區域於該第七石夕區域上方; 形成一導電區域於該閘極介電區域上方。 19·如申請專利範圍第18項所述之方法,更包含: 形成一毯覆介電層於一整體垂直柱結構上方; 形成-第-導電介層穿職毯覆介電層,接_第—p型單 晶砍區域, 形成一第一導電介層穿過該毯覆介電層,接觸該垂直結構頂 上之該第五矽磊晶區域;以及 开>成-第二導電介層穿過該毯覆介電層,接觸該導電區域。 20·如申請專利範圍第17項所述之方法,其中該第一 p型單晶矽 區域、第三矽磊晶區域和第五矽磊晶區域、第二碳摻雜磊晶區^、 第四壓縮應變Slhw—qGewCq磊晶區域和第六壓縮應變區域 係藉一製程形成,該製程選自UHV-CVD、RTC:VD、UPCTO、 APCVD和MBE所組成之群組。 21.如申請專利範圍第17項所述之方法,其中該第一 p型單晶石夕 區域係藉一製程摻雜為P型,該製程選自離子佈植隨後退火及原 33 1302740 位摻雜所組成之群組。 ^ i年··对自修(更)正替換頁1 案號:知4印Rn _] 7年9月1曰修正一替換頁 22·如申請專利範圍第Π項所述之方法,复中 相對該第四壓縮應變SWqGewC^晶區域之上;面為==區域 其中該第五矽磊晶區域 23·如申請專利範圍第17項所述之方法, 可為單晶矽或多晶矽或多晶矽鍺。 24.如申請專利範圍第17項所述之方法,其中該垂直結構係藉一 製程形成’該製程選自反應式離子侧及離子束移除所組成^一 垂直結構之該侧 25·如申請專利範圍第Π項所述之方法,其中該 壁係於晶體平面(100)中,且與基板平面垂直。 26.如申請專利範圍第17項所述之方法,其中於該垂直結構之該 侧壁上的該第六壓縮賴Sil_sGes區域姉於該第_ p 域係應變的。 卞阳 27.如申請專利範圍第18項所述之方法,其中該間極介電區域係 選自氧化物,氮化物,石夕之氧氮化物,與铪_、銘(A1)、錯⑼、 鑭(La)、紀⑺、叙(Ta)之氧化物及魏鹽的單獨或組合所組成之群 組。 28.如申請專利範圍第18項所述之方法,其中該導電區域係選自 金屬、金屬石夕化物、摻雜的多晶石夕和摻雜的多晶石夕錯組成之群組。 34 1302740 i 4修(句正替換頁 案號 U3445950~„—一 ^ 97年9月1日修正—替換頁 晶 圍第17項所述之方法,其中鄕三碳播雜蟲 £域被推雜為ρ型,範圍為㈣19至1Χ1021原子/立方公分。 30·如申請專利範圍第17項所述之方法,其中該 被掺雜為P型,至筋圍发 19 2;,4 21 猫日日區或 P至犯圍為1x10至1x1021原子/立方公分的水平。 31. 如申請專利範圍第17項所述之方法,其中 &i-sGes區域與第七石夕區域、 t 石戌於如P型早晶石夕區域、第二碳摻雜 旁的^祐白M SWq(}eweq蟲晶區域和第五石夕蠢晶區域 方的£域被自動摻雜為p型,而退火後,於該第三 ^ 的區域被自動摻雜為n型。 日日&或方 32. 如申請專利範圍第17項所述之方法,其中 SU-sGes區域和第七石夕區域中的 巴、,= 摻雜物的活化係藉—|y純r 抑」,雜£域中該些 火及雷射退火所製程係選自快速退火、爐管退 33. 場效電晶體之一垂直通道的方法,包含以下步驟: 曰矽Ρ型早晶魏域於—第—基板上,該第—Ρ型單 形成一第二壓縮應變Si Ger石曰 石夕區域上方,細ρ广 域於该弟一 Ρ型單晶 至一大於了相二壓縮應變Si—GexCy蟲晶區域為ρ型, 至大於_原子/立方公分的濃度水平; 域上:成;t二鳩區域於該第二壓縮應變Sll_”GexCy磊晶區 一、上方摻雜该弟三矽磊晶區域為n型; 35 1302740
.專m ΜΨ,: 93115950 ^ 97年9月1日修正一替換頁 、心成第四壓縮應變Si^-qGewCq蟲晶區域於該第三石夕羞晶區 域上方,獅_第四壓縮應變Sii_wqGewCq蟲晶區域為㈣,至一 大於1x10原子/立方公分的濃度水平; 、形成-第五石夕蠢晶區域於該第四壓縮應變s磊晶區 域上方,摻雜該第五石夕蠢晶區域為p型,至一大於ΐχΐ〇19原子/立 方公分的濃度水平; ” 形成-垂直結構,包含至少―側壁自該第—ρ型單晶石夕區域、 第了壓縮應變Si—GexCyi^l!域、第三綠晶區域、第四壓縮 應變Sl^qGewCq磊晶區域、以及第五矽磊晶區域延伸; 形成-第六壓縮應變Si“Ges區域於該垂直結構之該至少一側 壁之-區域上方,自該第二壓縮應變SiixyGexC々晶區域延伸過 该第二石夕蠢晶區域上方、至該第四壓縮應變%·#〜以晶區域。 34.如申請專利範圍第33項所述之方法,更包含: 形成一閘極介電區域於該第六壓縮應變叫我區域上方; 形成一導電區域於該閘極介電區域上方。 35·如申請專利範圍第34項所述之方法,更包含: 形成一毯覆介電層於一整體垂直柱結構上方; 形成-第-導電介層穿過該毯覆介電層,接觸 晶矽區域; p 土平 形成-第二導電介層穿過該職介電層,接觸誠直結 上之該第五矽磊晶區域;以及 、 形成-第三導電介層穿過該毯覆介電層,接戦導電區域。 见如申請專利範圍第%項所述之方法,其中該第一 p型單晶石夕 36 1302740 案號 年月β Μ修(受)正替換頁 ^ 97年9月1日修正一替換頁 區域、弟三梦m域和第五#晶區域、第二壓縮應變 Si^GexCy蟲晶區域、第四壓縮應變Si—ο%蠢晶區域和第六 壓縮應變SiuGes區域係藉-製程形成,該製程選自uhv_cvd、 RTCVD ' LPCVD、APCVD和MBE所組成之群組。 3义如申請專利範圍第33項所述之方法,其中該第三雜晶區域 係藉-製程摻雜為η型’該製程選自離子佈植隨後退火及原位換 雜所組成之群組。 ^ 18料=請ί利細第33項所述之方法,其中該第三_晶區域 相對該苐二壓縮應變Sll_xyGexCyj^晶區域之上表面為鬆弛的。 说如申請專利範圍第33項所述之方法,其 相對該第四壓縮應變SWqGewCqg晶區域之上表面為域 J為早日日矽或多晶矽或多晶矽鍺。 請專利範圍第%項所述之方法,其中該垂直結構係藉一 組二7 ’销程選自反應式離子蝴及離子束移除所組成之群 33項所叙方法,其巾該_構之該側 土只貝上係於晶體平面⑽)中,且與該第—基板的平面垂直。 43.如申請專利範圍第33項所述之方法,其中於該垂直結構之該 37 (对江I、(是j正赛 案號:Qk咖η __ 97年9月1曰修正一替換頁 1302740 替換頁 :=第六壓縮應變SiuGes區域相對於該第-。型單: :自如申氣 1Γ範圍Γ7所述之方法,其中該閘極介電區域係 化物,I化物,秒之氧氮化物,與Hf、^、&、^、γ、 &之氧化物及石夕酸鹽的單獨或組合所組成之群組。 =屬如34項所述之方法,財該導電區域係選自 金屬、金屬石夕化物、摻雜的多晶石夕和摻雜的多晶石夕鍺組成之群組。 33項所述之方法,其中該第二_應變 i-x-yGexCy猫日日區域被摻雜為p型,範圍為ΐχΐ〇19至 立方公分。 界亇 17=ΓΓ顧第33項所述之方法,其中該第五綠晶區域 被摻雜為Ρ型,至細為副19至㈣21原子/立方公分的水平。 l8.G如專利1 刪33項所述之方法,其中該第六義應變 磊第一 P型單晶矽區域、第二壓縮應變SWyGexCy 四壓縮應變HQ蠢晶區域和第五綠晶區域 二二2動摻雜為P型,而退火後,於該第三石結晶區域旁 的區域被自動摻雜為η型。 s· Γ申月專利辜巳圍第33項所述之方法,其令該第六麼縮應變 上二:域中的自動摻雜以及該些摻雜區财該些摻雜物的活化 。措-衣程執行,該製程係選自快速退火、爐管退火及雷射退火 38 1302740 I 0 1 j个州替換f 案號:93115θ5θ—— , 97年9月1日修正-替換頁 所組成之群組。 50· —種準備一反相器的方法’該反相器由垂直場效互補金氧半電 晶體組成,該方法包含下列步驟: 形成一第一矽磊晶區域於一第一單晶基板上,摻雜該第一矽 蟲晶區域為η型,至一大於lxlO19原子/立方公分的濃度水平; 形成一第二Si^jGeiCj蟲晶區域於該第一石夕蟲晶區域上方; 形成第二砍蟲sa £域於遠苐二Si^jGeiCj遙晶區域上方,摻 雜該第三矽磊晶區域為p型; 少 形成一第四應變SLyCy磊晶區域於該第三矽磊晶區域上方, 摻雜該第四應變Sii_yCy磊晶區域為η型,至一大於1χ1〇ΐ9原子/立 方公分的濃度水平; ' ▲々形成一第五矽區域於該第四應變SiiyCy區磊晶域上方,摻雜 該第五魏域為n型’至—大於lxl()19原子/立方公分的濃度水 平; 形成一第一垂直柱結構,包含至少一侧壁自該第一矽磊晶β 過該!二SilijGeiCj蟲晶區域、該第三綠晶區域、該第已 心、交Si1-yCy磊晶區域上方,至該第五矽區域; 域上=成_第六㈣域於該第—垂直結構之該至少—侧壁之—逼 形成-第-閘極介電區域於該第六㈣域上方; 以二 域於該第一閘極介電區域上方; 二Ϊ ^近區域以暴露該第一單晶基板; 區域且有二Π區域於該第—單晶基板上,該第七P型石夕 开;二二 ω原子/立方公分的濃度水平,· 弟八油雜蟲晶區域於該第七Ρ财區域上方,換雜 39 年· IUS修(更)正替換頁 案號:*&»Ι45Θ6Θ 、 1302740 該第八碳摻雜蟲晶區域為ρ型,至 月1日修正-替換頁 濃度水平; 巧Κ至大於W9原子/立方公分的 μΓΪΓ第九料晶區域於該第人碳摻聽晶區域上方,摻雜 該弟九石夕蟲晶區域為η型; 雜 找上:成於:卜Sll,GewCq磊晶區域於該第九矽磊晶區 大於1x10原子/立方公分的濃度水平,· 形成1十-辦晶區域於該第十魏應變qG‘Cq蟲晶 Q域上方’祕該第十―石夕蟲晶區域為p型,至 子/立方公分的濃度水平·; 原 μ石?成:第5^柱結構’包含該第七p _區域、第八碳摻 ,晶區第九矽磊晶區域、第十壓縮應變Si—GewCq磊晶區 域、以及弟十一石夕蟲晶區域; 形成-第忙應變Si“%區域於該第二垂直柱結構之外圍 (outerperimeter)上方; 形成-第二間齡電區域於該第十二應變Si“Ges區域之外圍 上方; ‘ 形成-第二閘極導電區域於該第二閘極介電區域之外圍上 方0 51·如申請專利範圍第50項所述之方法,更包含: 形成一第一毯覆介電層於該第一垂直柱結構上方; 形成-第-導電區域穿過該第一毯覆介電層,接觸該第一石夕 蠢晶區域, 形成一第二導電區域穿過該第一毯覆介電層,接觸該第一垂 直柱結構頂上之該第五石夕區域;
, ® l,>{ ψΜ wl 案號:93ttS9S〇^Η1 97年9月1日修正一替換頁^---J 1302740 形成-第三導電區域穿 9;年: 直柱結糊上之該第1極輸電層接射弟—垂 :::ΓΐΓ電層於該第二垂直柱結構上方; 型石夕區域,·四V £域穿過該第二毯覆介電層’接觸該第七Ρ 直柱:構成二電十區― 直柱:二=— 第板上’且介於該第—鱼 第一垂直柱結構間,作為元件隔離。 /、 52. 如申請專利範圍第M項所述之方法,其中經 J四耦合至該第一導電區域,該第六導電區域耦合至: 弟二¥電區域,且該第五導電區域轉合至該第二導電區域。 53. 如申請專利範圍第50項所述之方法,其中該第一垂直柱結構 之側壁係於平面(100)中’且垂直於該第一單晶基板平面。 54. 如申5月專利範圍第5〇項所述之方法,其中該第二垂直柱結構 之側壁係於平面(110)中,且垂直於該第一單晶基板平面。 55. 如申請專利範圍第50項所述之方法,其中該第十二應變 Sii_sGes區域係一石夕層。 56·種準備一反相為的方法’ 4反相為由垂直場效互補金氧半電 41 1302740 案號:9幻15.91_.................... ( 97年9月1日修正一替換頁 換 晶體組成,該方法包含下列步驟: 兮第晶區域於一第—單晶基板上,摻雜 μ第-fc弛Su—區域為n型,至—大於1χΐ()19 立 分的濃度水平; 、 A ^成-第^摻神船晶區域於鄕—紐私你蟲晶區 成上方,摻雜該第二碳摻雜石夕鍺蟲晶區域 原子/立方公分的濃度水平; 主大於1x10 域上;^成捽^二弛^^ ^晶區域於該第二碳摻雜贿磊晶區 ^ #雜該第U SlwGei蟲晶區域為p型; _ =成:第四拉伸應變石夕蟲晶區域於該第三鬆他別说蟲晶區 ^上方’摻_第雄伸應變綠晶區 原子/立方公分的濃度水平; Λ^1χ1° 方t一Ϊ五鬆弛知邮域於該第四拉伸應變石夕蠢晶區域上 方,4雜該第五鬆弛Sil_iGei區域為 — 立方公分的濃度水平; 大於1x10原子/ 形成一第一垂直柱結構,包A 一 Sii-iGei磊晶區域,延伸過哕第 =* 土自該第-鬆弛 弛% Ge蟲曰^ 雜石夕錯蟲晶區域、該第三鬆 鬆他sU= _伸_編域上方,至該第五 之-2=;六毅魏域㈣m減構之駐少-側壁 =2:閘極介電區域於該$六應變頻域上方; 遮罩二域於?第-閘極介電區域上方; j 4近£域,以暴露該第-單晶A你· 區域:二大^ ===該第—軍晶基板上、第七P型石夕 否大於lxlG軒/対公麵濃度水平; 42 1302740 儿 y· UI 年月日修(更)正替換頁 案棘^9,341咖0 --- 97年9月1日修正一替換頁 〃形成-第八碳雜遙晶區域於該第七ρ财區域上方,捧雜 該第八碳摻雜蠢域為Ρ型’至—大於1χ1()19原子/立方公分的 》辰度水平, 形成-第九石夕遙晶區域於該第八破摻雜蠢晶區域上方,換雜 該第九秒蠢晶區域為η型; 、形成第十壓縮應麦Si—GewCqi晶區域於該第九石夕磊晶區 域上方,掺雜該第十壓縮應變別—⑹^蟲晶區域為p型,至一 大於lxlO19原子/立方公分的濃度水平; 形成-第十-石綠晶區域於該第十壓縮應變Si—G 晶 區域上方,摻雜該第十一矽磊晶區域為p型,至一大於ω〇 子/立方公分的濃度水平; μ 形成-第二垂直柱結構,包含該第七ρ型石夕區域、第八碳捧 雜遙晶區域、第九石夕遙晶區域、第十壓縮應變HCq磊晶區 域、以及第十一石夕遙晶區域; 形成-第十二應變Si“Ges區域於該第二垂直柱結構之外圍上
形成-第二閘極介電區域於該第十二應變區域之外 上方;以及 形成-第二閘極導電區域於該第二閘極介電區域之外圍上 57·如申請專利範圍第56項所述之方法,更包含: 形成一第一毯覆介電層於該第一垂直柱結構上方; 形成-第-導電區域穿過該第—毯覆介電層,接觸該第一鬆 弛Sii_jGej蟲晶區域, 形成-第二導電區域穿過該第—毯覆介電層,接觸該第一垂 43 ί υ. 年月曰修(€)正替換頁 QS-14595Q -——>— 1302740 J 直柱結構頂巧該第五鬆㈣咖區域;97年9月1日誠—替顚 過該第-毯覆介電層’接觸該第-垂 :m覆介電層於該第二垂直柱結構上方; 型石夕2 電區域穿過該第二毯覆介電層,接觸該第七P 直二===覆介電層,接觸該第二垂 直柱六導電區域穿過該第二毯覆介電層,接觸該第二垂 直柱、、,°構外社之該第H極導電區域;以及 一 第三介電區域於該第—單晶基板上、介於該第-與第 一垂直柱結構間,以作為元件隔離。 如申請專利範圍第56項所述之方法’其中經由導電材料,該 電區軸合至韻—導電區域,該第六導電區馳合至該 弟二¥電區域’該第五導電區域麵合至該第二導電區域。 59. 如申請專利範圍帛56項所述之方法,其中該第一垂直柱結構 之侧壁係於平面(100)中,且垂直於該第一單晶基板平面。 60. 如申請專利範圍第56項所述之方法,其中該第二垂直柱結構 之側壁係於平面(110)中,且垂直於該第一單晶基板平面。 61· —種場效電晶體,包含: 一基板, 一弟一單晶石夕區域於該基板上,該第一單晶石夕區域具有一大 44
1302740 案號:9ai 15950 认店7 , 97年9月1曰修正-替換頁 於1x10原子/立方公分的p型濃度水平; 一第—兔摻雜遙晶區域於該第—單晶魏域上方,該第二碳 乡雜^晶區域具有一大於㈣19原子/立方公分的p型濃度水平; -第三㈣域於該第二碳摻雜晶區域上方,該第三 被摻雜為η型; ^ ^苐四壓縮應Ί Sil-w-qGewCq遙晶區域於該第三石夕區域上方, “第四壓縮應、憂Sii wqGewCqU區域具有—大於1谓19原子/立 方公分的P型濃度水平; 五含魏域於該第四壓縮應變SWqG〜Cqi晶區域上 ’該第五含魏域具有—大於⑽、子/立方公分的p型濃度 水平; 山一垂直柱結構,包含至少一侧壁自該第一單晶矽區域、第二 ,摻雜蠢晶區域、第三雜域、第四_顧Si—Gewcq蟲晶區 或’延伸至該第五含矽區域; 第/、壓縮應變Si^Ges區域於該垂直柱結構之該至少一侧壁 之區域上方,自該第二碳摻雜磊晶區域延伸過該第三矽區域上 方、至該第四壓縮應變Sil_w_qGewCq磊晶區域; 一閘極介電區域於該第六壓縮應變Sii sGes區域上方;以及 一閘極導電區域於該閘極介電區域上方。 62.如申請專利範圍第61項所述之場效電晶體,更包含·· 一毯覆介電層於該垂直柱結構上方; 、一第一導電介層穿過該毯覆介電層,接觸該第一單晶矽區 域; 二第二導電介層穿毯覆介電層,接_餘柱結構頂上 之該第五含矽區域;以及 45 1302740 日修⑽正替換頁 案號:〖aai1505Q- 一第:道、 97年9月1日修正一替換頁 二^電介層穿過該毯覆介電層,接觸該閘極導電區域 6區3域ttt利範圍第61項所述之場_體,其中該第五含石夕 :伐知壓縮應變swqGewCq蟲晶區域之上表面為鬆弛 64· 早曰曰矽、多晶矽和多晶矽鍺所組成之群組。 第61項㈣之财編,射該垂直柱結 構之摘壁胁日日日體平面⑽)中,且與該基板之—主表面垂直。 61項所述之場效電晶體,其巾於該垂直柱 、、’口構之該侧壁上的該第六魏 石夕區域係壓縮應變的。 We;域相對於糾一單晶 專利_61項所述之場效電晶體,其中該閘極介電 严域氧化物’氮化物’石夕之氧氮化物,與班、=電 UY、孔之氧化物及石夕酸鹽的單獨或組合所組成之群組。、 圍第61項所述之場效電晶體,其中該閘極導電 組成之群組。 科的多㈣和摻雜的多晶石夕鍺 69.如申請專利範圍第61項所述之場心日雕 雜蟲晶區域被摻雜為p型,範圍為119:日日脰、中該第二碳摻 至1x10原子/立方公分。 46 1302740 Γ I 正替換頁 案聽今31十5956~———一一 97年9月1日修正-替換頁 70·如申請專利範圍第61項所述之場效電晶體,其中該第五含矽 區域被摻雜為P型,範圍為lxlO19至lxlO21原子/立方公分。 71·如申請專利範圍第61項所述之場效電晶體,其中該第六壓縮 應變SikGes區域於該第一單晶矽區域、第二碳摻雜磊晶區域、第 四壓縮應變Si^qGewCq蠢晶區域和第五含矽區域旁的區域被摻雜 為p型,而於該第三矽區域被摻雜為n型。 72·如申請專利範圍第61項所述之場效電晶體,更-包含一第七矽 區域於該第六壓縮應變SiuGes區域上方、且於該閘極介電區域下 方。 73.如中請專利範圍第72項所述之場效電晶體,其中該第六厭給
交ii-w-qGewCq蠢晶區域和第五含石夕區域 而於該第三矽區域被摻雜為n型。
縮應變Si^y 縮應變 型濃度水平。 74項所述之場效電晶體 SlkyGexCy磊晶區坺之 y如申請專利範圍第74 3或相_該第八壓縮應變Si .¾日日體,其中該第三石夕區 區域之上表面為鬆弛的。 47 1302740 i) L ye U1 年月日修(楚)正替換頁 案 §4丨-93116060 97年9月1曰修正一替換頁 76·如申請專利範圍第74項所述之場效電晶體,其中該第六壓縮 應變Sii_sGes區域於該第一單晶石夕區域、第八壓縮應變sii x_yGexCy 磊晶區域、第四壓縮應變Sii-w-qGewCq磊晶區域和第五含石夕區域旁 的區域被摻雜為p型,而於該第三矽區域被摻雜為η型。 77· —種反相器,包含: 一第一石夕磊晶區域於一第一單晶基板上,該第一石夕磊晶區域 具有一大於1χ1〇19原子/立方公分的η型濃度水平; 一第二Sii-HGeiCj磊晶區域於該第一矽磊晶區域上方; 一第二石夕磊晶區域於該第二Si㈤GeiCj磊晶區域上方,該第三 砍蠢晶區域被換雜為p型; 弟四應變Si1-yCy蠢晶區域於該第三石夕蟲晶區域上方,該第 四應變Sl^yCy磊晶區域具有一大於1χ1〇19原子/立方公分的n型濃 度水平; 彳 / 1五區域於該第四應冑Sil_ycy蟲晶區域上方,該第五區域 係選自單祕、多晶补多晶铺所域之群組,該第五區域具 有大於1χ1〇原子/立方公分的η型濃度水平; ,ΓΪ一垂直柱結構,包含至少—側壁自該第—雜晶區域延 伸過该第二SlwGedSa區域、該第三綠晶區域、該第四應變 Sii-yCy蟲晶區域上方,至該第五區域; 、芰 •-第六雜域於該第—垂直柱結構之該至少—側壁之一 上方; % 一第一閘極介電區域於該第六矽區域上方; 一,一閘極導電區域於該第一閘極介電區域上方; =七P型料晶區域於該第—單晶基板上,該 蟲晶區域具有—大於_19原子/立方公分的濃度水平; 夕 48 :11 :11 1302740 ΙΗ I r n 曰修 案號灼儿兔 97年9月1日修正〜替〜〜〜 一第八碳摻雜磊晶區域於該第七p型矽磊晶區域上方,該第 八碳摻雜I晶區域具有-大於lxlG19原子/立方公分的p型濃^水 平; -第九綠晶區域於該第人碳摻雜蟲晶區域上方,該第 遙晶區域被摻雜為η型; -第十壓縮應變SWqGewCq磊晶區域於該第九矽磊晶區域上 方,該第十壓縮應變SWqGewCq遙晶區域具有一纽ω /立方公分的p型濃度水平; 、 第十-區域於該第十壓縮應tsWqGewC@晶區域上方, 2十區域係選自單晶石夕、多晶石夕和多晶石夕鍺所組成之群組, 该第—區域具有-大於W9原子/立方公分的p型濃度水平; -第二垂直柱結構’包含至少一侧壁自該第七P型石夕蟲晶區 =、第八碳摻雜蟲晶區域、第九#晶區域、第十壓縮應變 ll-w-qGewCq蟲晶區域延伸至該第十一區域; 一第十二應變sil-SGes區域於該第二垂直柱 該 壁之一區域上方; 一f二閘極介電區域於該第十二應變Si·七域上方; 以及 -第二閘極導魏域於該第二閘極介魏域上方。 .如申μ專利範圍第77項所述之反相II,更包含: 厂第-導電介層穿第—毯覆介電層,翻該第一砍蠢 第-毯覆介電層於該第一垂直柱結構上方; 晶 區域; -第二導較層扣—毯覆介電層 結構頂上之該第五區域; -第三導電介層穿顧第—毯覆介電層,接觸該第—間極導 49 1302740 月日修(動正替換頁 電區域; 案號1 咖〇 —一· 97年9月1日修正一替換頁 一第二毯覆介電層於該第二垂直柱結構上方; 否晶=轉電介料過該第二毯覆介電層,接峨第七Ρ财 '嶋SC二毯覆介電層’接觸該第二垂餘 接觸該第二閘極導 一第六導電介層穿過該第二毯覆介電層, 電區域;以及 直柱單晶基板上、介於該第-與第二垂 79. 3之範圍第77項所述之反相器,其中該第一垂直柱結 冓之側土係於平面_)中’且垂直於該第—單晶基板之—主表面。 - 如申請專利範圍第77項所述之反相器’其中該第二垂士 構之側壁係於平面⑽)中,且垂直於該第一單晶基板之一主表^ · 82.如申請專利範圍第77項所述之反相器,其中該第十二應變 Sii-sGes區域係一石夕區域。 83· —種反相器,包含: 第鬆弛晶區域於一第一單晶基板上,該第一鬆 50 1302740 ui $月曰修(€1正替換頁 案號:^3115950 弛_轉晶區域被摻雜為n型,至—大^正古 的濃度水平; 人於1χΐ0原子/立方公分 方,變綠晶區域於該第—鬆弛队純晶區域上 原子/立 ===區_雜為η型,至一大於㈣19 方,晶區域於該第二拉伸應變綠晶區域上 μ,一#々弛SiuGei磊晶區域被摻雜為p型; 方,該ί變石夕蠢晶區域於該第三鬆他sii-iGej晶區域上 原子/立方公分申的^^晶區域被換雜為η型’至一大於1谓19 一第五區域於該第四拉伸應變矽磊晶區域 曰F R第-垂直柱結構,包含至少—側壁自該第—鬆弛蠢 ΐ :二延^該$二拉伸應變石夕蟲晶區域、該第三鬆弛Si也 曰曰亥苐四拉伸應變石夕蟲晶區域上方,至該第五區域; 第六應變㈣域於該第—垂直柱結構之該至少—側 區域上方; 一,一閘極介電區域於該第六應變矽區域上方;以及 弟閘極導電區域於該第一閘極介電區域上方; 石曰第七p型矽磊晶區域於該第一單晶基板上,該第七p型矽 猫晶區,具有—大於㈣19軒/立方公分的濃度水平; 山△第八奴#雜磊晶區域於該第七p型矽磊晶區域上方,該第 八,摻雜磊晶區域被摻雜為?型,至一大於lxlol9原子/立方公分 的濃度水平; 51 1302740 案號:93U5950 … 97年9月1曰修正-替換頁 -第九石綠晶區域於該第人碳摻雜蟲晶區域上方,該第九石夕 蟲晶區域被摻雜為η型; -第十壓騎變Si^qGewCq遙晶區域於鮮九縣晶區域上 方,該第十獅應變Si—G^Cq蟲晶區域具有—大於1χ1〇ΐ9原子 /立方公分的Ρ型濃度水平; -第十-區域於該第十壓縮應變silwqGewc^晶區域上方, =十區域係選自單晶石夕、多晶石夕和多晶石夕鍺所組成之群組, ^二:區域具有一大於1x1019原子/立方公分的ρ型濃度水平; 竹1 ^直柱結構,包含至少—侧壁自該第·P _蟲晶區 r ί八;炭ff編域·、第九石夕蟲晶區域、第十屢縮應變 l-W-qGewCq磊晶區域延伸,至該第十一區域; 壁之:域於該,二垂直柱結構之該至少-側 二^_介電區域於該第十二應變silsGes區域上方;以及 4-閘極導電區域於該第二閘極介電區域上方。 84·=請專利範圍第83項所述之反相器·,更包含: 二第一毯覆介電層於該第—垂直柱結構上方; 第一導電介層穿過該第—毯覆介電芦 結構頂上之該第五區域;m層接觸料-垂直柱 電區域弟—W介層穿過該第—毯覆介電層,接觸該第1極導 二,二毯覆介電層於該第—垂直柱結構上方; —第四導電介層穿職第二毯覆介,翻該第切蟲曰 52 1302740
年月日修(吏)正替換頁 一第五導電介層穿過該第二毯覆介電層 ’接觸該第一垂直柱 €十二應變SiUsGe^ 一 1 -----—%设厂,招 w構頂上之該弟十一區域上方之區域中的該 域; 帛4電介層穿伽第二毯覆介電層,接_第二問 電區域;以及 -第三介賴域於該第—單晶基板上、介於該第-與第二垂 直柱結構間,以提供元件隔離。 如申睛專利範圍第84項所述之反相器,其中經由導電材料, 該第四導電介層#合至該第—導較層,該第六導電介層輛合至 該第三導電介層,該第五導電介層耦合至該第二導電介層。 86·如申請專利範圍第83項所述之反相器,其中該第一垂直柱結 構之側壁係於平面(1〇〇)中,且垂直於該第一單晶基板之一主表面。 87·如申請專利範圍第83項所述之反相器,其中該第二垂直柱結 構之側壁係於平面(110)中,且垂直於該第一單晶基板之一主表面。 88·如申請專利範圍第83項所述之反相器,其中該第十二應變 Sii_sGes區域係一砍區域。 53 1302740 ΎηΤΨΓ ^ ~ J 年月曰修{的正替換頁丨 6000 168 171
162 161 ~ργ C回Ο 1302740 W 巧~qY*" 年·启日修(更)正替換頁 6000 168 171
162 161
6 1302740 6000 168 171
161 回
1302740 dZ f>. 2B 年^ Ώ修(更)正替換頁 棄號:03115050-- 97年5月28日修正-替換頁 · 七、指定代表圖: (一) 本案指定代表圖為:圖5。 (二) 本代表圖之元件符號簡單說明: 104箭頭 160垂直元件 161單晶基板 162汲極 163體極 164源極 165通道 166絕緣層或區域 167閘極 168毯覆介電層 169汲極電極 170源極電極 171閘極電極 _ 210碳掺雜磊晶層或區域 410鬆弛矽層或區域、多晶矽層或區域、或多晶矽鍺層或區域 570介面 5000, 6000垂直柱結構 八、本案若有化學式時,請揭示最能顯示發坷特徵的化學式: 無0
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-
2003
- 2003-06-17 US US10/463,039 patent/US6943407B2/en not_active Expired - Fee Related
-
2004
- 2004-06-03 TW TW093115950A patent/TWI302740B/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
CN1574253A (zh) | 2005-02-02 |
US6943407B2 (en) | 2005-09-13 |
US20040256639A1 (en) | 2004-12-23 |
TW200512930A (en) | 2005-04-01 |
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