JP5477291B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5477291B2 JP5477291B2 JP2010521698A JP2010521698A JP5477291B2 JP 5477291 B2 JP5477291 B2 JP 5477291B2 JP 2010521698 A JP2010521698 A JP 2010521698A JP 2010521698 A JP2010521698 A JP 2010521698A JP 5477291 B2 JP5477291 B2 JP 5477291B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- plane
- channel
- semiconductor device
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 214
- 239000000758 substrate Substances 0.000 claims description 66
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 23
- 239000012535 impurity Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
11 ゲート電極
12 半導体突出部
13 チャネル面
14a ソース電極
14b ドレイン電極
115 Pウェル
125 Nウェル
130 素子分離領域
131 絶縁膜
132 層間絶縁膜
133a、133b、133c コンタクトプラグ
Claims (11)
- 基板の主面に対して平行で一定方向に延在するゲート電極と、
両端のうち一方の端部にソース電極が設けられ、前記両端のうち他方の端部にドレイン電極が設けられ、前記ゲート電極を貫通し、ゲート絶縁膜を介して前記ゲート電極と接する第1および第2の半導体突出部と、を有し、
前記第1および第2の半導体突出部は前記一定方向に沿って配列され、
前記第1の半導体突出部は、前記ゲート絶縁膜に接する、チャネルが発生する面であるチャネル面を複数備えた四角柱が前記一定方向に複数連接された形状であり、
前記第2の半導体突出部は、前記ゲート絶縁膜に接する前記チャネル面を複数備えた直方体の形状であり、
前記第1の半導体突出部の複数の前記四角柱のそれぞれは、複数の前記チャネル面の全ての向きが前記一定方向に対して斜めである、半導体装置。 - 前記第1の半導体突出部の複数の前記四角柱のそれぞれは、前記主面に平行な断面形状が正方形であり、
前記第2の半導体突出部の前記直方体は前記主面に平行な断面形状が長方形であり、該長方形の長辺が前記一定方向に平行である、請求項1記載の半導体装置。 - 前記第1の半導体突出部の複数の前記四角柱のそれぞれは、前記主面に平行な断面形状が長方形であり、
前記第2の半導体突出部の前記直方体は前記主面に平行な断面形状が長方形であり、該長方形の長辺が前記一定方向に平行である、請求項1記載の半導体装置。 - 前記第1および第2の半導体突出部は前記基板の厚さ方向に対し同一階層レベルに形成されている、請求項1から3のいずれか1項に記載の半導体装置。
- 前記ゲート電極および前記第1の半導体突出部を有する第1のトランジスタと、前記ゲート電極および前記第2の半導体突出部を有する第2のトランジスタとが設けられた請求項1から4のいずれか1項に記載の半導体装置。
- 前記第1および第2のトランジスタのそれぞれのチャネル面の面方位が互いに異なっている、請求項5記載の半導体装置。
- 前記第1のトランジスタは面方位が(100)面であるチャネル面を有し、前記第2のトランジスタは面方位が(110)面であるチャネル面を有する、請求項6記載の半導体装置。
- 前記第1のトランジスタがNチャネル素子であり、前記第2のトランジスタがPチャネル素子である、請求項7記載の半導体装置。
- 前記第1の半導体突出部の複数の前記四角柱のそれぞれにおいて、複数の前記チャネル面のうち少なくとも1つのチャネル面と前記一定方向とのなす角度が45°である請求項1から8のいずれか1項に記載の半導体装置。
- 前記主面の面方位が(100)面である半導体基板上に形成されている、請求項1から9のいずれか1項に記載の半導体装置。
- 前記主面の面方位が(110)面である半導体基板上に形成されている、請求項1から9のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010521698A JP5477291B2 (ja) | 2008-07-22 | 2009-07-21 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008188503 | 2008-07-22 | ||
JP2008188503 | 2008-07-22 | ||
PCT/JP2009/063042 WO2010010865A1 (ja) | 2008-07-22 | 2009-07-21 | 半導体装置 |
JP2010521698A JP5477291B2 (ja) | 2008-07-22 | 2009-07-21 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2010010865A1 JPWO2010010865A1 (ja) | 2012-01-05 |
JP5477291B2 true JP5477291B2 (ja) | 2014-04-23 |
Family
ID=41570325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010521698A Expired - Fee Related JP5477291B2 (ja) | 2008-07-22 | 2009-07-21 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP5477291B2 (ja) |
WO (1) | WO2010010865A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6178118B2 (ja) * | 2013-05-31 | 2017-08-09 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TWI689920B (zh) | 2014-01-08 | 2020-04-01 | 日商新力股份有限公司 | 半導體裝置及記憶體電路 |
US20240096964A1 (en) * | 2022-09-20 | 2024-03-21 | Qualcomm Incorporated | Vertical channel field effect transistor (vcfet) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03145761A (ja) * | 1989-11-01 | 1991-06-20 | Toshiba Corp | 半導体装置 |
JPH0799311A (ja) * | 1993-05-12 | 1995-04-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08227997A (ja) * | 1995-02-20 | 1996-09-03 | Hitachi Ltd | 半導体装置とその製造方法 |
JPH08250679A (ja) * | 1996-01-04 | 1996-09-27 | Tadamichi Masamoto | 電子素子又は電子装置。 |
JP2003086714A (ja) * | 2001-06-23 | 2003-03-20 | Fujio Masuoka | 半導体記憶装置及びその製造方法 |
US20030102518A1 (en) * | 2001-12-04 | 2003-06-05 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
JP2005012213A (ja) * | 2003-06-17 | 2005-01-13 | Internatl Business Mach Corp <Ibm> | 低漏洩ヘテロ接合垂直トランジスタおよびその高性能デバイス |
-
2009
- 2009-07-21 JP JP2010521698A patent/JP5477291B2/ja not_active Expired - Fee Related
- 2009-07-21 WO PCT/JP2009/063042 patent/WO2010010865A1/ja active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03145761A (ja) * | 1989-11-01 | 1991-06-20 | Toshiba Corp | 半導体装置 |
JPH0799311A (ja) * | 1993-05-12 | 1995-04-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08227997A (ja) * | 1995-02-20 | 1996-09-03 | Hitachi Ltd | 半導体装置とその製造方法 |
JPH08250679A (ja) * | 1996-01-04 | 1996-09-27 | Tadamichi Masamoto | 電子素子又は電子装置。 |
JP2003086714A (ja) * | 2001-06-23 | 2003-03-20 | Fujio Masuoka | 半導体記憶装置及びその製造方法 |
US20030102518A1 (en) * | 2001-12-04 | 2003-06-05 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
JP2005012213A (ja) * | 2003-06-17 | 2005-01-13 | Internatl Business Mach Corp <Ibm> | 低漏洩ヘテロ接合垂直トランジスタおよびその高性能デバイス |
Also Published As
Publication number | Publication date |
---|---|
JPWO2010010865A1 (ja) | 2012-01-05 |
WO2010010865A1 (ja) | 2010-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4417601B2 (ja) | 半導体装置及びその形成方法 | |
CN102237359B (zh) | 半导体器件 | |
KR100763330B1 (ko) | 활성 핀들을 정의하는 소자분리 방법, 이를 이용하는반도체소자의 제조방법 및 이에 의해 제조된 반도체소자 | |
JP5086797B2 (ja) | 半導体装置 | |
JP5703790B2 (ja) | 半導体装置及びその製造方法 | |
US20070045736A1 (en) | FinFET and method for manufacturing the same | |
JP4783050B2 (ja) | 半導体装置及びその製造方法 | |
CN113327910B (zh) | 用于栅极绑定关断的新颖标准单元架构 | |
US20060006466A1 (en) | Semiconductor device and method of manufacturing the same | |
WO2005091374A1 (ja) | 半導体装置及びその製造方法 | |
CN101740568A (zh) | 集成电路 | |
TWI701763B (zh) | 電晶體結構和半導體佈局結構 | |
JP2007123784A (ja) | 半導体装置 | |
JP2011204745A (ja) | 半導体装置及びその製造方法 | |
JP2007053316A (ja) | Esd保護素子 | |
US7511342B2 (en) | Semiconductor device having SOI structure and method for manufacturing the same | |
JP2005136150A (ja) | 半導体装置及びその製造方法 | |
JP5477291B2 (ja) | 半導体装置 | |
JP3713020B2 (ja) | 半導体装置及びその製造方法 | |
JP2000124450A5 (ja) | ||
KR100673144B1 (ko) | 반도체소자의 트랜지스터 및 그 형성방법 | |
KR101576203B1 (ko) | 최적화된 채널 영역을 갖는 모스 트랜지스터들을 구비하는 반도체 소자들 및 그 제조방법들 | |
KR101404941B1 (ko) | 반도체 장치와 그 제조 방법 | |
US20160027778A1 (en) | Semiconductor device | |
JP2004207457A (ja) | 半導体装置及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120514 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131008 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131205 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140114 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140127 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5477291 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |