TWI244724B - Method for manufacturing device isolation film of semiconductor device - Google Patents

Method for manufacturing device isolation film of semiconductor device Download PDF

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TWI244724B
TWI244724B TW093137690A TW93137690A TWI244724B TW I244724 B TWI244724 B TW I244724B TW 093137690 A TW093137690 A TW 093137690A TW 93137690 A TW93137690 A TW 93137690A TW I244724 B TWI244724 B TW I244724B
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film
oxide film
nitride film
liner
region
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TW093137690A
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TW200603334A (en
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Sang-Don Lee
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Description

1244724 九、發明說明： 【發明所屬之技術領域】 本發明一般係關於一種製造半導體裝置之裝置隔離膜之 方法，更明確言之，係關於一種如下製造半導體裝置之裝 置絕緣膜之方法，即其中在形成裝置隔離膜之前，使用電 漿氧化藉由蝕刻周邊區域的内襯氧化膜而曝露的内襯氮化 膜，以防止HEIP現象，並改善半導體裝置的特徵。 【先前技術】 圖la至le之斷面圖說明了製造半導體裝置之裝置隔離膜 的傳統方法。 參考圖la，襯墊氧化膜20與襯墊氮化膜30依次形成於半 導體基板10上。半導體基板10包含一單元區域1〇〇〇&與一周 邊區域1000b。 參考圖lb，蝕刻襯墊氮化膜30、襯墊氧化膜2〇以及欲形 成波置隔離膜的半導體基板1〇之一預定區域，以形成溝渠 40 〇 參考圖lc，一側壁氧化膜50沈積於溝渠4〇之表面上。之 後，内襯氮化膜60與内襯氧化膜70依次形成於半導體基板 10的整個表面上。 參考圖1 d，在半導體基板i 〇的整個表面上形成一間隙填 充氧化膜80以填充溝渠4〇。 斤參考圖^，將間隙填充氧化膜80平坦化，直至曝露襯墊 虱化膜30。之後，將襯墊氮化膜30與襯墊氧化膜20移除， 以形成裝置隔離膜9〇。 97925.doc 1244724 依據製造半導體裝置之裝置隔離膜的傳統方法，可因内 襯氮化膜與内襯氧化膜而減少漏電流現象。但是，在其中 會形成pMOS電晶體以捕獲熱電子之pMOS區域内的氮化膜 與氧化膜的介面處會形成電子阱。捕獲的熱電子會導致熱 電子引致的穿透崩潰（Hot electron Induced Punch-through · HEIP)現象。HEIP現象指，即使未向pMOS電晶體之閘極施 加電壓，亦會在通道區域内產生電流之狀態。heip現象會 增加DRAM的靜態電流，導致裝置特徵與良率下降。 為解決該問題，提出了一種增加側壁氧化膜厚度之方 法。然而，隨著側壁氧化膜厚度增加，間隙填充特徵劣化 並且作用區域的寬度減小，從而降低了電流驅動能力及電 晶體的臨界電壓，並使電晶體的更新特徵降級。 【發明内容】 本發明之目的係提供一種製造半導體裝置之裝置隔離層 之方法，其中在形成裝置隔離膜之前，先使用電漿將藉由 移除周邊區域中的内襯氧化膜而曝露之内襯氮化膜氧化， 以防止HEIP現象，從而改善半導體裝置之特徵，例如更新 特徵與電流•驅動能力。 為實現本發明之上述目的，提供了 一種製造半導體裝置 之裝置隔離膜之方法，其包含以下步驟：在半導體基板上 依次形成一襯墊氧化膜與一襯墊氮化膜，其中半導體基板 包含一周邊區域以及一單元區域，其中該周邊區域包括一 PMOS區域以及一nM〇s區域；蝕刻襯墊氮化膜、襯墊氧化 膜以及欲形成裝置隔離膜之半導體基板之一預定區域，以 97925.doc 1244724 形成一溝渠；纟溝渠表面上形成-側壁氧化膜；在包括溝 渠與襯墊氮化膜之半導體基板之表面上依次形成—内概氮 ㈣與-内絲化膜；至少移除周邊區域之nM_pM〇s 區域中PMOSII域部份的内襯氧化膜，以曝露所移除部份之 内，氧化膜下的部份内襯氮化膜；氧化該内襯氮化膜之已 曝:’在半導體基板上形成—間隙填充氧化膜以填充 溝渠；實施平坦化程序以曝露襯墊氮化膜；以及移除概塾 氮化膜與襯墊氧化膜。 【實施方式】 將參考隨附圖式詳細說明本發明。 圖2a至2g之斷面圖說明了依據本發明製造半導體裝置之 裝置隔離膜之方法的第一項具體實施例。 參考圖2a，襯墊氧化膜11〇與襯墊氮化膜12〇依次形成於 半導體基板1〇〇上。半導體基板1〇〇包含一單元區域2〇〇〇&與 一周邊區域2000b。周邊區域2000b亦包括一 pM〇s區域 3 000&與一11]\4〇8區域30001)。 參考圖2b，蝕刻襯墊氮化膜12〇、襯墊氧化膜11〇以及欲 形成裝置隔離膜的半導體基板100之一預定區域，以形成溝 渠 13 0 〇 參考圖2c，側壁氧化膜140沈積於溝渠13〇之表面上。之 後，内襯氮化膜150與内襯氧化膜16〇依次形成於包括溝渠 130及襯墊氮化膜120的半導體基板1〇〇的整個表面上。側壁 氧化膜140之厚度較佳係在20至200 A之範圍内。經由在一 NH3、一N2〇或—N0環境下的熱處理程序，對側壁氧化膜 97925.doc 1244724 140作進一步熱處理。内襯氮化膜160的厚度較佳係在20至 100 A之範圍内，並可經由在一出環境下的熱處理程序作進 一步的熱處理。内襯氧化膜之厚度係在2〇至200 A之範圍内。 參考圖2d，形成一光阻膜（圖中未顯示）以覆蓋單元區域 2000a與周邊區域2〇〇〇b的nMOS區域3000b。之後，使用光 阻膜作為蝕刻遮罩進行蝕刻，將pM〇s區域3000a中部份的 内襯氧化膜160移除，以形成内襯氧化膜圖案165。藉由 pMOS區域3000a中内襯氧化膜160的移除程序來曝露pMOS 區域3000a中的内襯氮化膜15〇。 依據本發明之第二項具體實施例，如圖3 a所示，形成一 光阻膜（圖中未顯示）以僅將單元區域2000a覆蓋，而非覆蓋 單元區域20 00a與周邊區域2〇〇〇b中的nMOS區域3000b。之 後’使用光阻膜作為蝕刻遮罩進行蝕刻，將包括pM〇s區域 3000與nMOS區域3000b的周邊區域2000b中的整個内襯氧 化膜160移除’以曝露周邊區域中的内襯氮化膜15〇。 參考圖2e，氧化内襯氮化膜150之已曝露部份。當依據第 一項具體實施例移除pMOS區域3000a中的内襯氧化膜160 時’僅氧化pMOS區域3000a中的内襯氮化膜150。當依據第 二項具體實施例移除包括pMOS區域3000a及nMOS區域 3000b的周邊區域2000b中的整個内襯氧化膜16〇時，氧化周 邊區域2000b中的整個内襯氮化膜150。較佳地，該内襯氮 化膜1 5 0之已曝露部份之氧化程序包含一使用電漿之氧化 程序。 參考圖2f，在半導體基板1 〇〇的整個表面上形成一間隙填 97925.doc 1244724 充氧化膜170以填充溝渠130。間隙填充氧化膜17〇較佳係高 密度電漿（High Density Plasma ; HDP)氧化膜。圖2e所示2 内襯氮化膜150之氧化程序可與HDP氧化膜之形成程序同 時實施。即，在使用高密度電漿形成HDp氧化膜的程序期 間，可使用高密度電漿來氧化内襯氮化膜15〇之已曝露部 份。 參考圖2g，經由化學機械拋光（Chemical Polishing; CMP)程序實施平坦化程序，以曝露襯墊氮化膜 120。之後，將襯墊氮化膜12〇與襯墊氧化膜11〇移除，以形 成裝置隔離膜180。當依據第二項具體實施例移除周邊區域 2000b中的整個内襯氧化膜16〇時，即可獲得圖扑中所示之 裝置隔離膜180。 如上所述，依據本發明，在形成裝置隔離膜之前，藉由 移除周邊區域中的内襯氧化膜來曝露内襯氮化膜，然後再 使用電聚將其氧化，以減少所產生的電子阱，從而防止HEIp 現象以及HEIP現象導致的半導體裝置劣化。此外，無需增 加側壁氧化膜之厚度便可有效防止heip現象，從而防止電 晶體之驅動電流及臨界電壓下降及裝置之更新特徵退化。 【圖式簡單說明】 圖la至le之斷面圖說明了製造半導體裝置之裝置隔離膜 的傳統方法。 圖2a至2g之斷面圖說明了依據本發明製造半導體裝置之 裝置隔離膜之方法的第一項具體實施例。 圖3a至3b之斷面圖說明了依據本發明之製造半導體裝置 97925.doc 1244724 之裝置隔離膜之方法的第二項具體實施例。 【主要元件符號說明】 10 、 100 20 、 110 30 、 120 40 、 130 50 、 140 60 、 150 70 ^ 160 165 80 、 170 90 1000a 、 2000a 1000b 、 2000b 3000a 3000b 半導體基板 襯墊氧化膜 襯墊氮化膜 溝渠 側壁氧化膜 内襯氮化膜 内襯氧化膜 内襯氧化膜圖案 間隙填充氧化膜 裝置隔離膜 單元區域 周邊區域 pMOS區域 nMOS區域 10- 97925.doc

Claims (1)

1244724 十、申請專利範圍： 1· 一種製造半導體裝置之裝置隔離膜之方法，其包含以下 步驟： 在一半導體基板上依次形成一襯墊氧化膜與一襯墊氮 化膜，其中該半導體基板包含一周邊區域以及一單元區 域’遠周邊區域包括一 pMOS區域及一 nMOS區域； 鍅刻該襯墊氮化膜、該襯墊氧化膜以及欲形成一裝置 隔離膜之該半導體基板之一預定區域，以形成一溝渠； 在該溝渠之一表面上形成一側壁氧化膜； 在包括該溝渠與該襯墊氮化膜的該半導體基板之表面 上依次形成一内襯氮化膜及一内襯氧化膜； 至少移除該周邊區域之該等nMOS與pMOS區域中的該 pMOS區域中的部份内襯氧化膜，以曝露該内襯氧化膜之 移除部份下的部份内襯氮化膜； 氧化該内襯氮化膜之已曝露部份； 在该半導體基板上形成一間隙填充氧化膜，以填充該 溝渠； ' ~ 貫％ —平坦化程序以曝露該襯墊氮化膜；以及 移除該襯墊氮化膜及該襯墊氧化膜。 2_如請求項1之方法，其進一步包含一在_NH3、_N2〇或一 NO環境下對該側壁氧化膜進行熱處理之熱處理程序。 3·如請求们之方法’其進一步包含一在—H2環境下對該内 襯氮化膜進行熱處理之熱處理程序。 4.如請求項丨之方法，移除該内襯氧化膜之部份之步驟包 97925.doc Ϊ244724 含·· 形成光阻膜以覆蓋該單元區域與該nM〇S區域；以及 使用4光阻膜作為一蝕刻遮罩來蝕刻該pM〇s區域中 的該内襯氧化膜。 如請求頂1夕女^ 、 万法’私除該内襯氧化膜之部份之步驟包 含： · 6. 9. 开y成一光阻膜以覆蓋該單元區域；以及 、使用该光阻膜作為一蝕刻遮罩來蝕刻包括該nM〇S區 域與4 PMOS區域之周邊區域中的該内襯氧化膜。 士明求項1之方法’其中氧化該内襯氮化膜之已曝露部份 之步驟包含一使用電漿之氧化程序。 如明求項1之方法，其中該側壁氧化膜之厚度在20至200 A 之範圍内。 如明求項1之方法，其中該内襯氮化膜之厚度在20至1〇〇 A 之範圍内。 如味求項1之方法，其中該内襯氧化膜之厚度在20至200 A 之範圍内。 •如巧求項1之方法，其中該平坦化程序包含一 CMP程序。 •如巧求項1之方法，其中氧化該内襯氮化膜之已曝露部份 之步驟係與一使用電漿之HDP氧化膜以形成該間隙填充 氧化膜同時實施。 97925.doc
TW093137690A 2004-07-13 2004-12-07 Method for manufacturing device isolation film of semiconductor device TWI244724B (en)

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US20060024912A1 (en) 2006-02-02

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