CN1722403A - 制造半导体器件的器件隔离膜的方法 - Google Patents

制造半导体器件的器件隔离膜的方法 Download PDF

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CN1722403A
CN1722403A CNA2004101037175A CN200410103717A CN1722403A CN 1722403 A CN1722403 A CN 1722403A CN A2004101037175 A CNA2004101037175 A CN A2004101037175A CN 200410103717 A CN200410103717 A CN 200410103717A CN 1722403 A CN1722403 A CN 1722403A
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李相敦
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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Abstract

本发明揭示一种制造半导体器件的器件隔离膜的方法。本发明在形成器件隔离膜之前，对藉由蚀刻周边区域中的一内衬氧化膜而暴露的一内衬氮化膜进行等离子氧化，以防止产生一电子阱(electron trap)，其会导致该氧化膜与该氮化膜的接口处发生电子捕获，从而导致一HEIP现象。

Description

制造半导体器件的器件隔离膜的方法
技术领域
本发明总体上涉及一种制造半导体器件的器件隔离膜的方法，更具体地是涉及一种如下制造半导体器件的器件绝缘膜的方法，即其中在形成器件隔离膜之前，使用等离子氧化藉由蚀刻周边区域的内衬氧化膜而曝露的内衬氮化膜，以防止HEIP现象，并改善半导体器件的特征。
背景技术
图1A至1E的断面图说明了制造半导体器件的器件隔离膜的传统方法。
参考图1A，衬垫氧化膜20与衬垫氮化膜30依次形成于半导体基板10上。半导体基板10包括一单元区域1000a与一周边区域1000b。
参考图1B，蚀刻衬垫氮化膜30、衬垫氧化膜20以及半导体基板10的欲形成器件隔离膜的一预定区域，以形成沟槽40。
参考图1C，一侧壁氧化膜50沉积于沟槽40的表面上。之后，内衬氮化膜60与内衬氧化膜70依次形成于半导体基板10的整个表面上。
参考图1D，在半导体基板10的整个表面上形成一间隙填充氧化膜80以填充沟槽40。
参考图1E，将间隙填充氧化膜80平坦化，直至曝露衬垫氮化膜30。之后，将衬垫氮化膜30与衬垫氧化膜20移除，以形成器件隔离膜90。
依据制造半导体器件的器件隔离膜的传统方法，可因内衬氮化膜与内衬氧化膜而减少漏电流现象。但是，在其中会形成pMOS晶体管以捕获热电子的pMOS区域内的氮化膜与氧化膜的接口处会形成电子阱。捕获的热电子会导致热电子引致的穿透崩溃(Hot electron Induced Punch-through；HEIP)现象。HEIP现象指，即使未向pMOS晶体管的栅极施加电压，亦会在信道区域内产生电流的状态。HEIP现象会增加DRAM的静态电流，导致器件特征与良率下降。
为解决该问题，提出了一种增加侧壁氧化膜厚度的方法。然而，随着侧壁氧化膜厚度增加，间隙填充特征劣化并且作用区域的宽度减小，从而降低了电流驱动能力及晶体管的临界电压，并使晶体管的更新特征降级。
发明内容
本发明的目的是提供一种制造半导体器件的器件隔离层的方法，其中在形成器件隔离膜之前，先使用等离子将藉由移除周边区域中的内衬氧化膜而曝露的内衬氮化膜氧化，以防止HEIP现象，从而改善半导体器件的特征，例如更新特征与电流驱动能力。
为实现本发明的上述目的，提供了一种制造半导体器件的器件隔离膜的方法，其包括以下步骤：在半导体基板上依次形成一衬垫氧化膜与一衬垫氮化膜，其中半导体基板包括一周边区域以及一单元区域，其中该周边区域包括一pMOS区域以及一nMOS区域；蚀刻衬垫氮化膜、衬垫氧化膜以及欲形成器件隔离膜的半导体基板的一预定区域，以形成一沟槽；在沟槽表面上形成一侧壁氧化膜；在包括沟槽与衬垫氮化膜的半导体基板的表面上依次形成一内衬氮化膜与一内衬氧化膜；至少移除周边区域的nMOS与pMOS区域中pMOS区域部分的内衬氧化膜，以曝露所移除部分的内衬氧化膜下的部分内衬氮化膜；氧化该内衬氮化膜的已曝露部分；在半导体基板上形成一间隙填充氧化膜以填充沟槽；实施平坦化工序以曝露衬垫氮化膜；以及移除衬垫氮化膜与衬垫氧化膜。
附图说明
图1A至1E的断面图说明了制造半导体器件的器件隔离膜的传统方法。
图2A至2G的断面图说明了依据本发明制造半导体器件的器件隔离膜的方法的第一具体实施例。
图3A至3B的断面图说明了依据本发明的制造半导体器件的器件隔离膜的方法的第二具体实施例。
主要组件符号说明
10、100：半导体基板
20、110：衬垫氧化膜
30、120：衬垫氮化膜
40、130：沟槽
50、140：侧壁氧化膜
60、150：内衬氮化膜
70、160：内衬氧化膜
165：内衬氧化膜图案
80、170：间隙填充氧化膜
90：器件隔离膜
1000a、2000a：单元区域
1000b、2000b：周边区域
3000a：pMOS区域
3000b：nMOS区域
具体实施方式
下面将参考附图详细说明本发明。
图2A至2G的断面图说明了依据本发明制造半导体器件的器件隔离膜的方法的第一具体实施例。
参考图2A，衬垫氧化膜110与衬垫氮化膜120依次形成于半导体基板100上。半导体基板100包括一单元区域2000a与一周边区域2000b。周边区域2000b亦包括一pMOS区域3000a与一nMOS区域3000b。
参考图2B，蚀刻衬垫氮化膜120、衬垫氧化膜110以及半导体基板100的欲形成器件隔离膜的一预定区域，以形成沟槽130。
参考图2C，一侧壁氧化膜140沉积于沟槽130的表面上。之后，内衬氮化膜150与内衬氧化膜160依次形成于包括沟槽130及衬垫氮化膜120的半导体基板100的整个表面上。侧壁氧化膜140的厚度优选系在20至200的范围内。经由在NH3、N2O或NO环境下的热处理工序，对侧壁氧化膜140作进一步热处理。内衬氮化膜160的厚度优选系在20至100的范围内，并可经由在H2环境下的热处理工序作进一步的热处理。内衬氧化膜的厚度在20至200的范围内。
参考图2D，形成一光阻膜(图中未显示)以覆盖单元区域2000a与周边区域2000b的nMOS区域3000b。之后，使用光阻膜作为蚀刻掩模进行蚀刻，将pMOS区域3000a中部分的内衬氧化膜160移除，以形成内衬氧化膜图案165。藉由pMOS区域3000a中内衬氧化膜160的移除工序来曝露pMOS区域3000a中的内衬氮化膜150。
依据本发明的第二具体实施例，如图3A所示，形成一光阻膜(图中未显示)以仅将单元区域2000a覆盖，而不覆盖单元区域2000a与周边区域2000b中的nMOS区域3000b。之后，使用光阻膜作为蚀刻掩模进行蚀刻，将包括pMOS区域3000与nMOS区域3000b的周边区域2000b中的整个内衬氧化膜160移除，以曝露周边区域中的内衬氮化膜150。
参考图2E，氧化内衬氮化膜150的已曝露部分。当依据第一项具体实施例移除pMOS区域3000a中的内衬氧化膜160时，仅氧化pMOS区域3000a中的内衬氮化膜150。当依据第二项具体实施例移除包括pMOS区域3000a及nMOS区域3000b的周边区域2000b中的整个内衬氧化膜160时，氧化周边区域2000b中的整个内衬氮化膜150。优选地，该内衬氮化膜150的已曝露部分的氧化工序包括一使用等离子的氧化工序。
参考图2F，在半导体基板100的整个表面上形成一间隙填充氧化膜170以填充沟槽130。间隙填充氧化膜170优选系高密度等离子(High DensityPlasma；HDP)氧化膜。图2E所示的内衬氮化膜150的氧化工序可与HDP氧化膜的形成工序同时实施。即，在使用高密度等离子形成HDP氧化膜的工序期间，可使用高密度等离子来氧化内衬氮化膜150的已曝露部分。
参考图2G，经由化学机械抛光(Chemical Mechanical Polishing；CMP)工序实施平坦化工序，以曝露衬垫氮化膜120。之后，将衬垫氮化膜120与衬垫氧化膜110移除，以形成器件隔离膜180。当依据第二具体实施例移除周边区域2000b中的整个内衬氧化膜160时，即可获得图3B中所示的器件隔离膜180。
如上所述，依据本发明，在形成器件隔离膜之前，藉由移除周边区域中的内衬氧化膜来曝露内衬氮化膜，然后再使用等离子将其氧化，以减少所产生的电子阱，从而防止HEIP现象以及HEIP现象导致的半导体器件劣化。此外，无需增加侧壁氧化膜的厚度便可有效防止HEIP现象，从而防止晶体管的驱动电流及临界电压下降及器件的更新特征退化。

Claims (11)

1.一种制造半导体器件的器件隔离膜的方法，包括以下步骤：
在一半导体基板上依次形成一衬垫氧化膜与一衬垫氮化膜，其中该半导体基板包括一周边区域以及一单元区域，该周边区域包括一pMOS区域及一nMOS区域；
蚀刻该衬垫氮化膜、该衬垫氧化膜以及该半导体基板的欲形成一器件隔离膜的预定区域，以形成一沟槽；
在该沟槽的一表面上形成一侧壁氧化膜；
在包括该沟槽与该衬垫氮化膜的该半导体基板的表面上依次形成一内衬氮化膜及一内衬氧化膜；
至少移除该周边区域的该nMOS与pMOS区域中的该pMOS区域中的部分内衬氧化膜，以曝露该内衬氧化膜的移除部分下的部分内衬氮化膜；
氧化该内衬氮化膜的已曝露部分；
在该半导体基板上形成一间隙填充氧化膜，以填充该沟槽；
实施一平坦化工序以曝露该衬垫氮化膜；以及
移除该衬垫氮化膜及该衬垫氧化膜。
2.如权利要求1所述的方法，其进一步包括在NH3、N2O或NO环境下对该侧壁氧化膜进行热处理的热处理工序。
3.如权利要求1所述的方法，其进一步包括在H2环境下对该内衬氮化膜进行热处理的热处理工序。
4.如权利要求1所述的方法，移除该内衬氧化膜的部分的步骤包括：
形成一光阻膜以覆盖该单元区域与该nMOS区域；以及
使用该光阻膜作为一蚀刻掩模来蚀刻该pMOS区域中的该内衬氧化膜。
5.如权利要求1所述的方法，移除该内衬氧化膜的部分的步骤包括：
形成一光阻膜以覆盖该单元区域；以及
使用该光阻膜作为一蚀刻掩模来蚀刻包括该nMOS区域与该pMOS区域的周边区域中的该内衬氧化膜。
6.如权利要求1所述的方法，其中氧化该内衬氮化膜的已曝露部分的步骤包括使用等离子的氧化工序。
7.如权利要求1所述的方法，其中该侧壁氧化膜的厚度在20至200的范围内。
8.如权利要求1所述的方法，其中该内衬氮化膜的厚度在20至100的范围内。
9.如权利要求1所述的方法，其中该内衬氧化膜的厚度在20至200的范围内。
10.如权利要求1所述的方法，其中该平坦化工序包括一CMP工序。
11.如权利要求1所述的方法，其中氧化该内衬氮化膜的已曝露部分的步骤是与使用等离子的HDP氧化膜以形成该间隙填充氧化膜同时实施。
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