TW579593B - Elevated pore phase-change memory - Google Patents
Elevated pore phase-change memory Download PDFInfo
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- TW579593B TW579593B TW091118923A TW91118923A TW579593B TW 579593 B TW579593 B TW 579593B TW 091118923 A TW091118923 A TW 091118923A TW 91118923 A TW91118923 A TW 91118923A TW 579593 B TW579593 B TW 579593B
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- 230000015654 memory Effects 0.000 title claims abstract description 38
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- 239000012782 phase change material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 19
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8616—Thermal insulation means
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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Description
579593 A7 __ B7_ 五、發明説明(1 ) 背景 本發明係大致有關於一種使用相變化材料之記憶體。 相變化材料可呈現至少兩種不同之狀態,該等狀態可 以被稱為非結晶與結晶狀態。在這些狀態間之過度狀態可 依據溫度變化而選擇性地被觸發,這些狀態是可加以區別 的,因該非結晶狀態通常具有比結晶狀態高之電阻,該非 結晶狀態具有一較無次序之原子結構且該結晶狀態具有一 較有久序之原子結構。通常,任何相變化材料均可使用, 但是,在某些實施例中,薄膜硫族化物合金是特別適合者。 該相變化係可逆的,因此,該記憶體可由該非結晶狀 態變化成結晶狀態且可在此之後逆轉回到該非結晶狀態, 並且反之亦然。事實上,各記憶晶胞可被視為一在較高與 較低電阻狀態間可逆變化之可程式化電阻。 在某些情形中,一晶胞可以具有多種狀態,即,因為 各狀態可以由其電阻來區別,故可以是多種電阻決定狀 態’因此可以在一單一晶胞中儲存多數位元。 多種相變化合金是已知的,通常硫族化物合金合有一 或多種來自週期表第VI族之元素,一組特別適合之合金是 GeSbTe合金。 -相變化材料可以形成在-通過―絕緣材料之通道或 孔’該相變化材料可以與在該通道任一端上之接頭輕合。 狀態過渡段可以藉由施加-電流以加熱該相變化材料來產 生。 -存取裝置可以形成在-半導體積體電路之基材中以 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公楚) (請先閲讀背面之注意事項再填寫本頁)
-4- 579593 A7 --------------B7 _ 五、發明説明(2 ) 致動一置於上方之相變化材料,其他相變化記憶體元件也 可結合在該半導體基材中。在結合之構形上形成圖案之結 構會不利地衝擊置於下方之結合結構,因此,在該積體電 路之其餘部份上方,以不會干涉先前製造出之結合結構之 方式形成該相變化記憶體是必要的。 另一個有關相變化記憶體之議題是來自各記憶晶胞之 …、損失愈大,裝置程式化所必須施加之電流也愈大。因此, 必須減少來自該已加熱之相變化材料之熱損失量。類似 地,將熱均勻地分布在該相變化材料上也是必要的。但是 許多目前所提出之方法均會在一程式化動作後產生裝置電 阻之局部變化,這些局部變化亦會在該相變化程式化時在 局部區域中產生應力。 儘可能地減少晶胞之尺寸以減少製造成本將是必要 的,同時,在最大可能範圍内減少製造步驟之數目以減少 成本也是必要的。 因此’需要有一種改良相變化記憶體與用以製造該相 變化記憶體之方法。 圖式之簡箪說明 第1圖是本發明之一實施例之放大橫截面圖;及 第2A至21圖是放大橫截面圖,顯示本發明之一實施例 之用以製造第1圖所示之裝置的方法。 詳細說明 请參閱第1圖’依據本發明之一實施例,一相變化記憶 晶胞10可包括一升高孔,一基材12可包括一積體電路,而 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公楚) (請先閲讀背面之注意事項再填寫本頁)
_5- 579593 A7 ---------Ξ_______ 五、發明説明(3 ) 4積體電路包含一控制通過一基底接頭16之存取電晶體 (圖未不)。一淺槽隔離結構14可隔離該記憶晶胞1〇與形成 在4基材中之其餘結構,依據本發明之一實施例,在該基 材上方的是一内襯導體18,該内襯導體“可以是管狀或杯 狀的且依據本發明之一實施例,可界定出一可充填一填充 絕緣體20之開口中央區域。該内襯導體18將來自該基底接 頭16向上導通至一升高孔。 該升高孔包括一也可以是管狀或杯狀之電阻或下電極 22,在5亥下電極22之内部的是一由一對相對間隔件24與一 相變化層28所界定出的孔。在本發明之一實施例中,該相 變化層28也可以是杯狀的且可以填充有一上電極3〇。在本 發明之一實施例中,該上電極3〇與該相變化層以可以形成 圖案。 請參閱第2A圖,用以形成第丨圖所示之結構之方法係 由形成一通過一蝕刻阻擋層26與一絕緣層32之孔34開始。 该蝕刻阻擋層26可以是由一種相對多種周圍層比較不會被 餘刻之材料所製成者,在一實施例中,該蝕刻阻擋層%可 以是氮化矽或Si3N4。 請參閱第2B圖,在本發明之一實施例中,一内襯導體 18可沈積在該孔34内。在某些實施例中,該内襯導體财 以是鈦、氮化鈦、嫣或這些材料之組合,該内概導體職 墊該圓柱形孔34且可以一填充材料2〇加以填充。有利的 是,該内襯導體18係相配合且一致地覆蓋在該孔“之侧壁 上。該填充材料20提供熱與電絕緣,在一實施例中,該材 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
(請先閲讀背面之注意事項再填寫本頁) 訂 —線· -6- 579593
發明説明 料20可為二氧化矽。 明再參閱第2C圖’第2B圖所示之結構可加以平面化, 在本發明之-實施例中,_化學機械平面化(cMp)製程可 才用來產生以s表示之平坦表面。該蝕刻阻擋層26可以被 用來提供一控制之平面化最後停止點。 如第2D圖所不’該填充材料2〇係受到一具有控制距離 之蝕刻,因此,一開孔36係形成為具有一受控制之深度, 在本發明之一實施例中,該填充材料20之蝕刻係以一乾絕 緣蝕刻來達成,然後可再進行該内襯導體18之蝕刻。在一 實施例中,該内襯導體18可以在具有最小之過度蝕刻之情 形下進行各向同性地蝕刻。在一實施例中,該内襯導體j 8 可以使用一濕蝕刻來蝕刻並且接著蝕刻該填充材料2〇。 接著’在本發明之一實施例中,可以沈積一電阻或下 電極22 ’如第2E圖所示,在該蝕刻阻擋層26之上表面中之 開孔3 6可以被該下電極22覆蓋,接著,該電極22可被一絕 緣體40覆蓋。該下電極22與該内襯導體18電接觸,而該内 襯導體18則再與一在該基材中之接頭16電接觸。 然後,對第2E圖所示之結構進行一平面化製程,如 CMP ’以產生第2F圖所示之平面化結構。接著對該内襯導 體18進行一凹孔蝕刻以產生在e處所示之凹陷區域,在一 實施例中,該凹孔蝕刻可以是一短濕蝕刻。 接者’該絕緣體40可使用一#刻法加以移除,如一乾 或濕絕緣I虫刻以產生以F所示之孔,如第2G圖所示,且該 下電極22被暴露出來。然後,可形成一側壁間隔件24,如 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) …裝丨 •、可i :線丨 579593 五、發明説明(5 ) 第2H圖所示。該間隔件24可以習知之方法形成,例如藉由 沈積一絕緣材料且接著各向異性地蝕刻該沈積之絕緣材料 (請先閲讀背面之注意事項再填寫本頁) 來形成。在一實施例中,該側壁間隔件24可以是氮化矽或 二氧化矽。 然後,如第21圖所示,第2H圖所示之結構可以被一相 變化層28與一上電極層3〇覆蓋,在一實施例中,該相變化 層28呈一杯形且向下延伸至該孔中,而該孔係由在該侧邊 上之間隔件24與在該底部上之下電極22界定出來者。在一 實施例中,該相變化材料可以是Ge2Sb2Te5。 該相變化層28可以是一多層之夾層物,在一實施例 中,該夾層物可包括,由在底部之鈦開始,接著是氮化欽 並且再來是鋁。 :線丨 由在。亥基材12中之底座接頭16開始通過該内襯導體μ 至該下電極22並且接著到達該相變化層28可建立一電連 接,最後,在某些實施例中,該相變化層28與上電極3〇可 以形成圖案以達成第丨圖中料之在某些實施财之結構。 在某些實施例中,將該孔升高至該基材12上方有助於 該相變化記憶晶胞結合於標準互補金屬氧化物半導體 (CMOS)製程流中。特別地,將該孔升高避免在該基材η 中於積體電路構形上形成具圖形之構件。因此照像微影成 像階部可以在平面化之表面上。 在某些實施例中,一熱效率裝置結構係被用來藉由減 〈裝置耘式化所需之電力來改善裝置性能,以相變化層Μ 代表之4可&式之媒體體積係幾乎被熱絕緣物包圍。 本紙張尺細㈣幻 -8- A7 A7 B7 五、發明説明(6 ) (請先閲讀背面之注意事項再填寫本頁) 。亥下電極22提供用以在低電流時產生相變化之熱,在 某些實施例中,該下電極22可以被作成非常薄,藉此減少 通過該電極22之熱損失。此外,在某些實施例中,在程式 化時溫度分布更為均勻,而此可在程式化後使裝置電阻產 生較少之局部變化。在某些實施例中,該結構也可以在產 生相變化時於局部區域中產生較少之應力。 類似地’在某些實施例中,晶胞尺寸可以減少,藉此 可減少產品成本。形成該結構只需要兩外加之加光罩步 驟’因此可減少成本與縮短製程循環時間。 雖然本發明已對於一定數目之實施例加以說明過了, 但是熟習此項技術者可以由此了解多種修改與變化。以下 申明專利範圍係包含在本發明之真正精神與範疇内之所有 的這些修改與變化。 【元件標號對照表】 30…上電極層 32···絕緣層 34···孔 3 6…開孔 40···絕緣體 10…相變化記憶晶胞 12…基材 14…淺槽隔離結構 16…基底接頭 18···内襯導體 20…填充絕緣體;填充材料 22…下電極 24…間隔件 26…蝕刻阻擋層 28···相變化層 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 9·
Claims (1)
- 六、申請專利範圍 第91118923號專利申請案申請專利範圍修正本| 1· 一種製造相變化記憶體的方法,其包含:丨/力£ 在一半導體結構中形成一基底接頭; 以一層覆蓋該半導體結構; 形成一通過該層到該接頭之電連接;及 在該層上方形成一相變化材料,該材料係與該接頭 電氣地搞合。 2.如申請專利範圍第1項之方法 結構包括以至少一絕緣層覆蓋該結構 3·如申請專利範圍第2項之方法 之通道。 4·如申請專利範圍第3項之方法 電連接部。 5·如申請專利範圍第4項之方法, 形成一杯狀電連接部。 6·如申請專利範圍第5項之方法, 狀電連接部。 7·如申請專利範圍第6項之方法, 接部麵合之下電極。 8·如申請專利範圍第7項之方法, 其中以一層覆蓋該半導體 包括形成一通過該絕緣層 包括形成一通過該通道之 其中形成一電連接部包#括 包括以一絕緣體填充該杯 包括形成一與該杯狀電連 包括形成一杯狀下電極。 如申明專利範圍第8項之方法,包括在該杯狀下電極中形 成一側壁間隔件。 如申明專利範圍第9項之方法,其中形成一相變化材料 &括在該絕緣層與該間隔件上沈積一相變化材料並且 與該下電極電接觸。 U·一種相變化記憶體,其包含·· 一半導體結構; 基底接頭,係形成在該半導體結構上; 一絕緣層,係在該半導體結構上方; ——通道,係通過該絕緣層而形成,該通道包括一電 連接部;及 一相變化材料,其係與該電連接部電氣耦合。 12·如申請專利範圍第u項之相變化記憶體,其中該電連接 部呈杯狀。 13·如申請專利範圍第12項之相變化記憶體,包括—下電極。 14·如申請專利範圍第13項之相變化記憶體,包括一在該下 電極上之側壁間隔件。 15·如申請專利範圍第14項之相變化記憶體,其中該相變·化 材料係形成在該侧壁間隔件上方且與該下電極接觸。 16·如申請專利範圍第丨5項之相.變化記憶體,包括一在該杯 狀電連接部内之絕緣材料。 17.如申請專利範圍第16項之相變化記憶體,其中該下電極 呈杯狀。 18·如申請專利範圍第17項之相變化記憶體,其中該下電極 係在該絕緣層之上表面下方凹陷。 19·如申請專利範圍第18項之相變化記憶體,包括一在該相 變化材料上方之上電極。 20·—種相變化記憶體,其包含: 一半導體結構; 一相變化材料,其係與該電連接部電氣耦合;及 一管狀連接器,其係電氣地耦合該相變化材 半“ _。 亥 h如申請專利範圍第2〇項之相變化記憶體,包括_在該半 導體結構上方之絕緣層。 22·如申請專利範圍第21項之相變化記憶體,包括_通過該 絕緣層而形成之通道。 ^ 23·如申請專利範圍第22項之相變化記憶體,其中該通道係 内襯有該管狀連接器。 ' 24_如申請專利範圍第20項之相變化記憶體,包括一下電 極’其係電氣地编合於該相變化材料與該連接器。 女申明專利範圍第24項之相變化記憶體,其中該下電極 呈管狀。 . 26.如申請專利範圍第2〇項之相變化記憶體,其中該連接器 呈杯狀。 27·如申請專利範圍第26項之相變化記憶體,其中該下電極 呈杯狀。 28·如申請專利範圍第27項之相變化記憶體,包括一在該下電 極上方且在該電極與該相變化材料之間的側壁間隔件。 29·如申請專利範圍第28項之相變化記憶體,其中該侧壁間 隔件係定位在該通道内且其中該側壁間隔件呈圓柱形。 30.如申請專利範圍第29項之相變化記憶體,包括一在該相 變化材料上方之上電極。
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- 2002-08-20 WO PCT/US2002/026375 patent/WO2003021693A2/en active Application Filing
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TWI419322B (zh) * | 2007-09-07 | 2013-12-11 | Micron Technology Inc | 多位元儲存之相變記憶體裝置 |
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KR100534530B1 (ko) | 2005-12-07 |
JP2005525690A (ja) | 2005-08-25 |
WO2003021693A3 (en) | 2003-11-13 |
US6764894B2 (en) | 2004-07-20 |
WO2003021693A2 (en) | 2003-03-13 |
US7326952B2 (en) | 2008-02-05 |
JP4150667B2 (ja) | 2008-09-17 |
KR20040032955A (ko) | 2004-04-17 |
US20040202033A1 (en) | 2004-10-14 |
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