JP4150667B2 - ポアの位置を高くした相変化型メモリ - Google Patents
ポアの位置を高くした相変化型メモリ Download PDFInfo
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- JP4150667B2 JP4150667B2 JP2003525922A JP2003525922A JP4150667B2 JP 4150667 B2 JP4150667 B2 JP 4150667B2 JP 2003525922 A JP2003525922 A JP 2003525922A JP 2003525922 A JP2003525922 A JP 2003525922A JP 4150667 B2 JP4150667 B2 JP 4150667B2
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- cup
- electrical connection
- phase change
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8616—Thermal insulation means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
Description
Claims (2)
- 半導体構造基板内にベースコンタクトを形成するステップと、
該半導体構造基板を絶縁層により被覆するステップと、
該層を貫通する微細孔を形成し、該微細穴中に、その底面が前記ベースコンタクト表面に接触するカップ状電気的接続を形成するステップと、
該カップ状電気的接続の内側に絶縁体を積層した後、前記カップ状電気的接続の側壁部上面と前記絶縁体の上面とが平坦面を構成するように平坦化処理を行うステップと、
前記絶縁層に形成された微細孔内側の壁面、並びに前記カップ状電気的接続の上面と前記絶縁体の上面とからなる平坦面を覆い、該カップ状電気的接続に電気的に結合するカップ状下部電極を形成するステップと、
前記絶縁層、及び前記カップ状下部電極を覆い、前記カップ状下部電極と前記カップ状電気的接続とを介して前記ベースコンタクトに電気的に結合する相変化層を形成するステップと、
前記相変化層を覆う上部電極を形成するステップと
を含んでなる、半導体メモリの製造方法。 - 半導体構造基板と、
該半導体構造基板上に形成されたベースコンタクトと、
該半導体構造基板を上から覆う絶縁層と、
該絶縁層を貫通する微細孔中に形成され、その底面が前記ベースコンタクト表面に接触するカップ状電気的接続部と、
前記カップ状電気的接続の内側に形成され、その上面と前記カップ状電気的接続の側壁部上面とが平坦面を構成する絶縁体と、
前記絶縁層に形成された微細孔内側の壁面、並びに前記カップ状電気的接続の上面と前記絶縁体の上面とからなる平坦面を覆い、前記カップ状電気的接続に電気的に結合するカップ状下部電極と、
前記絶縁層、及び前記カップ状下部電極を覆い、前記電気的接続部と前記カップ状下部電極とを介して前記ベースコンタクトに電気的に結合した相変化層と、
前記相変化層を覆う上部電極と
を含んでなる、半導体メモリ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/944,478 US6764894B2 (en) | 2001-08-31 | 2001-08-31 | Elevated pore phase-change memory |
PCT/US2002/026375 WO2003021693A2 (en) | 2001-08-31 | 2002-08-20 | Elevated pore phase-change memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005525690A JP2005525690A (ja) | 2005-08-25 |
JP4150667B2 true JP4150667B2 (ja) | 2008-09-17 |
Family
ID=25481474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003525922A Expired - Fee Related JP4150667B2 (ja) | 2001-08-31 | 2002-08-20 | ポアの位置を高くした相変化型メモリ |
Country Status (5)
Country | Link |
---|---|
US (2) | US6764894B2 (ja) |
JP (1) | JP4150667B2 (ja) |
KR (1) | KR100534530B1 (ja) |
TW (1) | TW579593B (ja) |
WO (1) | WO2003021693A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8580606B2 (en) | 2010-12-03 | 2013-11-12 | Samsung Electronics Co., Ltd. | Method of forming resistance variable memory device |
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US8580606B2 (en) | 2010-12-03 | 2013-11-12 | Samsung Electronics Co., Ltd. | Method of forming resistance variable memory device |
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TW579593B (en) | 2004-03-11 |
JP2005525690A (ja) | 2005-08-25 |
US7326952B2 (en) | 2008-02-05 |
US6764894B2 (en) | 2004-07-20 |
KR20040032955A (ko) | 2004-04-17 |
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KR100534530B1 (ko) | 2005-12-07 |
WO2003021693A2 (en) | 2003-03-13 |
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